blob: 728dfef1867627860d1a0c808404d727312aafaf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* camss-csiphy.h
*
* Qualcomm MSM Camera Subsystem - CSIPHY Module
*
* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
* Copyright (C) 2016-2018 Linaro Ltd.
*/
#ifndef QC_MSM_CAMSS_CSIPHY_H
#define QC_MSM_CAMSS_CSIPHY_H
#include <linux/clk.h>
#include <media/media-entity.h>
#include <media/v4l2-device.h>
#include <media/v4l2-mediabus.h>
#include <media/v4l2-subdev.h>
#define MSM_CSIPHY_PAD_SINK 0
#define MSM_CSIPHY_PAD_SRC 1
#define MSM_CSIPHY_PADS_NUM 2
struct csiphy_lane {
u8 pos;
u8 pol;
};
struct csiphy_lanes_cfg {
int num_data;
struct csiphy_lane *data;
struct csiphy_lane clk;
};
struct csiphy_csi2_cfg {
struct csiphy_lanes_cfg lane_cfg;
};
struct csiphy_config {
u8 combo_mode;
u8 csid_id;
struct csiphy_csi2_cfg *csi2;
};
struct csiphy_device {
struct camss *camss;
u8 id;
struct v4l2_subdev subdev;
struct media_pad pads[MSM_CSIPHY_PADS_NUM];
void __iomem *base;
void __iomem *base_clk_mux;
u32 irq;
char irq_name[30];
struct camss_clock *clock;
int nclocks;
u32 timer_clk_rate;
struct csiphy_config cfg;
struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM];
};
struct resources;
int msm_csiphy_subdev_init(struct camss *camss,
struct csiphy_device *csiphy,
const struct resources *res, u8 id);
int msm_csiphy_register_entity(struct csiphy_device *csiphy,
struct v4l2_device *v4l2_dev);
void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
#endif /* QC_MSM_CAMSS_CSIPHY_H */
|
