summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi
blob: d7ad769a42fcbdc2548789dc08dc50bc3e506439 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm3384", "brcm,bcm33843";

	memory@0 {
		device_type = "memory";

		/* Typical range.  The bootloader should fill this in. */
		reg = <0x0 0x08000000>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* On BMIPS5000 this is 1/8th of the CPU core clock */
		mips-hpt-frequency = <100000000>;

		cpu@0 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <1>;
		};
	};

	cpu_intc: cpu_intc {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	clocks {
		periph_clk: periph_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <54000000>;
		};
	};

	aliases {
		uart0 = &uart0;
	};

	ubus {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "brcm,ubus", "simple-bus";
		ranges;
		dma-ranges = <0x00000000 0x08000000 0x08000000>,
			     <0x08000000 0x00000000 0x08000000>;

		periph_intc: periph_intc@14e00038 {
			compatible = "brcm,bcm3380-l2-intc";
			reg = <0x14e00038 0x4 0x14e0003c 0x4>,
			      <0x14e00340 0x4 0x14e00344 0x4>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <4>;
		};

		zmips_intc: zmips_intc@104b0060 {
			compatible = "brcm,bcm3380-l2-intc";
			reg = <0x104b0060 0x4 0x104b0064 0x4>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <29>;
			brcm,int-map-mask = <0xffffffff>;
		};

		iop_intc: iop_intc@14e00058 {
			compatible = "brcm,bcm3380-l2-intc";
			reg = <0x14e00058 0x4 0x14e0005c 0x4>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <6>;
			brcm,int-map-mask = <0xffffffff>;
		};

		uart0: serial@14e00520 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x14e00520 0x18>;
			interrupt-parent = <&periph_intc>;
			interrupts = <2>;
			clocks = <&periph_clk>;
			status = "disabled";
		};

		ehci0: usb@15400300 {
			compatible = "brcm,bcm3384-ehci", "generic-ehci";
			reg = <0x15400300 0x100>;
			big-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <41>;
			status = "disabled";
		};

		ohci0: usb@15400400 {
			compatible = "brcm,bcm3384-ohci", "generic-ohci";
			reg = <0x15400400 0x100>;
			big-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <40>;
			status = "disabled";
		};
	};
};