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/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/clock/bcm-sr.h>
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
crmu_ref25m: crmu_ref25m {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&osc>;
clock-div = <2>;
clock-mult = <1>;
};
genpll0: genpll0@1d104 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll0";
reg = <0x0001d104 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll0", "clk_125m", "clk_scr",
"clk_250", "clk_pcie_axi",
"clk_paxc_axi_x2",
"clk_paxc_axi";
};
genpll2: genpll2@1d1ac {
#clock-cells = <1>;
compatible = "brcm,sr-genpll2";
reg = <0x0001d1ac 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll2", "clk_nic",
"clk_ts_500_ref", "clk_125_nitro",
"clk_chimp", "clk_nic_flash",
"clk_fs";
};
genpll3: genpll3@1d1e0 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll3";
reg = <0x0001d1e0 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll3", "clk_hsls",
"clk_sdio";
};
genpll4: genpll4@1d214 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll4";
reg = <0x0001d214 0x32>,
<0x0001c854 0x4>;
clocks = <&osc>;
clock-output-names = "genpll4", "clk_ccn",
"clk_tpiu_pll", "clk_noc",
"clk_chclk_fs4",
"clk_bridge_fscpu";
};
genpll5: genpll5@1d248 {
#clock-cells = <1>;
compatible = "brcm,sr-genpll5";
reg = <0x0001d248 0x32>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "genpll5", "clk_fs4_hf",
"clk_crypto_ae", "clk_raid_ae";
};
lcpll0: lcpll0@1d0c4 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll0";
reg = <0x0001d0c4 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll0", "clk_sata_refp",
"clk_sata_refn", "clk_sata_350",
"clk_sata_500";
};
lcpll1: lcpll1@1d138 {
#clock-cells = <1>;
compatible = "brcm,sr-lcpll1";
reg = <0x0001d138 0x3c>,
<0x0001c870 0x4>;
clocks = <&osc>;
clock-output-names = "lcpll1", "clk_wan",
"clk_usb_ref",
"clk_crmu_ts";
};
hsls_clk: hsls_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 1>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_div2_clk: hsls_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <2>;
clock-mult = <1>;
};
hsls_div4_clk: hsls_div4_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
clock-div = <4>;
clock-mult = <1>;
};
hsls_25m_clk: hsls_25m_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&crmu_ref25m>;
clock-div = <1>;
clock-mult = <1>;
};
hsls_25m_div2_clk: hsls_25m_div2_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&hsls_25m_clk>;
clock-div = <2>;
clock-mult = <1>;
};
sdio0_clk: sdio0_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};
sdio1_clk: sdio1_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
clock-div = <1>;
clock-mult = <1>;
};
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