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|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom SPI controller
maintainers:
- Kamal Dasu <kdasu.kdev@gmail.com>
- Rafał Miłecki <rafal@milecki.pl>
description: |
The Broadcom SPI controller is a SPI master found on various SOCs, including
BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
of:
MSPI : SPI master controller can read and write to a SPI slave device
BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
for flash reads and be configured to do single, double, quad lane
io with 3-byte and 4-byte addressing support.
Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
of a MSPI master without the BSPI to use with non flash slave devices that
use SPI protocol.
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
oneOf:
- description: Second Instance of MSPI BRCMSTB SoCs
items:
- enum:
- brcm,spi-bcm7425-qspi
- brcm,spi-bcm7429-qspi
- brcm,spi-bcm7435-qspi
- brcm,spi-bcm7445-qspi
- brcm,spi-bcm7216-qspi
- brcm,spi-bcm7278-qspi
- const: brcm,spi-bcm-qspi
- const: brcm,spi-brcmstb-mspi
- description: Second Instance of MSPI BRCMSTB SoCs
items:
- enum:
- brcm,spi-brcmstb-qspi
- brcm,spi-brcmstb-mspi
- brcm,spi-nsp-qspi
- brcm,spi-ns2-qspi
- const: brcm,spi-bcm-qspi
reg:
minItems: 1
maxItems: 5
reg-names:
minItems: 1
items:
- const: mspi
- const: bspi
- enum: [ intr_regs, intr_status_reg, cs_reg ]
- enum: [ intr_regs, intr_status_reg, cs_reg ]
- enum: [ intr_regs, intr_status_reg, cs_reg ]
interrupts:
minItems: 1
maxItems: 7
interrupt-names:
oneOf:
- minItems: 1
items:
- const: mspi_done
- const: mspi_halted
- const: spi_lr_fullness_reached
- const: spi_lr_session_aborted
- const: spi_lr_impatient
- const: spi_lr_session_done
- const: spi_lr_overread
- const: spi_l1_intr
clocks:
maxItems: 1
description: reference clock for this block
native-endian:
$ref: /schemas/types.yaml#/definitions/flag
description: Defined when using BE SoC and device uses BE register read/write
unevaluatedProperties: false
required:
- reg
- reg-names
- interrupts
- interrupt-names
examples:
- | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
spi@f03e3400 {
compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
reg-names = "mspi", "bspi", "cs_reg";
interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
interrupt-parent = <&gic>;
interrupt-names = "mspi_done",
"mspi_halted",
"spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread";
clocks = <&hif_spi>;
#address-cells = <0x1>;
#size-cells = <0x0>;
flash@0 {
#size-cells = <0x2>;
#address-cells = <0x2>;
compatible = "m25p80";
reg = <0x0>;
spi-max-frequency = <0x2625a00>;
spi-cpol;
spi-cpha;
};
};
- | # BRCMSTB SoC: MSPI master for any SPI device
spi@f0416000 {
clocks = <&upg_fixed>;
compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
reg = <0xf0416000 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&irq0_aon_intc>;
interrupt-names = "mspi_done";
#address-cells = <1>;
#size-cells = <0>;
};
- | # iProc SoC
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@18027200 {
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
reg = <0x18027200 0x184>,
<0x18027000 0x124>,
<0x1811c408 0x004>,
<0x180273a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mspi_done",
"mspi_halted",
"spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done";
clocks = <&iprocmed>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
- | # NS2 SoC
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
spi@66470200 {
compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
reg = <0x66470200 0x184>,
<0x66470000 0x124>,
<0x67017408 0x004>,
<0x664703a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "spi_l1_intr";
clocks = <&iprocmed>;
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p80";
reg = <0x0>;
spi-max-frequency = <12500000>;
spi-cpol;
spi-cpha;
};
};
|
