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BMC/Intel-BMC/linux.git
dev
dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
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path:
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include
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asm-sh
/
cpu-sh5
Age
Commit message (
Expand
)
Author
Files
Lines
2008-02-14
sh: Kill off more dead symbols.
Paul Mundt
1
-6
/
+0
2008-02-14
sh: Get SH-5 caches working again post-unification.
Paul Mundt
1
-3
/
+1
2008-02-14
sh: Update SH-5 flush_cache_sigtramp() for API changes.
Paul Mundt
1
-1
/
+1
2008-01-28
sh: comment tidying for sh64->sh migration.
Paul Mundt
4
-27
/
+25
2008-01-28
rtc: rtc-sh: Split out the CPU defs to asm/cpu/.
Paul Mundt
1
-0
/
+8
2008-01-28
sh: Get the mach-cayman IRQ support building.
Paul Mundt
1
-27
/
+1
2008-01-28
sh: Kill off the last of the sh64 headers.
Paul Mundt
2
-0
/
+149
2008-01-28
sh: Nopped out p3_cache_init() on SH-5 also.
Paul Mundt
1
-0
/
+1
2008-01-28
sh: timer.h stub for SH-5.
Paul Mundt
1
-0
/
+4
2008-01-28
sh: More SH-5 cpuinfo tidying.
Paul Mundt
1
-0
/
+4
2008-01-28
sh: Move in the SH-5 mmu_context headers.
Paul Mundt
1
-0
/
+27
2008-01-28
sh: Split out irqflags.h in to _32 and _64 variants.
Paul Mundt
1
-0
/
+106
2008-01-28
sh: Add in cacheflush and DMA headers for SH-5.
Paul Mundt
2
-0
/
+40
2008-01-28
sh: Add cache definitions for SH-5.
Paul Mundt
1
-0
/
+94
2008-01-28
sh: Add addrspace.h segmentation stub for SH-5.
Paul Mundt
1
-0
/
+6