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2021-12-22soc/tegra: fuse: Fix bitwise vs. logical OR warningNathan Chancellor2-2/+2
[ Upstream commit a7083763619f7485ccdade160deb81737cf2732f ] A new warning in clang points out two instances where boolean expressions are being used with a bitwise OR instead of logical OR: drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical] reg = tegra_fuse_read_spare(i) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ || drivers/soc/tegra/fuse/speedo-tegra20.c:72:9: note: cast one or both operands to int to silence this warning drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical] reg = tegra_fuse_read_spare(i) | ^~~~~~~~~~~~~~~~~~~~~~~~~~ || drivers/soc/tegra/fuse/speedo-tegra20.c:87:9: note: cast one or both operands to int to silence this warning 2 warnings generated. The motivation for the warning is that logical operations short circuit while bitwise operations do not. In this instance, tegra_fuse_read_spare() is not semantically returning a boolean, it is returning a bit value. Use u32 for its return type so that it can be used with either bitwise or boolean operators without any warnings. Fixes: 25cd5a391478 ("ARM: tegra: Add speedo-based process identification") Link: https://github.com/ClangBuiltLinux/linux/issues/1488 Suggested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-08-11soc/tegra: fuse: Enable fuse clock on suspend for Tegra124Dmitry Osipenko4-0/+39
The FUSE clock should be enabled during suspend on Tegra124. Currently clk driver enables it on all SoCs, but FUSE may require a higher core voltage on Tegra30 while enabled. Move the quirk into the FUSE driver and make it specific to Tegra124. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-11soc/tegra: fuse: Add runtime PM supportDmitry Osipenko3-9/+40
The Tegra FUSE belongs to the core power domain and we're going to enable GENPD support for the core domain. Now FUSE device must be resumed using runtime PM API in order to initialize the FUSE power state. Add runtime PM support to the FUSE driver. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-11soc/tegra: fuse: Clear fuse->clk on driver probe failureDmitry Osipenko1-0/+1
The fuse->clk must be cleared if FUSE driver fails to probe, otherwise tegra_fuse_readl() will crash. It's unlikely to happen in practice, nevertheless let's correct it for completeness. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11soc/tegra: fuse: Fix Tegra234-only buildsThierry Reding1-1/+2
The tegra30_fuse_read() symbol is used on Tegra234, so make sure it's available. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-02soc/tegra: fuse: Don't return -ENOMEM when allocate lookups failedYang Yingliang1-4/+2
fuse->base can not be unmapped if allocate lookups failed in tegra_init_fuse(), because it is an early_initcall, the driver will be loaded anyway and fuse->base will be accessed by other functions later, so remove the return -ENOMEM after allocating lookups failed to make less confusing. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> [treding@nvidia.com: drop error message, out-of-memory is noisy anyway] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-27Merge tag 'tegra-for-5.11-soc' of ↵Arnd Bergmann2-21/+8
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.11-rc1 This contains a couple of warning fixes and a fix for a mostly harmless bug in the process ID retrieval code. * tag 'tegra-for-5.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: fuse: Fix index bug in get_process_id soc: tegra: fuse: speedo-tegra210: Remove a group of set but unused variables soc: tegra: fuse: speedo-tegra124: Remove some set but unused variables Link: https://lore.kernel.org/r/20201127144329.124891-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-11-19soc/tegra: fuse: Fix index bug in get_process_idNicolin Chen1-1/+1
This patch simply fixes a bug of referencing speedos[num] in every for-loop iteration in get_process_id function. Fixes: 0dc5a0d83675 ("soc/tegra: fuse: Add Tegra210 support") Cc: <stable@vger.kernel.org> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-10soc: tegra: fuse: speedo-tegra210: Remove a group of set but unused variablesLee Jones1-5/+1
Fixes the following W=1 kernel build warning(s): drivers/soc/tegra/fuse/speedo-tegra210.c: In function ‘tegra210_init_speedo_data’: drivers/soc/tegra/fuse/speedo-tegra210.c:105:56: warning: variable ‘soc_iddq’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra210.c:105:46: warning: variable ‘gpu_iddq’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra210.c:105:36: warning: variable ‘cpu_iddq’ set but not used [-Wunused-but-set-variable] Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> [treding@nvidia.com: remove unnecessary reads altogether] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-10soc: tegra: fuse: speedo-tegra124: Remove some set but unused variablesLee Jones1-15/+6
Fixes the following W=1 kernel build warning(s): drivers/soc/tegra/fuse/speedo-tegra124.c: In function ‘tegra124_init_speedo_data’: drivers/soc/tegra/fuse/speedo-tegra124.c:105:38: warning: variable ‘soc_iddq_value’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra124.c:105:22: warning: variable ‘gpu_iddq_value’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra124.c:105:6: warning: variable ‘cpu_iddq_value’ set but not used [-Wunused-but-set-variable] Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> [treding@nvidia.com: remove unnecessary reads altogether] Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-06soc/tegra: fuse: Export tegra_read_ram_code()Dmitry Osipenko1-0/+2
The tegra_read_ram_code() is used by EMC drivers and we're going to make these driver modular, hence this function needs to be exported. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201104164923.21238-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-09-18soc/tegra: misc: Add Tegra234 supportThierry Reding1-0/+1
The MISC block is largely similar to that found on earlier chips, but not completely compatible. Allow binding to the instantiation found on Tegra234. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Add Tegra234 supportThierry Reding4-2/+45
Add support for FUSE block found on the Tegra234 SoC, which is largely similar to the IP found on previous generations. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Implement tegra_is_silicon()Thierry Reding1-0/+19
This function can be used by drivers to determine whether code is running on silicon or on a simulation platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-18soc/tegra: fuse: Extract tegra_get_platform()Thierry Reding2-1/+6
This function extracts the PRE_SI_PLATFORM field from the HIDREV register and can be used to determine which platform the kernel runs on (silicon, simulation, ...). Note that while only Tegra194 and later define this field, it should be safe to call this on prior generations as well since this field should read as 0, indicating silicon. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-07-17soc/tegra: fuse: Fix typo in APB MISC warningThierry Reding1-1/+1
The hardware block is called APB MISC, not ABP MISC, so fix the warning to use the correct name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-04-22soc/tegra: fuse: Update the SoC revision attribute to display a nameJon Hunter1-1/+2
Currently the SoC revision attribute for Tegra devices displays the value of the enum associated with a particular revision. This is not very useful because to obtain the actual revision you need to use the tegra_revision enumeration to translate the value. It is more meaningful to display a name for the revision, such as 'A01', than the enumarated value and therefore, update the revision attribute to display a name. This change does alter the ABI, which is unfortunate, but this is more meaningful and maintable. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-04-22soc/tegra: fuse: Trivial clean-up of tegra_init_revision()Jon Hunter1-13/+9
Clean-up the tegra_init_revision() function by removing the 'rev' variable which is not needed and use the newly added helper function tegra_get_minor_rev() to get the minor revision. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-04-22soc/tegra: fuse: Add custom SoC attributesJon Hunter5-0/+79
Add a custom SoC attribute for Tegra to expose the HIDREV register fields to userspace via the sysfs. This register provides additional details about the type of device (eg, silicon, FPGA, etc) as well as revision. Exposing this information is useful for identifying the exact device revision and device type. For Tegra devices up until Tegra186, the majorrev and minorrev fields of the HIDREV register are used to determine the device revision and device type. For Tegra194, the majorrev and minorrev fields only determine the revision. Starting with Tegra194, there is an additional field, pre_si_platform (which occupies bits 20-23), that now determines device type. Therefore, for all Tegra devices, add a custom SoC attribute for the majorrev and minorrev fields and for Tegra194 add an additional attribute for the pre_si_platform field. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-02-12soc/tegra: fuse: Fix build with Tegra194 configurationThierry Reding1-1/+2
If only Tegra194 support is enabled, the tegra30_fuse_read() and tegra30_fuse_init() function are not declared and cause a build failure. Add Tegra194 to the preprocessor guard to make sure these functions are available for Tegra194-only builds as well. Link: https://lore.kernel.org/r/20200203143114.3967295-1-thierry.reding@gmail.com Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-02-09Merge tag 'armsoc-drivers' of ↵Linus Torvalds4-14/+56
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms: - Nvidia: Fuse support for Tegra194, continued memory controller pieces for Tegra30 - NXP/FSL: Refactorings of QuickEngine drivers to support ARM/ARM64/PPC - NXP/FSL: i.MX8MP SoC driver pieces - TI Keystone: ring accelerator driver - Qualcomm: SCM driver cleanup/refactoring + support for new SoCs. - Xilinx ZynqMP: feature checking interface for firmware. Mailbox communication for power management - Overall support patch set for cpuidle on more complex hierarchies (PSCI-based) and misc cleanups, refactorings of Marvell, TI, other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits) drivers: soc: xilinx: Use mailbox IPI callback dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists MAINTAINERS: Add brcmstb PCIe controller entry soc/tegra: fuse: Unmap registers once they are not needed anymore soc/tegra: fuse: Correct straps' address for older Tegra124 device trees soc/tegra: fuse: Warn if straps are not ready soc/tegra: fuse: Cache values of straps and Chip ID registers memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence soc/tegra: regulators: Do nothing if voltage is unchanged memory: tegra: Correct reset value of xusb_hostr soc/tegra: fuse: Add APB DMA dependency for Tegra20 bus: tegra-aconnect: Remove PM_CLK dependency dt-bindings: mediatek: add MT6765 power dt-bindings soc: mediatek: cmdq: delete not used define memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later ...
2020-01-10soc/tegra: fuse: Unmap registers once they are not needed anymoreDmitry Osipenko1-4/+8
Both Chip ID and strapping registers are now read out during of APB MISC initialization, the registers' mapping isn't needed anymore once registers are read. Hence let's unmap registers once they are not needed anymore, for consistency. Suggested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10soc/tegra: fuse: Correct straps' address for older Tegra124 device treesDmitry Osipenko1-1/+1
Trying to read out Chip ID before APBMISC registers are mapped won't succeed, in a result Tegra124 gets a wrong address for the HW straps register if machine uses an old outdated device tree. Fixes: 297c4f3dcbff ("soc/tegra: fuse: Restrict legacy code to 32-bit ARM") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10soc/tegra: fuse: Warn if straps are not readyDmitry Osipenko1-1/+3
Now both Chip ID and HW straps are becoming available at the same time, thus we could simply check the availability of the ID in order to check the availability of the straps. We couldn't check straps for 0x0 because it could be a correct value. This change didn't uncover any problems, but anyways it is nicer to have straps verified for consistency with the Chip ID verification. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-10soc/tegra: fuse: Cache values of straps and Chip ID registersDmitry Osipenko1-11/+10
There is no need to re-read Chip ID and HW straps out from hardware each time, it is a bit nicer to cache the values in memory. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-09soc/tegra: fuse: Add Tegra194 supportJC Kuo4-0/+37
This commit adds Tegra194 fuse/apbmisc support. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-01-06remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig2-3/+3
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
2019-10-16soc/tegra: fuse: Register cell lookups for compatibilityThierry Reding3-0/+168
Typically nvmem cells would be stored in device tree. However, for compatibility with device trees that don't contain nvmem cell definitions, register lookups for cells currently used by consumers. This allows the consumers to use the same API to query cells from the device tree or using the legacy mechanism. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-16soc/tegra: fuse: Add cell informationThierry Reding1-0/+90
Create nvmem cells for all the fuses currently used by consumers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-16soc/tegra: fuse: Implement nvmem deviceThierry Reding2-47/+38
The nvmem framework provides a generic infrastructure and API to access the type of information stored in fuses such as the Tegra FUSE block. Implement an nvmem device that can be used to access the information in a more generic way to decouple consumers from the custom Tegra API and to add a more formal way of creating the dependency between the FUSE device and the consumers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-16soc/tegra: fuse: Restore base on sysfs failureThierry Reding1-6/+10
Make sure to also restore the register base address on sysfs registration failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-01soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl()Nagarjuna Kristam1-1/+4
tegra_fuse_readl() can be called from drivers at any time. If this API is called before tegra_fuse_probe(), we end up enabling the clock before it is registered. Add a check for the FUSE clock in tegra_fuse_readl() and propagate any errors. Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-07-20Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-2/+4
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: - A driver for SCU (system control) on NXP i.MX8QXP - Qualcomm Always-on Subsystem messaging driver (AOSS QMP) - Qualcomm PM support for MSM8998 - Support for a newer version of DRAM PHY driver for Broadcom (DPFE) - Reset controller support for Bitmain BM1880 - TI SCI (System Control Interface) support for CPU control on AM654 processors - More TI sysc refactoring and rework" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits) reset: remove redundant null check on pointer dev soc: rockchip: work around clang warning dt-bindings: reset: imx7: Fix the spelling of 'indices' soc: imx: Add i.MX8MN SoC driver support soc: aspeed: lpc-ctrl: Fix probe error handling soc: qcom: geni: Add support for ACPI firmware: ti_sci: Fix gcc unused-but-set-variable warning firmware: ti_sci: Use the correct style for SPDX License Identifier soc: imx8: Use existing of_root directly soc: imx8: Fix potential kernel dump in error path firmware/psci: psci_checker: Park kthreads before stopping them memory: move jedec_ddr.h from include/memory to drivers/memory/ memory: move jedec_ddr_data.c from lib/ to drivers/memory/ MAINTAINERS: Remove myself as qcom maintainer soc: aspeed: lpc-ctrl: make parameter optional soc: qcom: apr: Don't use reg for domain id soc: qcom: fix QCOM_AOSS_QMP dependency and build errors memory: tegra: Fix -Wunused-const-variable firmware: tegra: Early resume BPMP soc/tegra: Select pinctrl for Tegra194 ...
2019-07-17Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-1/+1
Pull dmaengine updates from Vinod Koul: - Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers * tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits) dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support" dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback Documentation: dmaengine: clean up description of dmatest usage dmaengine: tegra210-adma: remove PM_CLK dependency dmaengine: fsl-edma: add i.mx7ulp edma2 version support dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma dmaengine: fsl-edma-common: version check for v2 instead dmaengine: fsl-edma-common: move dmamux register to another single function dmaengine: fsl-edma: add drvdata for fsl-edma dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver" dmaengine: rcar-dmac: Reject zero-length slave DMA requests dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw-edma: fix semicolon.cocci warnings dmaengine: sh: usb-dmac: Use [] to denote a flexible array member dmaengine: dmatest: timeout value of -1 should specify infinite wait dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit dmaengine: fsl-edma: support little endian for edma driver dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" dmagengine: pl330: add code to get reset property dt-bindings: pl330: document the optional resets property ...
2019-06-25Merge tag 'tegra-for-5.3-soc' of ↵Olof Johansson1-2/+4
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc: tegra: Changes for v5.3-rc1 This contains a set of minor fixes and cleanups for core Tegra drivers. * tag 'tegra-for-5.3-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: Select pinctrl for Tegra194 soc/tegra: fuse: Do not log error message on deferred probe soc/tegra: pmc: Add comments clarifying wake events soc/tegra: pmc: Avoid crash for non-wake IRQs soc/tegra: pmc: Fail to allocate more than one wake IRQ Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-10/+1
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-05soc/tegra: fuse: Do not log error message on deferred probeThierry Reding1-2/+4
Recent changes have made it much more probable that clocks are not available yet when the FUSE driver is first probed. However, that is a situation that the driver can cope with just fine. To avoid confusion, don't output an error when this happens. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner9-111/+9
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-27soc: tegra: fuse: Use dma_request_channel instead of __dma_request_channel()Baolin Wang1-1/+1
The __dma_request_channel() prototype has been changed to help to do device node validation, thus we can use dma_request_channel() instead of __dma_request_channel() to keep kernel bisectable. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-01-25soc/tegra: fuse: Fix typo in tegra210_init_speedo_dataJoseph Lo1-1/+1
Fix typo when reading SoC speedo value from fuse SoC speedo register. Reported-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-01-25soc/tegra: fuse: Fix illegal free of IO base addressTimo Alho1-3/+9
On cases where device tree entries for fuse and clock provider are in different order, fuse driver needs to defer probing. This leads to freeing incorrect IO base address as the fuse->base variable gets overwritten once during first probe invocation. This leads to the following spew during boot: [ 3.082285] Trying to vfree() nonexistent vm area (00000000cfe8fd94) [ 3.082308] WARNING: CPU: 5 PID: 126 at /hdd/l4t/kernel/stable/mm/vmalloc.c:1511 __vunmap+0xcc/0xd8 [ 3.082318] Modules linked in: [ 3.082330] CPU: 5 PID: 126 Comm: kworker/5:1 Tainted: G S 4.19.7-tegra-gce119d3 #1 [ 3.082340] Hardware name: quill (DT) [ 3.082353] Workqueue: events deferred_probe_work_func [ 3.082364] pstate: 40000005 (nZcv daif -PAN -UAO) [ 3.082372] pc : __vunmap+0xcc/0xd8 [ 3.082379] lr : __vunmap+0xcc/0xd8 [ 3.082385] sp : ffff00000a1d3b60 [ 3.082391] x29: ffff00000a1d3b60 x28: 0000000000000000 [ 3.082402] x27: 0000000000000000 x26: ffff000008e8b610 [ 3.082413] x25: 0000000000000000 x24: 0000000000000009 [ 3.082423] x23: ffff000009221a90 x22: ffff000009f6d000 [ 3.082432] x21: 0000000000000000 x20: 0000000000000000 [ 3.082442] x19: ffff000009f6d000 x18: ffffffffffffffff [ 3.082452] x17: 0000000000000000 x16: 0000000000000000 [ 3.082462] x15: ffff0000091396c8 x14: 0720072007200720 [ 3.082471] x13: 0720072007200720 x12: 0720072907340739 [ 3.082481] x11: 0764076607380765 x10: 0766076307300730 [ 3.082491] x9 : 0730073007300730 x8 : 0730073007280720 [ 3.082501] x7 : 0761076507720761 x6 : 0000000000000102 [ 3.082510] x5 : 0000000000000000 x4 : 0000000000000000 [ 3.082519] x3 : ffffffffffffffff x2 : ffff000009150ff8 [ 3.082528] x1 : 3d95b1429fff5200 x0 : 0000000000000000 [ 3.082538] Call trace: [ 3.082545] __vunmap+0xcc/0xd8 [ 3.082552] vunmap+0x24/0x30 [ 3.082561] __iounmap+0x2c/0x38 [ 3.082569] tegra_fuse_probe+0xc8/0x118 [ 3.082577] platform_drv_probe+0x50/0xa0 [ 3.082585] really_probe+0x1b0/0x288 [ 3.082593] driver_probe_device+0x58/0x100 [ 3.082601] __device_attach_driver+0x98/0xf0 [ 3.082609] bus_for_each_drv+0x64/0xc8 [ 3.082616] __device_attach+0xd8/0x130 [ 3.082624] device_initial_probe+0x10/0x18 [ 3.082631] bus_probe_device+0x90/0x98 [ 3.082638] deferred_probe_work_func+0x74/0xb0 [ 3.082649] process_one_work+0x1e0/0x318 [ 3.082656] worker_thread+0x228/0x450 [ 3.082664] kthread+0x128/0x130 [ 3.082672] ret_from_fork+0x10/0x18 [ 3.082678] ---[ end trace 0810fe6ba772c1c7 ]--- Fix this by retaining the value of fuse->base until driver has successfully probed. Signed-off-by: Timo Alho <talho@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21soc/tegra: fuse: Explicitly request DMA channel from APB DMA driverDmitry Osipenko1-1/+8
Currently fuse driver requests DMA channel from an arbitrary DMA device, it is not a problem since there is only one DMA provider for Tegra20 yet, but it may become troublesome if another provider will appear. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21soc/tegra: fuse: Fix reading registers using DMA on Tegra20Dmitry Osipenko2-1/+4
FUSE driver doesn't configure DMA channel properly, because of it DMA transfer is never issued and tegra20_fuse_read() always return 0x0. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Add Tegra186 chip ID supportThierry Reding1-0/+1
The register region containing chip ID information has been relocated in Tegra186 and changed in backwards-incompatible ways. Add a compatible string to allow the driver to make the distinction. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Warn if accessing unmapped registersThierry Reding1-0/+3
If the FUSE registers are accessed but the region is not mapped, warn and return 0. This potentially catches hard to diagnose bugs because the accesses happen before any kernel log output. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Move register mapping checkThierry Reding1-5/+5
The tegra_read_chipid() function can be called from places other than tegra_get_chip_id(), so the check for a valid mapping of the MISC registers needs to be moved to tegra_read_chipid() to catch all potential accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13soc/tegra: fuse: Add Tegra186 supportTimo Alho3-2/+26
Tegra210 and Tegra186 are mostly compatible from a fuses point of view. However, speedo support is implemented in the BPMP firmware, hence the implementation needs to be skipped in the fuses driver. Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> [treding@nvidia.com: reword commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman1-0/+1
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-08-23soc/tegra: fuse: Add missing semi-colonThierry Reding1-1/+1
Commit 8a46828e623c ("soc/tegra: Register SoC device") added a new initcall, but forgot to terminate the line with a semi-colon. Some recent versions of GCC seem to report this as an error. Fixes: 8a46828e623c ("soc/tegra: Register SoC device") Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-08-23soc/tegra: Restrict SoC device registration to TegraThierry Reding1-0/+8
Commit 8a46828e623c ("soc/tegra: Register SoC device") added an initcall to register the SoC device on Tegra. However, that code is unrestricted and will run on all platforms, causing unwanted warnings. Fix this by first checking that we're running on hardware that supports the fuses block that we use to provide SoC information. Fixes: 8a46828e623c ("soc/tegra: Register SoC device") Reported-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 11:58:14 +0300