BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Collapse)	Author	Files	Lines
2020-11-30	power: reset: ocelot: Add support 2 other MIPS based SoCs	Gregory CLEMENT	1	-3/+27
	This adds reset support for Luton and Jaguar2 in the ocelot-reset driver. They are both MIPS based belonging to the Vcore III family. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-10-09	power: reset: ocelot: Add support for Sparx5	Lars Povlsen	1	-12/+43
	This adds reset support for Sparx5 in the ocelot-reset driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2018-12-06	power: reset: ocelot: switch the SI to boot mode	Alexandre Belloni	1	-0/+12
	Switch the SI to boot mode so on a warm reboot, the SI is able to access the flash. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2018-02-12	power: reset: Add a driver for the Microsemi Ocelot reset	Alexandre Belloni	1	-0/+88
	The Microsemi Ocelot SoC has a register allowing to reset the MIPS core. Unfortunately, the syscon-reboot driver can't be used directly (but almost) as the reset control may be disabled using another register. Cc: linux-pm@vger.kernel.org Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>