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Add PECI adapter that allows to send MCTP PCI VDM packets
via i3c-mctp driver.
Signed-off-by: Oleksandr Shulzhenko <oleksandr.shulzhenko.viktorovych@intel.com>
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peci_client can be created dynamically using sysfs API or during build
time using DTS.
Let's use extended DTS properties to create peci_client corresponding to
specific Domain ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Since PECI Target addressing has been changed to use Domain ID
information, each peci_client instance should correspond with both CPU
ID and Domain ID.
Let's extend peci_client structure, sysfs API and intel-peci-client to
use Domain ID. Make MFD device ID as a combination of peci adapter
number, CPU ID and Domain ID.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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PECI address parameter provided to create peci_client instance is not
validated in the function that handles data passed from userspace or
DTS, it is only done later on in peci_new_device().
Let's move PECI address verification before peci_new_device() is called.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Remove "static" specifier for mctp_peci_vdm_hdr struct declaration to
fix compilation warning:
drivers/peci/busses/peci-mctp.c:45:1: warning: useless storage class specifier in empty declaration
45 | } __packed;
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Fixes: 00037aaa6440 ("peci: mctp: Add peci-mctp adapter")
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Get DomainId from peci subsystem message to send message to
requested EID. Required EID is taken from aspeed-mctp
based on the discovery performed by user-space application.
For each particular agent behind master, information about
its BDF/DomainId is sufficient to get its EID.
Signed-off-by: Krzysztof Richert <krzysztof.richert@intel.com>
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It's possible that a PECI command can be sent in the old format
without a domain ID. This uses the IOCTL size as a message length
and compares it to the size of the new struct with the domain ID.
If the sizes match, then the domain ID is provided; otherwise, it
is set to 0.
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>
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To support the new domain ID, we need to include an extra byte from
userspace. This adds a length to the peci_command function so we can
detect when the domain ID is sent from userspace.
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>
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When processing PECI transaction, observing any HW state different than
"idle" means that PECI controller won't be able to send PECI commands.
When that occurs, attempting to reinitialize the HW by writing registers
is not enough in some cases, and actual reset needs to be involved.
Fixes: 20b020c06aa9 ("peci: aspeed: add a WA to cover timing negotiation issue")
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Currently, there is no way to view PECI over MCTP transmit or receive
data. To simplify peci-mctp debugging, let's add debug level logging for
tx and rx packets.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
Change-Id: Ia746ae72f37c06e9a2647b4568e9aa6c5be76f76
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This commit adds debug printing out to check caller PID for traffic
profiling.
The printing can be enabled by this command:
echo -n 'file drivers/peci/peci-core.c line 218 +p' > /sys/kernel/debug/dynamic_debug/control
echo '8' > /proc/sys/kernel/printk
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Remove modparam to enable peci-mctp probe and enable it by default.
Tested: Verified that peci-mctp driver probes correctly:
peci peci-1: cdev of adapter [peci-mctp] registered as minor 1
Manually verified that applications using PECI work correctly.
Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
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When peci-mctp finds that there is no discovered CPU, it queries
aspeed-mctp to read BDFs for each static EID reserved by CPU socket.
If BDF is non-zero, peci-mctp reads CPUNODEID_CFG register to determine
CPU represented by this endpoint.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Right now, send and receive API functions are called directly from xfer
handler. Let's add a dedicated helper function responsible for
send/receive to allow issuing PECI messages originated in peci-mctp
driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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PECI frames can be encapsulated into MCTP PCIe VDM packets.
Let's add driver that allows to send PECI frames via aspeed-mctp driver.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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Right now, PECI revision is determined using a result of GetDIB() PECI
command. Because GetDIB() may not be supported by all type of physical
media that provides PECI, we need an alternative.
Until we figure how to determine PECI revision there (if we can't do
that, we'll fallback to device tree), let's allow to hardcode PECI
revision as a property of hardware adapter.
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
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This commit adds a WA to cover timing negotiation hang issue on
target CPU cold resets by retriggering the timing negotiation.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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peci_get_xfer_msg() returns NULL on failure, not an ERR_PTR. Also
avoid calling kfree() on an ERR_PTR.
Fixes: 90ddc4e972b5 ("peci: Add support for PECI bus driver core")
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200926212734.23836-2-zev@bewilderbeest.net
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Add support for the Nuvoton NPCM BMC hardware to the Platform
Environment Control Interface (PECI) subsystem.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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This commit adds Aspeed PECI adapter driver for Aspeed
AST24xx/25xx/26xx SoCs.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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This commit adds driver implementation for PECI bus core into linux
driver framework.
PECI (Platform Environment Control Interface) is a one-wire bus interface
that provides a communication channel from Intel processors and chipset
components to external monitoring or control devices. PECI is designed to
support the following sideband functions:
* Processor and DRAM thermal management
- Processor fan speed control is managed by comparing Digital Thermal
Sensor (DTS) thermal readings acquired via PECI against the
processor-specific fan speed control reference point, or TCONTROL. Both
TCONTROL and DTS thermal readings are accessible via the processor PECI
client. These variables are referenced to a common temperature, the TCC
activation point, and are both defined as negative offsets from that
reference.
- PECI based access to the processor package configuration space provides
a means for Baseboard Management Controllers (BMC) or other platform
management devices to actively manage the processor and memory power
and thermal features.
* Platform Manageability
- Platform manageability functions including thermal, power, and error
monitoring. Note that platform 'power' management includes monitoring
and control for both the processor and DRAM subsystem to assist with
data center power limiting.
- PECI allows read access to certain error registers in the processor MSR
space and status monitoring registers in the PCI configuration space
within the processor and downstream devices.
- PECI permits writes to certain registers in the processor PCI
configuration space.
* Processor Interface Tuning and Diagnostics
- Processor interface tuning and diagnostics capabilities
(Intel Interconnect BIST). The processors Intel Interconnect Built In
Self Test (Intel IBIST) allows for infield diagnostic capabilities in
the Intel UPI and memory controller interfaces. PECI provides a port to
execute these diagnostics via its PCI Configuration read and write
capabilities.
* Failure Analysis
- Output the state of the processor after a failure for analysis via
Crashdump.
PECI uses a single wire for self-clocking and data transfer. The bus
requires no additional control lines. The physical layer is a self-clocked
one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on
whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. In this way, it
is highly flexible even though underlying logic is simple.
The interface design was optimized for interfacing between an Intel
processor and chipset components in both single processor and multiple
processor environments. The single wire interface provides low board
routing overhead for the multiple load connections in the congested routing
area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability
to transfer critical device operating conditions and configuration
information.
This implementation provides the basic framework to add PECI extensions to
the Linux bus and device models. A hardware specific 'Adapter' driver can
be attached to the PECI bus to provide sideband functions described above.
It is also possible to access all devices on an adapter from userspace
through the /dev interface. A device specific 'Client' driver also can be
attached to the PECI bus so each processor client's features can be
supported by the 'Client' driver through an adapter connection in the bus.
Signed-off-by: Jason M Biils <jason.m.bills@linux.intel.com>
Signed-off-by: Yunge Zhu <yunge.zhu@linux.intel.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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