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path: root/drivers/net/dsa
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2021-06-30Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2-3/+9
2021-06-29net: dsa: sja1105: fix dynamic access to L2 Address Lookup table for SJA1110Vladimir Oltean1-4/+22
2021-06-25net: dsa: sja1105: fix NULL pointer dereference in sja1105_reload_cbs()Vladimir Oltean1-0/+6
2021-06-24net: dsa: sja1105: document the SJA1110 in the KconfigVladimir Oltean1-2/+6
2021-06-22net: dsa: b53: Create default VLAN entry explicitlyFlorian Fainelli1-8/+19
2021-06-22net: dsa: mv88e6xxx: Fix adding vlan 0Eldar Gasanov1-3/+3
2021-06-18net: dsa: sja1105: completely error out in sja1105_static_config_reload if so...Vladimir Oltean1-7/+12
2021-06-18net: dsa: sja1105: allow the TTEthernet configuration in the static config fo...Vladimir Oltean1-2/+1
2021-06-18net: dsa: sja1105: properly power down the microcontroller clock for SJA1110Vladimir Oltean4-16/+53
2021-06-16net: dsa: xrs700x: forward HSR supervision framesGeorge McCollister1-8/+19
2021-06-15net: dsa: b53: remove redundant null check on devColin Ian King1-2/+1
2021-06-14net: dsa: sja1105: constify the sja1105_regs structuresVladimir Oltean1-3/+3
2021-06-14net: phy: micrel: ksz886x/ksz8081: add cabletest supportOleksij Rempel1-0/+13
2021-06-14net: dsa: microchip: ksz8795: add LINK_MD register supportOleksij Rempel2-2/+25
2021-06-14net: phy/dsa micrel/ksz886x add MDI-X supportOleksij Rempel1-0/+5
2021-06-14net: dsa: microchip: ksz8795: add phylink supportMichael Grzeschik1-0/+55
2021-06-14net: phy: micrel: move phy reg offsets to common headerMichael Grzeschik2-121/+60
2021-06-11net: dsa: sja1105: plug in support for 2500base-xVladimir Oltean3-2/+16
2021-06-11net: dsa: sja1105: SGMII and 2500base-x on the SJA1110 are 'special'Vladimir Oltean1-0/+2
2021-06-11net: dsa: sja1105: register the PCS MDIO bus for SJA1110Vladimir Oltean3-0/+109
2021-06-11net: dsa: sja1105: migrate to xpcs for SGMIIVladimir Oltean6-199/+195
2021-06-11net: dsa: sja1105: implement TX timestamping for SJA1110Vladimir Oltean4-0/+81
2021-06-11net: dsa: sja1105: add the RX timestamping procedure for SJA1110Vladimir Oltean4-3/+40
2021-06-11net: dsa: add support for the SJA1110 native tagging protocolVladimir Oltean5-1/+18
2021-06-11net: dsa: sja1105: make SJA1105_SKB_CB fit a full timestampVladimir Oltean1-1/+1
2021-06-11net: dsa: sja1105: allow RX timestamps to be taken on all ports for SJA1110Vladimir Oltean3-10/+22
2021-06-11net: dsa: sja1105: enable the TTEthernet engine on SJA1110Vladimir Oltean1-0/+2
2021-06-10net: dsa: sja1105: Fix assigned yet unused return code rcColin Ian King1-1/+1
2021-06-10net: dsa: qca8k: check the correct variable in qca8k_set_mac_eee()Dan Carpenter1-3/+1
2021-06-10net: dsa: qca8k: fix an endian bug in qca8k_get_ethtool_stats()Dan Carpenter1-3/+3
2021-06-09net: dsa: b53: Do not force CPU to be always taggedFlorian Fainelli1-3/+14
2021-06-09net: dsa: felix: set TX flow control according to the phylink_mac_link_up res...Vladimir Oltean1-0/+2
2021-06-09net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TXVladimir Oltean5-1/+358
2021-06-09net: dsa: sja1105: make sure the retagging port is enabled for SJA1110Vladimir Oltean3-0/+58
2021-06-09net: dsa: sja1105: add support for the SJA1110 switch familyVladimir Oltean8-12/+1312
2021-06-08net: mscc: ocelot: check return value after calling platform_get_resource()Yang Yingliang1-0/+5
2021-06-07net: dsa: hellcreek: Use is_zero_ether_addr() instead of memcmp()Zou Wei1-2/+1
2021-06-07net: dsa: sja1105: determine PHY/MAC role from PHY interface typeVladimir Oltean1-46/+18
2021-06-07net: dsa: sja1105: apply RGMII delays based on the fixed-link propertyVladimir Oltean2-14/+15
2021-06-05net: dsa: xrs700x: allow HSR/PRP supervision dupes for node_tableGeorge McCollister1-0/+67
2021-06-01net: dsa: sja1105: some table entries are always present when read dynamicallyVladimir Oltean1-7/+8
2021-06-01net: dsa: sja1105: always keep RGMII ports in the MAC roleVladimir Oltean2-7/+8
2021-06-01net: dsa: sja1105: add a translation table for port speedsVladimir Oltean4-35/+84
2021-06-01net: dsa: sja1105: add a PHY interface type compatibility matrixVladimir Oltean3-29/+55
2021-06-01net: dsa: sja1105: cache the phy-mode port propertyVladimir Oltean2-21/+4
2021-06-01net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually MDIO_MMD_VEND2Vladimir Oltean3-17/+16
2021-06-01net: dsa: sja1105: allow SGMII PCS configuration to be per portVladimir Oltean1-31/+44
2021-06-01net: dsa: sja1105: be compatible with "ethernet-ports" OF node nameVladimir Oltean1-0/+2
2021-05-31net: dsa: qca8k: add missing check return value in qca8k_phylink_mac_config()Yang Yingliang1-2/+7
2021-05-31net: dsa: qca8k: check return value of read functions correctlyYang Yingliang1-70/+60
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