BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-03-16	irqchip/sifive-plic: Add support for multiple PLICs	Atish Patra	1	-30/+51
2020-03-16	irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline	Atish Patra	1	-4/+34
2020-01-24	Merge tag 'irqchip-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/...	Thomas Gleixner	1	-4/+26
2020-01-20	irqchip/sifive-plic: Support irq domain hierarchy	Yash Shah	1	-4/+26
2020-01-05	riscv: prefix IRQ_ macro names with an RV_ namespace	Paul Walmsley	1	-1/+1
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-4/+7
2019-10-25	Merge tag 'irqchip-fixes-5.4-2' of git://git.kernel.org/pub/scm/linux/kernel/...	Thomas Gleixner	1	-2/+2
2019-10-25	irqchip/sifive-plic: Skip contexts except supervisor in plic_init()	Alan Mikhak	1	-2/+2
2019-10-14	Merge tag 'irqchip-fixes-5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/...	Thomas Gleixner	1	-14/+15
2019-09-18	irqchip/sifive-plic: Switch to fasteoi flow	Marc Zyngier	1	-14/+15
2019-09-05	irqchip/sifive-plic: set max threshold for ignored handlers	Christoph Hellwig	1	-2/+10
2019-02-21	irqchip/sifive-plic: Implement irq_set_affinity() for SMP host	Anup Patel	1	-6/+39
2019-02-21	irqchip/sifive-plic: Differentiate between PLIC handler and context	Anup Patel	1	-8/+8
2019-02-21	irqchip/sifive-plic: Add warning in plic_init() if handler already present	Anup Patel	1	-0/+5
2019-02-21	irqchip/sifive-plic: Pre-compute context hart base and enable base	Anup Patel	1	-26/+21
2019-02-14	irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.	Atish Patra	1	-0/+5
2018-10-23	RISC-V: Use Linux logical CPU number instead of hartid	Atish Patra	1	-3/+5
2018-10-23	RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid	Palmer Dabbelt	1	-1/+1
2018-08-13	irqchip: add a SiFive PLIC driver	Christoph Hellwig	1	-0/+260