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path: root/drivers/gpu/drm/radeon/nid.h
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2014-01-21drm/radeon: fix surface sync in fence on cayman (v2)Alex Deucher1-0/+1
We need to set the engine bit to select the ME and also set the full cache bit. Should help stability on TN and cayman. V2: fix up surface sync in ib execute as well Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-07-14drm/radeon: add fault decode function for cayman/TN (v2)Alex Deucher1-0/+16
Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. v2: simplify fault decoding Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2013-07-02drm/radeon/dpm: add debugfs support for caymanAlex Deucher1-0/+4
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon: enable additional power gating features on trinityAlex Deucher1-0/+6
TN has some additional powergating features beyond what is supported on ON/LN. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28drm/radeon/kms: add dpm support for cayman (v5)Alex Deucher1-0/+552
This adds dpm support for cayman asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) - power containment - shader power scaling Set radeon.dpm=1 to enable. v2: fold in tdp fix v3: fix indentation v4: fix 64 bit div v5: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27drm/radeon: add support for thermal sensor on tnAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-17drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TNAlex Deucher1-0/+5
PTE/PDE doesn't support a single update (count = 1). We had previously disabled it since it we were hitting that case which let to hangs. The PTE/PDE packet is much more efficient for VM updates where it can be used. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon: add UVD tiling addr config v2Christian König1-0/+3
v2: set UVD tiling config for rv730 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-04-09drm/radeon: UVD bringup v8Christian König1-0/+9
Just everything needed to decode videos using UVD. v6: just all the bugfixes and support for R7xx-SI merged in one patch v7: UVD_CGC_GATE is a write only register, lockup detection fix v8: split out VRAM fallback changes, remove support for RV770, add support for HEMLOCK, add buffer sizes checks Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09drm/radeon/dce6: add missing display reg for tiling setupAlex Deucher1-0/+4
A new tiling config register for the display blocks was added on DCE6. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=62889 https://bugs.freedesktop.org/show_bug.cgi?id=57919 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-02-01drm/radeon: use status regs to determine what to reset (cayman)Alex Deucher1-0/+14
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-01drm/radeon: consolidate redundant macros and constantsIlija Hadzic1-11/+2
After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03drm/radeon: reset dma engine on gpu reset (v2)Jerome Glisse1-1/+1
This try to reset the dma engine when performing gpu reset. Hopefully bringing back the gpu dma engine in sane state. v2: agd5f: fix dma reset on cayman/TN, add support for SI Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-03drm/radeon: print dma status reg on lockup (v2)Jerome Glisse1-1/+0
To help debug dma related lockup. v2: agd5f: update SI as well Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-12-11drm/radeon/kms: Add initial support for async DMA on cayman/TNAlex Deucher1-0/+75
There are 2 async DMA engines on cayman, one at 0xd000 and one at 0xd800. The programming interface is the same as evergreen however there are some changes to the commands for using vmids. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-12-08drm/radeon: stop page faults from hanging the system (v2)Christian König1-0/+11
Redirect invalid memory accesses to the default page instead of locking up the memory controller. Also enable the invalid memory access interrupts and start spamming system log with it. v2 (agd5f): fix up against 2 level PT changes Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-10-23drm/radeon: fix PFP sync in vm_flushChristian König1-0/+1
Otherwise the next IB might start reading commands with the page table still invalid. Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: make page table updates async v2Christian König1-0/+1
Currently doing the update with the CP. v2: Rebased on Jeromes bugfix. Make validity comparison more human readable. Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-07-20drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xxJerome Glisse1-0/+4
Print various CP register that have valuable informations regarding GPU lockup. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-01drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4)Alex Deucher1-0/+11
Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and simplify render backend map. This now properly sets up the backend map on r6xx-9xx which should improve 3D performance. Vadim benchmarked also: Some benchmarks on juniper (5750), fullscreen 1920x1080, first result - kernel 3.4.0+ (fb21affa), second - with these patches: Lightsmark: 91 fps => 123 fps +35% Doom3: 74 fps => 101 fps +36% Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: Update evergreen functions for trinityAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-23drm/radeon/kms: add some missing semaphore initAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-06drm/radeon: GPU virtual memory support v22Jerome Glisse1-0/+2
Virtual address space are per drm client (opener of /dev/drm). Client are in charge of virtual address space, they need to map bo into it by calling DRM_RADEON_GEM_VA ioctl. First 16M of virtual address space is reserved by the kernel. Once using 2 level page table we should be able to have a small vram memory footprint for each pt (there would be one pt for all gart, one for all vram and then one first level for each virtual address space). Plan include using the sub allocator for a common vm page table area and using memcpy to copy vm page table in & out. Or use a gart object and copy things in & out using dma. v2: agd5f fixes: - Add vram base offset for vram pages. The GPU physical address of a vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete cards and the physical bus address of the stolen memory on integrated chips. - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1 v3: agd5f: - integrate with the semaphore/multi-ring stuff v4: - rebase on top ttm dma & multi-ring stuff - userspace is now in charge of the address space - no more specific cs vm ioctl, instead cs ioctl has a new chunk v5: - properly handle mem == NULL case from move_notify callback - fix the vm cleanup path v6: - fix update of page table to only happen on valid mem placement v7: - add tlb flush for each vm context - add flags to define mapping property (readable, writeable, snooped) - make ring id implicit from ib->fence->ring, up to each asic callback to then do ring specific scheduling if vm ib scheduling function v8: - add query for ib limit and kernel reserved virtual space - rename vm->size to max_pfn (maximum number of page) - update gem_va ioctl to also allow unmap operation - bump kernel version to allow userspace to query for vm support v9: - rebuild page table only when bind and incrementaly depending on bo referenced by cs and that have been moved - allow virtual address space to grow - use sa allocator for vram page table - return invalid when querying vm limit on non cayman GPU - dump vm fault register on lockup v10: agd5f: - Move the vm schedule_ib callback to a standalone function, remove the callback and use the existing ib_execute callback for VM IBs. v11: - rebase on top of lastest Linus v12: agd5f: - remove spurious backslash - set IB vm_id to 0 in radeon_ib_get() v13: agd5f: - fix handling of RADEON_CHUNK_ID_FLAGS v14: - fix va destruction - fix suspend resume - forbid bo to have several different va in same vm v15: - rebase v16: - cleanup left over of vm init/fini v17: agd5f: - cs checker v18: agd5f: - reworks the CS ioctl to better support multiple rings and VM. Rather than adding a new chunk id for VM, just re-use the IB chunk id and add a new flags for VM mode. Also define additional dwords for the flags chunk id to define the what ring we want to use (gfx, compute, uvd, etc.) and the priority. v19: - fix cs fini in weird case of no ib - semi working flush fix for ni - rebase on top of sa allocator changes v20: agd5f: - further CS ioctl cleanups from Christian's comments v21: agd5f: - integrate CS checker improvements v22: agd5f: - final cleanups for release, only allow VM CS on cayman Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon/kms: add support for per-ring fence interruptsAlex Deucher1-0/+9
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon/kms: add cayman specific fence_ring_emitAlex Deucher1-0/+24
cayman is wb only and doesn't have a VC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-02drm/radeon/kms: fix typo in cayman reg offsetAlex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-24drm/radeon/kms/cayman: fix typo in register maskAlex Deucher1-1/+1
Noticed by Droste on IRC. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-22drm/radeon/cayman: setup hdp to invalidate and flush when askedDave Airlie1-0/+2
On cayman we need to set the bit to cause HDP flushes to invalidate the HDP cache also. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-03drm/radeon/kms: add cayman asic reset supportAlex Deucher1-0/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-03drm/radeon/kms: add support for CP setup on cayman asicsAlex Deucher1-0/+168
Cayman asics have 3 ring buffers: ring 0 supports both gfx and compute rings 1 and 2 are compute only At the moment we only support ring 0. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-03drm/radeon/kms: add support for cayman gart setupAlex Deucher1-0/+57
This patch sets up the gart in legacy mode. We probably want to switch to full VM mode at some point. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-03drm/radeon/kms: add gpu_init function for caymanAlex Deucher1-0/+269
This may some work to get accel going. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-07drm/radeon/kms: add ucode loader for NIAlex Deucher1-0/+41
The MC ucode is no longer loaded by the vbios tables as on previous asics. It now must be loaded by the driver. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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