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path: root/drivers/gpu/drm/msm/dsi/pll
AgeCommit message (Expand)AuthorFilesLines
2018-02-20drm/msm/dsi: Populate PLL 10nm clock opsArchit Taneja1-8/+654
2018-02-20drm/msm/dsi: Add skeleton 10nm PHY/PLL codeArchit Taneja3-0/+188
2018-02-20drm/msm/dsi: check for failure on retrieving pll in dsi managerLloyd Atkinson1-1/+1
2017-12-29clk: divider: fix incorrect usage of container_ofJerome Brunet1-1/+1
2017-02-06drm/msm/dsi: Add PHY/PLL for 8x96Archit Taneja3-0/+1127
2016-11-02drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocksArchit Taneja2-0/+2
2016-03-03drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()Luis Henriques1-2/+2
2015-12-14drm/msm/dsi: Add DSI PLL for 28nm 8960 PHYArchit Taneja3-0/+546
2015-09-05Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds3-36/+46
2015-08-25drm/msm/dsi: Convert to clk_hw based provider APIsStephen Boyd1-2/+2
2015-08-16drm/msm/dsi: Make each PHY type compilation independentHai Li1-0/+8
2015-08-16drm/msm/dsi: Save/Restore PLL status across PHY resetHai Li3-36/+38
2015-06-11drm/msm/dsi: Add DSI PLL clock driver supportHai Li3-0/+905