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path: root/drivers/gpu/drm/i915/intel_runtime_pm.c
AgeCommit message (Expand)AuthorFilesLines
2016-11-07drm/i915/vlv: Prevent enabling hpd polling in late suspendLyude1-1/+3
2016-08-22drm/i915: pdev cleanupDavid Weinehall1-14/+16
2016-08-22drm/i915: consistent struct device namingDavid Weinehall1-19/+18
2016-08-16drm/i915: Silence GCC warning for cmn_a_wellChris Wilson1-2/+2
2016-08-10drm/i915: Apply the PPS register unlock workaround more consistentlyImre Deak1-0/+4
2016-07-14drm/i915: Enable polling when we don't have hpdLyude1-0/+2
2016-07-14drm/i915/vlv: Reset the ADPA in vlv_display_power_well_init()Lyude1-0/+7
2016-07-05drm/i915: Convert dev_priv->dev backpointers to dev_priv->drmChris Wilson1-13/+13
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-1/+5
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-5/+8
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-4/+10
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-2/+5
2016-06-30drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()Chris Wilson1-2/+5
2016-06-22drm/i915/bxt: Fix PPS lost state after suspend breaking eDP link trainingImre Deak1-1/+2
2016-06-13drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixesImre Deak1-2/+2
2016-06-13drm/i915/bxt: Move DDI PHY enabling/disabling to the power well codeImre Deak1-7/+99
2016-06-13drm/i915: Factor out intel_power_well_get/putImre Deak1-12/+21
2016-06-06drm/i915: Fix a buch of kerneldoc warningsTvrtko Ursulin1-0/+1
2016-05-23drm/i915: Assert the dbuf is enabled when disabling DC5/6Ville Syrjälä1-0/+11
2016-05-23drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk checkVille Syrjälä1-4/+4
2016-05-23drm/i915: Move SKL+ DBUF enable/disable to display core init/uninitVille Syrjälä1-0/+32
2016-05-23drm/i915: Unify SKL cdclk init pathsVille Syrjälä1-4/+1
2016-04-27drm/i915: Update RAWCLK_FREQ register on VLV/CHVVille Syrjälä1-0/+5
2016-04-22drm/i915/bxt: Enable DC5 during runtime resumeImre Deak1-1/+1
2016-04-22drm/i915/bxt: Sanitize DC state tracking during system resumeImre Deak1-3/+22
2016-04-21drm/i915/kbl: Don't WARN for expected secondary MISC IO power well requestImre Deak1-1/+2
2016-04-19drm/i915: Define HSW/BDW display power domains the right way upVille Syrjälä1-19/+26
2016-04-19drm/i915: Define VLV/CHV display power well domains properlyVille Syrjälä1-2/+40
2016-04-19drm/i915: Set .domains=POWER_DOMAIN_MASK for the always-on wellVille Syrjälä1-16/+6
2016-04-19drm/i915/gen9: Fix runtime PM refcounting in case DMC firmware isn't loadedImre Deak1-0/+3
2016-04-18drm/i915/kbl: Reset secondary power well requests left on by DMC/KVMRImre Deak1-1/+1
2016-04-15Revert "drm/i915/bxt: Disable power well support"Imre Deak1-5/+0
2016-04-15drm/i915/bxt: Add HW state verification for DDI PHY and CDCLKImre Deak1-0/+8
2016-04-15drm/i915/bxt: Don't toggle power well 1 on-demandImre Deak1-14/+61
2016-04-15drm/i915/skl: Unexport skl_pw1_misc_io_initImre Deak1-31/+18
2016-04-15drm/i915/gen9: Fix DMC/DC state assertsImre Deak1-21/+11
2016-04-15drm/i915/gen9: Make power well disabling synchronousImre Deak1-4/+5
2016-04-15drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMRImre Deak1-0/+41
2016-04-12drm/i915: Move vlv_init_display_clock_gating() to the display power wellVille Syrjälä1-0/+13
2016-04-07drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Joonas Lahtinen1-6/+6
2016-03-21drm/i915/bxt: add dsi transcodersJani Nikula1-0/+6
2016-03-09drm/i915/bxt: add missing DSI power domain to power well 1Jani Nikula1-0/+1
2016-03-07drm/i915/gen9: Fix DMC firmware initializationImre Deak1-20/+2
2016-03-01drm/i915/gen9: Remove state asserts when disabling DC statesImre Deak1-40/+1
2016-03-01drm/i915/gen9: Disable DC states if power well support is disabledImre Deak1-0/+3
2016-03-01drm/i915/gen9: Sanitize handling of allowed DC statesImre Deak1-21/+57
2016-03-01drm/i915/skl: Fix power domain suspend sequenceImre Deak1-3/+3
2016-02-26drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)Chris Wilson1-14/+12
2016-02-22drm/i915: Make sure pipe interrupts are processed before turning off power we...Ville Syrjälä1-0/+19
2016-02-22drm/i915: synchronize_irq() before turning off disp2d power well on VLV/CHVVille Syrjälä1-0/+3
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