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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-12drm/i915: s/plane_res_b/blocks/ etc.Ville Syrjälä1-101/+97
2021-03-12drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()Ville Syrjälä1-23/+35
2021-03-12drm/i915: Calculate min_ddb_alloc for trans_wmVille Syrjälä1-3/+5
2021-03-12drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_bVille Syrjälä1-1/+1
2021-03-12drm/i915: Tighten SAGV constraint for pre-tglVille Syrjälä1-4/+16
2021-03-12drm/i915: Workaround async flip + VT-d corruption on HSW/BDWVille Syrjälä1-1/+15
2021-03-03drm/i915: Check tgl+ SAGV watermarks properlyVille Syrjälä1-2/+2
2021-03-03drm/i915: Introduce SAGV transtion watermarkVille Syrjälä1-33/+61
2021-03-03drm/i915: Stuff SAGV watermark into a sub-structureVille Syrjälä1-15/+15
2021-03-03drm/i915: Print wm changes if sagv_wm0 changesVille Syrjälä1-1/+2
2021-03-03drm/i915: Zero out SAGV wm when we don't have enough DDB for itVille Syrjälä1-5/+6
2021-03-03drm/i915: Fix TGL+ plane SAGV watermark programmingVille Syrjälä1-23/+37
2021-02-17drm/i915: Remove dead code from skl_pipe_wm_get_hw_state()José Roberto de Souza1-3/+0
2021-02-08drm/i915: migrate skl planes code new file (v5)Dave Airlie1-0/+1
2021-02-02Merge tag 'topic/adl-s-enabling-2021-02-01-1' of git://anongit.freedesktop.or...Jani Nikula1-1/+1
2021-01-29drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_neededJosé Roberto de Souza1-1/+1
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä1-2/+48
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä1-246/+138
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä1-55/+88
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä1-11/+8
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä1-37/+18
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä1-15/+21
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
2021-01-20drm/i915/tgl: Use TGL stepping info for applying WAsAditya Swarup1-1/+1
2021-01-14drm/i915/dg1: Apply WA 1409120013 and 14011059788José Roberto de Souza1-5/+7
2021-01-07Merge tag 'drm-intel-next-2021-01-04' of git://anongit.freedesktop.org/drm/dr...Daniel Vetter1-276/+276
2020-12-03Merge tag 'drm-intel-next-queued-2020-11-27' of git://anongit.freedesktop.org...Dave Airlie1-140/+132
2020-12-01drm/i915/pm: replace I915_READ()/WRITE() with intel_uncore_read()/write()Jani Nikula1-276/+276
2020-11-16drm/i915: Remove skl_adjusted_plane_pixel_rate()Ville Syrjälä1-25/+2
2020-11-16drm/i915: Store plane relative data rate in crtc_stateVille Syrjälä1-37/+46
2020-11-16drm/i915: Precompute can_sagv for each wm levelVille Syrjälä1-13/+8
2020-11-16drm/i915: Nuke intel_atomic_crtc_state_for_each_plane_state() from skl+ wm codeVille Syrjälä1-16/+25
2020-11-16drm/i915: Pass intel_atomic_state aroundVille Syrjälä1-11/+13
2020-11-13drm/i915: Add hw.pipe_mode to allow bigjoiner pipe/transcoder splitMaarten Lankhorst1-38/+38
2020-11-13Merge tag 'drm-intel-gt-next-2020-11-12-1' of git://anongit.freedesktop.org/d...Dave Airlie1-16/+0
2020-11-11drm/i915/tgl: Fix Media power gate sequence.Rodrigo Vivi1-13/+0
2020-10-29drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registersVille Syrjälä1-9/+4
2020-10-16drm/i915: Apply WAC6entrylatency to kbl/cflVille Syrjälä1-0/+8
2020-10-16drm/i915/dg1: Add initial DG1 workaroundsStuart Summers1-13/+26
2020-09-28drm/i915: Make intel_{enable,disable}_sagv() staticVille Syrjälä1-2/+2
2020-08-28drm/i915/tgl: Fix stepping WA matchingJosé Roberto de Souza1-1/+1
2020-08-17drm/i915/kbl: Fix revision ID checksMatt Roper1-2/+2
2020-08-17drm/i915: Move WaDisableDopClockGating:skl to skl_init_clock_gating()Ville Syrjälä1-6/+4
2020-07-09drm/i915: Document FBC related w/as more thoroughlyVille Syrjälä1-11/+44
2020-07-09drm/i915: Limit WaFbcHighMemBwCorruptionAvoidance to skl and bxtVille Syrjälä1-4/+8
2020-07-09drm/i915: Don't do WaFbcTurnOffFbcWatermark for glkVille Syrjälä1-2/+16
2020-07-09drm/i915: Move all FBC w/as to .init_clock_gating()Ville Syrjälä1-0/+23
2020-07-08drm/i915: Use the gt in HAS_ENGINEDaniele Ceraolo Spurio1-1/+1
2020-07-03drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865Ville Syrjälä1-0/+10
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