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path: root/drivers/gpu/drm/i915/intel_hdmi.c
AgeCommit message (Expand)AuthorFilesLines
2016-03-07drm/i915: Fix bogus dig_port_map[] assignment for pre-HSWTakashi Iwai1-2/+0
2016-02-22drm/i915/hdmi: Ensure the HW is powered during HW state readoutImre Deak1-3/+11
2016-01-18Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds1-33/+30
2016-01-06Merge branch 'for-linus' into for-nextTakashi Iwai1-3/+4
2015-12-30drm/i915: increase the tries for HDMI hotplug live status checkingGary Wang1-1/+1
2015-12-24Backmerge drm-fixes merge into Linus's tree into drm-next.Dave Airlie1-3/+4
2015-12-23Merge tag 'drm-intel-next-2015-12-18' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-9/+9
2015-12-22drm/i915: Correct max delay for HDMI hotplug live status checkingGary Wang1-3/+4
2015-12-22drm/i915: mdelay(10) considered harmfulDaniel Vetter1-1/+1
2015-12-17drm/i915: mdelay(10) considered harmfulDaniel Vetter1-1/+1
2015-12-16drm/i915: Fix AVI/HDMI/SPD infoframes on HSW+Ville Syrjälä1-6/+4
2015-12-15Merge tag 'drm-intel-next-2015-12-04-1' of git://anongit.freedesktop.org/drm-...Dave Airlie1-24/+23
2015-12-11Merge tag 'drm-i915-get-eld' of tiwai/sound into drm-intel-next-queuedDaniel Vetter1-0/+2
2015-12-11drm: Pass 'name' to drm_encoder_init()Ville Syrjälä1-1/+1
2015-12-10drm/i915: Add reverse mapping between port and intel_encoderTakashi Iwai1-0/+2
2015-12-10drm/i915: Separate cherryview from valleyviewWayne Boyer1-2/+2
2015-12-02drm/i915: take a power domain reference while checking the HDMI live statusImre Deak1-0/+4
2015-12-02drm/i915: Introduce a gmbus power domainVille Syrjälä1-6/+2
2015-12-01drm/i915: Don't use crtc->config when reading out infoframe stateVille Syrjälä1-24/+23
2015-11-20drm/i915: take a power domain reference while checking the HDMI live statusImre Deak1-0/+4
2015-11-20drm/i915: take a power domain ref only when needed during HDMI detectImre Deak1-3/+4
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-26/+29
2015-11-17drm/i915: Introduce a gmbus power domainVille Syrjälä1-6/+2
2015-11-10drm/i915: Disable FIFO underrun reporting around IBX transcoder B workaroundVille Syrjälä1-0/+11
2015-10-21drm/i915: add helpers for platform specific revision id range checksJani Nikula1-1/+1
2015-10-21drm/i915/bxt: add revision id for A1 stepping and use itJani Nikula1-1/+1
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä1-12/+14
2015-10-08Revert "drm/i915: Add hot_plug hook for hdmi encoder"Daniel Vetter1-43/+11
2015-10-06drm/i915: Add hot_plug hook for hdmi encoderSonika Jindal1-11/+43
2015-10-06drm/i915: Don't bypass LRC on CHVVille Syrjälä1-5/+0
2015-09-30drm/i915: Add HDMI aspect ratio property for SDVOVille Syrjälä1-9/+0
2015-09-30drm/i915: Constify adjusted_modeVille Syrjälä1-11/+11
2015-09-30drm/i915: Move HDMI aspect ratio setup to .compute_config()Ville Syrjälä1-3/+3
2015-09-30drm/i915: Always call the adjusted mode 'adjusted_mode'Ville Syrjälä1-6/+3
2015-09-23drm/i915: Check live status before reading edidSonika Jindal1-7/+21
2015-09-10drm/i915: add attached connector to hdmi containerShashank Sharma1-0/+1
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-0/+21
2015-09-01drm/i915: Clean up CHV lane soft reset programmingVille Syrjälä1-39/+52
2015-08-31drm/i915: Enable HDMI on DDI-EXiong Zhang1-0/+21
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä1-0/+23
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä1-0/+4
2015-08-26drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer dis...Ville Syrjälä1-0/+23
2015-08-26drm/i915: Always program unique transition scale for CHVVille Syrjälä1-14/+16
2015-08-14drm/i915: Clean up DP/HDMI limited color range handlingVille Syrjälä1-14/+12
2015-08-14drm/i915/bxt: WA for swapped HPD pins in A steppingSonika Jindal1-1/+8
2015-08-14drm/i915: Get rid of dpms handling.Maarten Lankhorst1-1/+1
2015-07-13drm/i915: Adjust BXT HDMI port clock limitsVille Syrjälä1-3/+6
2015-07-06Revert "drm/i915: Disable 12bpc hdmi for now"Ville Syrjälä1-2/+1
2015-07-06drm/i915: Account for CHV/BXT DPLL clock limitationsVille Syrjälä1-15/+43
2015-07-06drm/i915: Bump HDMI min port clock to 25 MHzVille Syrjälä1-1/+1
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