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path: root/drivers/gpu/drm/i915/intel_display.c
AgeCommit message (Expand)AuthorFilesLines
2013-04-24drm/i915: Make data/link N value power of twoVille Syrjälä1-8/+18
2013-04-18drm/i915: fix bpc vs. bpp confusion in intel_crtc_compute_configDaniel Vetter1-2/+2
2013-04-18drm/i915: move cpu_transcoder to the pipe configurationDaniel Vetter1-16/+21
2013-04-18drm/i915: don't intel_crt_init on any ULT machinesPaulo Zanoni1-1/+1
2013-04-18drm/i915: Fixup pfit disabling for gen2/3Daniel Vetter1-7/+21
2013-04-18drm/i915: Fixup Oops in the pipe config computationDaniel Vetter1-10/+13
2013-04-18drm/i915: ensure single initialization and cleanup of backlight deviceJani Nikula1-0/+3
2013-04-18drm/i915: don't touch the PF regs if the power well is downPaulo Zanoni1-3/+7
2013-04-18drm/i915: add intel_using_power_wellPaulo Zanoni1-2/+2
2013-04-18drm/i915: don't check inconsistent modeset state when force-restoringDaniel Vetter1-6/+24
2013-04-18drm/i915: update FDI mPHY setup codeDaniel Vetter1-7/+0
2013-04-18drm/i915: tune down Y tiling scanout warningDaniel Vetter1-2/+4
2013-04-18drm/i915: set CB tuning also for the reduce clockDaniel Vetter1-2/+7
2013-04-18drm/i915: fix FP CB tuning limits for lvdsDaniel Vetter1-1/+1
2013-04-18drm/i915: fix lost FP_CB_TUNE setting for pch pllsDaniel Vetter1-3/+3
2013-04-06drm/i915: Support PCH no displayBen Widawsky1-0/+3
2013-04-05drm/i915: Set PIPECONF color range bit on ValleyviewVille Syrjälä1-0/+7
2013-04-05drm/i915: extract i9xx_set_pipeconfDaniel Vetter1-55/+65
2013-04-03drm/i915: create pipe_config->dpll for clock stateDaniel Vetter1-72/+83
2013-04-03drm/i915: hw readout support for ->has_pch_encodersDaniel Vetter1-9/+25
2013-04-03drm/i915: add hw state readout/checking for pipe_configDaniel Vetter1-10/+67
2013-04-03drm/i915: rip out superflous is_dp&is_cpu_edp trackingDaniel Vetter1-30/+7
2013-04-03drm/i915: track dp target_clock in pipe_configDaniel Vetter1-22/+3
2013-04-03drm/i915: move dp_m_n computation to dp_encoder->compute_configDaniel Vetter1-14/+16
2013-04-03drm/i915: clear up the fdi/dp set_m_n confusionDaniel Vetter1-31/+55
2013-04-03Merge tag 'v3.9-rc5' into drm-intel-next-queuedDaniel Vetter1-5/+5
2013-04-02drm/i915: add sprite assertion function for VLVJesse Barnes1-0/+20
2013-04-02drm/i915: sprite support for ValleyView v4Jesse Barnes1-4/+7
2013-04-02drm/i915: Skip modifying PCH DREF if not changing clock sourcesChris Wilson1-22/+61
2013-03-28drm/i915: fixup fb bpp computation in pipe_config_set_bppDaniel Vetter1-10/+21
2013-03-28drm/i915: check fb->pixel_format instead of bits_per_pixelDaniel Vetter1-4/+2
2013-03-28drm/i915: clean up pipe bpp confusionDaniel Vetter1-0/+8
2013-03-28drm/i915: clean up plane bpp confusionDaniel Vetter1-12/+8
2013-03-28drm/i915: convert DP autodither code to new infrastructureDaniel Vetter1-4/+0
2013-03-28drm/i915: precompute pipe bpp before touching the hwDaniel Vetter1-151/+73
2013-03-28drm/i915: introduce pipe_config->dither|pipe_bppDaniel Vetter1-8/+17
2013-03-28drm/i915: add pipe_config->limited_color_rangeDaniel Vetter1-7/+6
2013-03-28drm/i915: add pipe_config->has_pch_encoderDaniel Vetter1-32/+8
2013-03-28drm/i915: add pipe_config->pixel_multiplierDaniel Vetter1-37/+43
2013-03-28drm/i915: add pipe_config->timings_setDaniel Vetter1-1/+11
2013-03-28drm/i915: compute pipe_config earlierDaniel Vetter1-6/+6
2013-03-28drm/i915: introduce struct intel_crtc_configDaniel Vetter1-34/+48
2013-03-27drm/i915: Apply alignment restrictions on scanout surfaces for VT-dChris Wilson1-1/+29
2013-03-27drm/i915: restore cursor and sprite state when forcing a config restore v2Jesse Barnes1-1/+6
2013-03-24Revert "drm/i915: set TRANSCODER_EDP even earlier"Daniel Vetter1-5/+5
2013-03-23drm/i915: there's no DSPPOS register on gen4+Paulo Zanoni1-4/+6
2013-03-23drm/i915: fix DSPADDR Gen checkPaulo Zanoni1-1/+1
2013-03-23drm/i915: Rename intel_ddi_enable_pipe_func() to transcoder_func()Damien Lespiau1-1/+1
2013-03-23drm/i915: Cleanup if the EDP transcoder has a bobug input valueDamien Lespiau1-0/+8
2013-03-23drm/i915: Kill a strange comment about DPMS functionsVille Syrjälä1-1/+0
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