summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2012-12-10drm/i915: set the LPT FDI RX polarity reversal bit when neededPaulo Zanoni1-0/+2
2012-12-08drm/i915: fix hsw_fdi_link_train "retry" codePaulo Zanoni1-16/+27
2012-11-21drm/i915: fix intel_ddi_get_cdclk_freq for ULT machinesPaulo Zanoni1-0/+2
2012-11-21drm/i915: Enable DP audio for HaswellTakashi Iwai1-0/+9
2012-11-12drm/i915: fix Haswell FDI link disable pathPaulo Zanoni1-0/+26
2012-11-12drm/i915: fix Haswell FDI link training codePaulo Zanoni1-49/+70
2012-11-12drm/i915: set the correct number of FDI lanes on HaswellPaulo Zanoni1-2/+3
2012-11-12drm/i915: create the DDI encoderPaulo Zanoni1-37/+106
2012-11-12drm/i915: add intel_ddi_connector_get_hw_statePaulo Zanoni1-0/+40
2012-11-12drm/i915: add port field to intel_digital_portPaulo Zanoni1-13/+10
2012-10-26drm/i915: enable DDI eDPPaulo Zanoni1-1/+1
2012-10-26drm/i915: turn the eDP DDI panel on/offPaulo Zanoni1-2/+16
2012-10-26drm/i915: set/unset the DDI eDP backlightPaulo Zanoni1-2/+13
2012-10-26drm/i915: set the correct eDP aux channel clock divider on DDIPaulo Zanoni1-1/+1
2012-10-26drm/i915: select the correct pipe when using TRANSCODER_EDPPaulo Zanoni1-0/+17
2012-10-26drm/i915: convert PIPE_MSA_MISC to transcoderPaulo Zanoni1-9/+9
2012-10-26drm/i915: convert DDI_FUNC_CTL to transcoderPaulo Zanoni1-37/+64
2012-10-26drm/i915: convert PIPE_CLK_SEL to transcoderPaulo Zanoni1-2/+8
2012-10-18drm/i915: implement Haswell DP link train sequencePaulo Zanoni1-2/+51
2012-10-18drm/i915: add DP support to intel_ddi_disable_portPaulo Zanoni1-1/+10
2012-10-18drm/i915: add DP support to intel_ddi_mode_setPaulo Zanoni1-17/+44
2012-10-18drm/i915: add DP support to intel_enable_ddiPaulo Zanoni1-9/+12
2012-10-18drm/i915: add DP support to intel_ddi_get_hw_statePaulo Zanoni1-4/+4
2012-10-18drm/i915: add DP support to intel_ddi_get_encoder_portPaulo Zanoni1-3/+9
2012-10-18drm/i915: add DP support to intel_ddi_pll_mode_setPaulo Zanoni1-1/+24
2012-10-18drm/i915: add intel_ddi_set_pipe_settingsPaulo Zanoni1-0/+34
2012-10-17drm/i915: add DP support to intel_ddi_enable_pipe_funcPaulo Zanoni1-4/+30
2012-10-12drm/i915: Fix the SCC/SSC typo in the SPLL bits definitionDamien Lespiau1-1/+1
2012-10-11drm/i915: disable DDI_BUF_CTL at the correct timePaulo Zanoni1-10/+23
2012-10-10drm/i915: don't rely on previous values set on DDI_BUF_CTLPaulo Zanoni1-5/+1
2012-10-10drm/i915: completely rewrite the Haswell PLL handling codePaulo Zanoni1-53/+210
2012-10-10drm/i915: enable and disable PIPE_CLK_SEL at the right timePaulo Zanoni1-4/+33
2012-10-10drm/i915: enable and disable DDI_FUNC_CTL at the right timePaulo Zanoni1-19/+64
2012-10-10drm/i915: rewrite the LCPLL codePaulo Zanoni1-6/+31
2012-09-06drm/i915/hdmi: implement get_hw_stateDaniel Vetter1-0/+29
2012-09-06drm/i915/hdmi: convert to encoder->disable/enableDaniel Vetter1-11/+19
2012-08-17drm/i915: write eld info for HDMI audioWang Xingchao1-1/+5
2012-08-10drm/i915: try harder to find WR PLL clock settingsPaulo Zanoni1-22/+17
2012-08-09drm/i915: completely reset the value of DDI_FUNC_CTLPaulo Zanoni1-6/+1
2012-08-09drm/i915: correctly set the DDI_FUNC_CTL bpc fieldPaulo Zanoni1-6/+20
2012-08-09drm/i915: set the DDI sync polarity bitsPaulo Zanoni1-0/+6
2012-08-09drm/i915: fix pipe DDI mode selectPaulo Zanoni1-1/+6
2012-07-25drm/i915: add port parameter to intel_hdmi_initDaniel Vetter1-1/+1
2012-07-05drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov1-0/+9
2012-05-30drm/i915: add set_infoframes to struct intel_hdmiPaulo Zanoni1-2/+1
2012-05-20drm/i915: prepare HDMI link for HaswellEugeni Dodonov1-0/+116
2012-05-20drm/i915: add WR PLL programming tableEugeni Dodonov1-0/+388
2012-05-20drm/i915: detect digital outputs on HaswellEugeni Dodonov1-0/+29
2012-05-20drm/i915: support DDI training in FDI modeEugeni Dodonov1-0/+115
2012-05-20drm/i915: initialize DDI buffer translationsEugeni Dodonov1-0/+107
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-20 09:01:59 +0300