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path: root/drivers/gpu/drm/amd
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2019-06-22timekeeping: Use proper clock specifier names in functionsJason A. Donenfeld1-1/+1
This makes boot uniformly boottime and tai uniformly clocktai, to address the remaining oversights. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20190621203249.3909-2-Jason@zx2c4.com
2019-06-22drm/amd/display: Add DC core changes for DCN2Harry Wentland9-4/+728
Core DC changes for DCN2. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 HW Sequencer and ResourceHarry Wentland13-1/+5246
Add DCN2 resource definition and HW Sequencer changes. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 VMIDHarry Wentland2-0/+153
Add support to program DCN2 VMID (Virtual Memory Support) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 IPPHarry Wentland2-0/+67
Add support to program DCN2 cursor (IPP) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 DWBHarry Wentland9-0/+2427
Add support to program the DCN2 DWB (Display Writeback) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 MMHUBBUBHarry Wentland2-0/+867
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 HUBP and HUBBUBHarry Wentland9-2/+1739
Add support to program the DCN2 HUBP (Display to data fabric interface pipe) and HUBBUB (DCN memory HUB interface) HW Blocks: +--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 DPPHarry Wentland8-0/+2261
Add support to program the DCN2 DPP (Multiple pipe and plane combine) HW Blocks: +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 MPCHarry Wentland5-1/+955
Add support to program the DCN2 MPC (Multiple pipe and plane combine) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 OPPHarry Wentland4-0/+550
Add support to program the DCN2 OPP (Output Plane Processing) HW Blocks: +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 OPTCHarry Wentland5-2/+614
Add support for programming the DCN2 OPTC (Output Timing Controller) HW Blocks: +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 clk mgrHarry Wentland12-83/+999
Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 DIOHarry Wentland9-0/+1397
Add support for the DIO (Display IO) block of DCN2, which entails our stream and link encoders. HW Blocks: +--------+ | DIO | +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 changes to DMLHarry Wentland11-4/+8693
Update DML (Display Mode Lib) to support DCN2 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 IRQ handlingHarry Wentland3-0/+405
Add support to program DCN2 IRQ handling Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 BIOS parsingHarry Wentland2-0/+10
Handle BIOS parsing for DCN2 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add GPIO support for DCN2Harry Wentland9-0/+759
Adding support to program GPIO HW block of DCN2 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: add AUX and I2C for DCN2Harry Wentland3-0/+64
Adding support to program DCN2 AUX and I2C HW. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 and NV ASIC IDHarry Wentland2-0/+9
DCN2.0 (Display Core Next) is the display block in Navi10. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: use fixed-width data type for soc bounding box structXiaojie Yuan1-15/+15
since it's firmware. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.hLeo Li2-56/+84
DC needs to include the soc bounding box when initializing HW resources. Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is required to define amdgpu_device. The solution here is to split the bounding box structs into a different header, then include it in both amdgpu_ucode.h, and relevant DC HW resource files. Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Read soc_bounding_box from gpu_info (v2)Harry Wentland5-1/+91
[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: notify smu with active display counthersen wu1-0/+1
when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: allow dc request uclk changehersen wu1-1/+2
when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: initialize THM & CLK IP registers base addressHawking Zhang1-0/+2
was missed before. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10 (v2)Marek Olšák1-10/+11
Proper size is 0. v2: squash in whitespace fixes (Ernst Sjöstrand) Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10Kevin Wang1-13/+0
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: enable BACO feature as WARJack Xiao1-0/+1
It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabledKevin Wang1-3/+5
the uclk dpm feature is not work well on all navi10 asic, use pp feature mask module parameter to control it. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: add new navi10 DIDstiancyin1-0/+2
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: add ppt interface version logtiancyin1-2/+4
Include the interface version as well. Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/gfx10: update to latest golden settingAlex Deucher1-1/+1
Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/powerplay/vega20: use correct table indexAlex Deucher1-5/+5
Use the SMU_* variant so we look up the correct index. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN: enable indirect DPG SRAM modeLeo Liu1-0/+3
This is default mode for VCN2.x now Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN: implement indirect DPG SRAM modeLeo Liu2-19/+53
SRAM will be programmed by PSP Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN: add buffer for indirect SRAM usageLeo Liu2-0/+22
This will be used later for indirect SRAM mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: disable fw dstate when gfxoff is enabledJack Xiao1-1/+4
SMU FW has bug that it would cause hung when both fw dstate and gfxoff are enabled at the same time. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: update smu11_driver_if_navi10.hJack Xiao1-10/+14
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.23 Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/psp: add new psp interface for vcn updating sramJack Xiao2-0/+16
PSP leverages the existing fw loading function for vcn updating sram. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/psp: convert ucode id to psp ucode idJack Xiao1-0/+6
Convert ucode id to the corresponding psp ucode id. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: add corresponding vcn ram ucode idJack Xiao1-0/+2
Add VCN RAM ucode id in corresponding to psp ucode id. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/psp: add new VCN RAM ucode id to pspJack Xiao1-0/+2
PSP supports to program vcn sram by ucode loading interface. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu: enable VCN2.0 DPG modeLeo Liu1-1/+2
It will be the default for VCN2.x family Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN2.0: add DPG pause modeLeo Liu1-0/+70
Pause the DPG when not doing decode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)Leo Liu1-3/+296
This is for using SRAM directly v2: rebase (Alex) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN2.0: add direct SRAM read and writeLeo Liu1-0/+48
This will be the basic and used for DPG mode Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amdgpu/VCN2.0 remove unused Macro and declarationLeo Liu1-2/+0
Just for cleanup Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: simplified od_settings for each asicKevin Wang4-87/+77
the od_settings is asic related data, so move it to asic file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/powerplay: move od_default_setting callback to asic fileKevin Wang4-50/+43
the set default od_setting is asic related function, so move thic code to vega20_ppt file. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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