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path: root/drivers/gpu/drm/amd/display/dc/dcn30
AgeCommit message (Expand)AuthorFilesLines
2022-04-20drm/amd/display: Enable power gating before init_pipesRoman Li1-2/+3
2022-04-20drm/amd/display: Add pstate verification and recovery for DCN31Nicholas Kazlauskas1-0/+1
2022-02-01drm/amd/display: Fix FP start/end for dcn30_internal_validate_bw.Bas Nieuwenhuizen1-2/+2
2022-01-05drm/amd/display: Changed pipe split policy to allow for multi-display pipe splitAngus Wang1-1/+1
2021-11-18drm/amd/display: fix null pointer deref when plugging in displayAurabindo Pillai1-1/+2
2021-08-26drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to boundi...Nicholas Kazlauskas1-1/+1
2021-08-26drm/amd/display: Remove duplicate dml initAurabindo Pillai1-5/+0
2021-08-26drm/amd/display: Update bounding box states (v2)Jerry (Fangzhi) Zuo1-10/+31
2021-08-26drm/amd/display: Update number of DCN3 clock statesAurabindo Pillai1-0/+1
2021-08-09drm/amd/display: fix incorrect CM/TF programming sequence in dwbRoy Chan1-26/+64
2021-08-09drm/amd/display: fix missing writeback disablement if plane is removedRoy Chan1-1/+11
2021-08-09drm/amd/display: Remove invalid assert for ODM + MPC caseEric Bernstein1-1/+0
2021-08-06drm/amd/display: Assume LTTPR interop for DCN31+Wesley Chalmers1-0/+20
2021-07-28drm/amd/display: Always wait for update lock statusEric Bernstein1-5/+3
2021-07-23drm/amd/display: Line Buffer changesNevenko Stupar2-18/+1
2021-07-23drm/amd/display: Fixed hardware power down bypass during headless bootJake Wang1-14/+11
2021-07-21drm/amd/display: log additional register state for debugJosip Pavic2-1/+14
2021-06-22drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher1-2/+0
2021-06-16drm/amd/display: Add interface to get Calibrated Avg Level from FIFOWesley Chalmers2-0/+14
2021-06-16drm/amd/display: Enforce DPCD Address rangesWesley Chalmers1-0/+1
2021-06-16drm/amd/display: Read LTTPR caps first on bootupWesley Chalmers1-0/+3
2021-06-08drm/amd/display: Add interface for ADD & DROP PIXEL RegistersWesley Chalmers2-1/+18
2021-06-08drm/amd/display: Add Interface to set FIFO ERRDET SW OverrideWesley Chalmers1-0/+1
2021-06-08drm/amd/display: Change default policy for MPO with multidisplayAric Cyr1-1/+1
2021-06-08drm/amd/display: Return last used DRR VTOTAL from DCJayendran Ramani2-2/+5
2021-06-08drm/amd/display: Refactor visual confirmWyatt Wood2-3/+2
2021-06-04drm/amd/display: Add DCN3.1 DCHHUBNicholas Kazlauskas1-0/+5
2021-05-27drm/amd/display: Increase linebuffer pixel depth to 36bpp.Mario Kleiner1-1/+2
2021-05-27drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616.Mario Kleiner1-1/+2
2021-05-27Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"Qingqing Zhuo2-2/+1
2021-05-20drm/amd/display: Fix typo of format termination newlineJoe Perches1-1/+1
2021-05-20drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai1-0/+175
2021-05-20drm/amd/display: Refactor and add visual confirm for HW Flip QueueWyatt Wood2-1/+2
2021-05-20drm/amd/display: Use the correct max downscaling value for DCN3.x familyNikola Cornij1-3/+4
2021-05-20drm/amd/display: Add Overflow check to skip MALLBhawanpreet Lakha1-0/+9
2021-05-11drm/amd/display: Delete several unneeded bool conversionsZhen Lei1-1/+1
2021-04-29drm/amd/display: Add SE_DCN3_REG_LIST for control SDP numMax.Tseng1-0/+2
2021-04-29drm/amd/display: Clear MASTER_UPDATE_LOCK_DB_EN when disable doublebuffer lockRobin Chen1-1/+1
2021-04-29drm/amd/display: Add new DP_SEC registers for programming SDP Line numberMax.Tseng1-0/+2
2021-04-29drm/amd/display: ddc resource data need to be initializedYu-ting Shen1-1/+1
2021-04-09drm/amd/display: Add missing mask for DCN3Qingqing Zhuo1-0/+1
2021-04-09drm/amd/display: Add function and debugfs to dump DCC_EN bitVictor Lu1-1/+2
2021-04-09drm/amd/display: revert max lb lines changeDmytro Laktyushkin1-1/+1
2021-03-24drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
2021-03-24drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong1-2/+2
2021-03-24drm/amd/display: fix dcn3+ bw validation soc param update sequenceDmytro Laktyushkin2-5/+13
2021-03-24drm/amd/display: Separate caps for maximum RGB and YUV plane countsAtufa Khan1-0/+2
2021-03-24drm/amd/display: Correct algorithm for reversed gammaCalvin Hou1-8/+18
2021-03-24drm/amd/display: use max lb for latency hidingDmytro Laktyushkin1-1/+3
2021-03-24drm/amd/display: Remove unnecessary conversion to boolJiapeng Chong1-1/+1
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