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path: root/drivers/gpu/drm/amd/amdgpu/nv.c
AgeCommit message (Expand)AuthorFilesLines
2021-03-09drm/amdgpu:disable VCN for Navi12 SKUAsher.Song1-2/+4
2020-11-13drm/amdgpu: enable DCN for navi10 headless SKUTianci.Yin1-2/+1
2020-10-30drm/amdgpu: rename nv_is_headless_sku()Flora Cui1-3/+3
2020-10-30drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKUFlora Cui1-2/+3
2020-10-27drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)Tianci.Yin1-2/+12
2020-10-01drm/amdgpu: switch to indirect reg access helperHawking Zhang1-43/+8
2020-09-23drm/amdgpu: fix hdp register access errorStanley.Yang1-1/+1
2020-09-16drm/amdgpu: Fix consecutive DPC recovery failures.Andrey Grodzovsky1-2/+2
2020-08-26drm/amdgpu: use MODE1 reset for navy_flounder by defaultJiansong Chen1-0/+1
2020-08-26drm/amdgpu: add pre_asic_init callback for naviAlex Deucher1-0/+5
2020-08-15drm/amdgpu: note what type of reset we are usingAlex Deucher1-2/+4
2020-08-08drm/amdgpu: use mode1 reset by default for sienna_cichlidLikun Gao1-3/+8
2020-07-23drm/amdgpu: expand sienna chichlid reg access supportJohn Clements1-0/+45
2020-07-21drm/amdgpu: enable xgmi support for sienna cichlidJohn Clements1-0/+3
2020-07-15drm/amdgpu: enable ih CG for navy_flounderJiansong Chen1-1/+2
2020-07-15drm/amdgpu: enable hdp CG and LS for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amdgpu: enable mc CG and LS for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amdgpu: enable athub/mmhub PG for navy_flounderJiansong Chen1-1/+3
2020-07-15drm/amd/display: add DC support for navy flounderBhawanpreet Lakha1-0/+4
2020-07-15drm/amdgpu: enable GFX clock gating for navy_flounderJiansong Chen1-1/+4
2020-07-15drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+4
2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
2020-07-15drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang1-1/+8
2020-07-15drm/amdgpu: add module parameter choose reset modeWenhui Sheng1-0/+8
2020-07-15drm/amdgpu: enable mode1 resetWenhui Sheng1-7/+12
2020-07-08drm/amdgpu: fix coding error of mmhub pg enablementLikun Gao1-3/+3
2020-07-02drm/amdgpu: request init data in virt detectionWenhui Sheng1-6/+5
2020-07-01drm/amdgpu: Enable DM block for DCN3Bhawanpreet Lakha1-0/+4
2020-07-01drm/amdgpu: enable DPG mode for VCN3.0Boyuan Zhang1-0/+1
2020-07-01drm/amd/powerplay: enable mmhub pgKenneth Feng1-1/+2
2020-07-01drm/amd/powerplay: enable athub pgKenneth Feng1-1/+2
2020-07-01drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOVshaoyunl1-1/+1
2020-07-01drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.Likun Gao1-0/+1
2020-07-01drm/amd/amdgpu: add athub ls supportKenneth Feng1-1/+2
2020-07-01drm/amd/amdgpu: add IH cg supportKenneth Feng1-1/+2
2020-07-01drm/amd/amdgpu: add HDP mgcg and ls supportKenneth Feng1-1/+3
2020-07-01drm/amd/amdgpu: fix the HDP LS/DS/SD programmingKenneth Feng1-0/+10
2020-07-01drm/amdgpu: open GFX clock gating for sienna_cichlidLikun Gao1-1/+4
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