| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-08-15 | Merge tag 'v4.17.14' into dev-4.17 | Joel Stanley | 2 | -1/+3 |
| 2018-08-03 | clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle | Paul Cercueil | 1 | -1/+2 |
| 2018-08-03 | clk-si544: Properly round requested frequency to nearest match | Mike Looijmans | 1 | -0/+1 |
| 2018-07-30 | Merge tag 'v4.17.11' into dev-4.17 | Joel Stanley | 2 | -0/+39 |
| 2018-07-28 | clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL | Neil Armstrong | 1 | -0/+1 |
| 2018-07-28 | clk: aspeed: Support HPLL strapping on ast2400 | Joel Stanley | 1 | -13/+29 |
| 2018-07-28 | clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical | Joel Stanley | 1 | -2/+2 |
| 2018-07-28 | clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz | Gregory CLEMENT | 1 | -0/+38 |
| 2018-07-05 | Merge tag 'v4.17.4' into dev-4.17 | Joel Stanley | 3 | -16/+13 |
| 2018-07-05 | clk: aspeed: Treat a gate in reset as disabled | Benjamin Herrenschmidt | 1 | -0/+13 |
| 2018-07-03 | clk: at91: PLL recalc_rate() now using cached MUL and DIV values | Marcin Ziemianowicz | 1 | -12/+1 |
| 2018-07-03 | clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL | Martin Blumenstingl | 1 | -0/+7 |
| 2018-07-03 | clk:aspeed: Fix reset bits for PCI/VGA and PECI | Jae Hyun Yoo | 1 | -2/+2 |
| 2018-07-03 | clk: renesas: cpg-mssr: Stop using printk format %pCr | Geert Uytterhoeven | 1 | -4/+5 |
| 2018-06-21 | clk: aspeed: Support HPLL strapping on ast2400 | Joel Stanley | 1 | -13/+29 |
| 2018-06-19 | clk: npcm7xx: fix return value check in npcm7xx_clk_init() | Wei Yongjun | 1 | -1/+1 |
| 2018-06-19 | clk: npcm7xx: add clock controller | Tali Perry | 2 | -0/+657 |
| 2018-06-18 | clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical | Joel Stanley | 1 | -2/+2 |
| 2018-06-18 | clk: aspeed: Add 24MHz fixed clock | Lei YU | 1 | -1/+8 |
| 2018-06-18 | clk: aspeed: Fix reset bits for PCI/VGA and PECI | Jae Hyun Yoo | 1 | -2/+2 |
| 2018-06-18 | clk: aspeed: Support second reset register | Joel Stanley | 1 | -8/+36 |
| 2018-05-16 | clk: stm32: fix: stm32 clock drivers are not compiled by default | Gabriel Fernandez | 1 | -4/+2 |
| 2018-05-16 | clk: imx6ull: use OSC clock during AXI rate change | Stefan Agner | 1 | -1/+1 |
| 2018-05-02 | Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson i... | Stephen Boyd | 2 | -4/+3 |
| 2018-04-25 | clk: meson: meson8b: fix meson8b_cpu_clk parent clock name | Martin Blumenstingl | 1 | -1/+2 |
| 2018-04-25 | clk: meson: meson8b: fix meson8b_fclk_div3_div clock name | Martin Blumenstingl | 1 | -1/+1 |
| 2018-04-25 | clk: meson: drop meson_aoclk_gate_regmap_ops | Yixun Lan | 1 | -2/+0 |
| 2018-04-16 | clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmap | Jerome Brunet | 1 | -1/+10 |
| 2018-04-16 | clk: honor CLK_MUX_ROUND_CLOSEST in generic clk mux | Jerome Brunet | 2 | -4/+13 |
| 2018-04-16 | clk: cs2000: mark resume function as __maybe_unused | Arnd Bergmann | 1 | -1/+1 |
| 2018-04-16 | Merge branch 'clk-stm32mp1' into clk-fixes | Stephen Boyd | 1 | -31/+23 |
| 2018-04-14 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 158 | -3894/+14649 |
| 2018-04-06 | clk: stm32mp1: remove ck_apb_dbg clock | Gabriel Fernandez | 1 | -4/+0 |
| 2018-04-06 | clk: stm32mp1: set stgen_k clock as critical | Gabriel Fernandez | 1 | -2/+1 |
| 2018-04-06 | clk: stm32mp1: add missing tzc2 clock | Gabriel Fernandez | 1 | -3/+6 |
| 2018-04-06 | clk: stm32mp1: fix SAI3 & SAI4 clocks | Gabriel Fernandez | 1 | -2/+2 |
| 2018-04-06 | clk: stm32mp1: remove unused dfsdm_src[] const | Gabriel Fernandez | 1 | -4/+0 |
| 2018-04-06 | clk: stm32mp1: add missing static | Gabriel Fernandez | 1 | -16/+14 |
| 2018-04-06 | Merge branch 'clk-davinci' into clk-next | Stephen Boyd | 2 | -0/+8 |
| 2018-04-06 | clk: davinci: add a reset lookup table for psc0 | Bartosz Golaszewski | 2 | -0/+8 |
| 2018-04-06 | Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and 'clk-i... | Stephen Boyd | 18 | -70/+1299 |
| 2018-04-06 | Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' and... | Stephen Boyd | 29 | -45/+4394 |
| 2018-04-06 | Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and '... | Stephen Boyd | 48 | -759/+2614 |
| 2018-04-06 | Merge branches 'clk-mvebu', 'clk-phase', 'clk-nxp', 'clk-mtk2712' and 'clk-qc... | Stephen Boyd | 6 | -78/+187 |
| 2018-04-06 | Merge branches 'clk-spreadtrum', 'clk-stm32f', 'clk-stm32mp1', 'clk-hi655x' a... | Stephen Boyd | 6 | -8/+2234 |
| 2018-04-06 | Merge branches 'clk-versatile', 'clk-doc', 'clk-must-check', 'clk-qcom' and '... | Stephen Boyd | 4 | -67/+15 |
| 2018-04-06 | Merge branches 'clk-ti', 'clk-amlogic', 'clk-tegra' and 'clk-samsung' into cl... | Stephen Boyd | 49 | -2586/+3769 |
| 2018-04-06 | clk: imx: add clock driver for imx6sll | Bai Ping | 2 | -0/+341 |
| 2018-04-06 | clk: imx: add new gate/gate2 wrapper funtion | Bai Ping | 1 | -0/+14 |
| 2018-04-06 | clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux | Bai Ping | 1 | -2/+2 |
