BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-03-12	clk: tegra: Specify VDE clock rate	Dmitry Osipenko	1	-0/+1
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko	1	-10/+4
2017-11-01	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	1	-1/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	1	-0/+1
2017-10-19	clk: tegra: Make tegra_clk_pll_params __ro_after_init	Bhumika Goyal	1	-8/+8
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	1	-3/+1
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver	1	-0/+1
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	1	-111/+2
2016-04-28	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	Lucas Stach	1	-5/+6
2016-04-28	clk: tegra: Initialize PLL_C to sane rate on Tegra30	Lucas Stach	1	-0/+1
2015-11-20	clk: tegra: pll: Update PLLM handling	Danny Huang	1	-1/+1
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein	1	-110/+117
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein	1	-9/+15
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-1/+1
2015-11-18	clk: tegra: Format tables consistently	Thierry Reding	1	-189/+189
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding	1	-10/+5
2015-11-18	clk: tegra: Fix 26 MHz oscillator frequency	Thierry Reding	1	-1/+1
2015-10-20	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein	1	-1/+7
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd	1	-1/+0
2015-05-13	clk: tegra: Fix hda2codec_2x clock name for Tegra30	Marcel Ziswiler	1	-1/+1
2015-04-10	clk: tegra: Model oscillator as clock	Thierry Reding	1	-1/+2
2015-04-10	clk: tegra: Use consistent indentation	Thierry Reding	1	-10/+10
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding	1	-1/+6
2014-07-17	ARM: tegra: Convert PMC to a driver	Thierry Reding	1	-1/+1
2014-07-17	ARM: tegra: Move includes to include/soc/tegra	Thierry Reding	1	-1/+4
2013-12-12	clk: tegra: remove bogus PCIE_XCLK	Stephen Warren	1	-7/+0
2013-12-12	clk: tegra: implement a reset driver	Stephen Warren	1	-1/+2
2013-11-26	clk: tegra: add FUSE clock device	Alexandre Courbot	1	-1/+1
2013-11-26	clk: tegra: Properly setup PWM clock on Tegra30	Thierry Reding	1	-1/+3
2013-11-26	clk: tegra: Initialize secondary gr3d clock on Tegra30	Thierry Reding	1	-0/+1
2013-11-26	clk: tegra: move tegra30 to common infra	Peter De Schrijver	1	-895/+403
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	1	-2/+2
2013-11-26	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver	1	-27/+35
2013-11-26	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver	1	-28/+11
2013-11-26	clk: tegra: simplify periph clock data	Peter De Schrijver	1	-201/+116
2013-11-26	clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks	Peter De Schrijver	1	-9/+10
2013-08-29	clk: tegra30: Don't wait for PLL_U lock bit	Tuomas Tynkkynen	1	-1/+1
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan	1	-11/+22
2013-08-09	clk: tegra30: Fix incorrect placement of __initdata	Sachin Kamat	1	-1/+1
2013-07-03	Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux	Linus Torvalds	1	-3/+22
2013-06-16	ARM: tegra30: clocks: Fix pciex clock registration	Jay Agarwal	1	-5/+6
2013-06-12	clk: tegra: override bits for Tegra30 PLLM	Peter De Schrijver	1	-0/+18
2013-05-31	clk: tegra: Use common of_clk_init function	Prashant Gaikwad	1	-1/+2
2013-05-31	clk: tegra: fix clk_out parents list	Prashant Gaikwad	1	-2/+2
2013-05-04	Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Linus Torvalds	1	-131/+145
2013-04-09	Merge tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linu...	Arnd Bergmann	1	-2/+1
2013-04-05	clk: tegra: Add flags to tegra_clk_periph()	Peter De Schrijver	1	-1/+1
2013-04-05	clk: tegra: move from a lock bit idx to a lock mask	Peter De Schrijver	1	-11/+11
2013-04-05	clk: tegra: Add PLL post divider table	Peter De Schrijver	1	-0/+7
2013-04-05	clk: tegra: Refactor PLL programming code	Peter De Schrijver	1	-117/+117