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:
BMC/Intel-BMC/linux.git
dev
dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
tegra
/
clk-dfll.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-11-01
clk: tegra: dfll: Fix drvdata overwriting issue
Nicolin Chen
1
-5
/
+5
2017-01-30
PM / OPP: Update OPP users to put reference
Viresh Kumar
1
-11
/
+6
2016-04-28
clk: tegra: dfll: Reference CVB table instead of copying data
Thierry Reding
1
-5
/
+6
2016-03-03
clk: tegra: Remove CLK_IS_ROOT
Stephen Boyd
1
-1
/
+0
2015-10-20
Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...
Michael Turquette
1
-57
/
+57
2015-10-20
clk: tegra: dfll: Monitor code is DEBUG_FS only
Thierry Reding
1
-50
/
+49
2015-09-17
clk: tegra: dfll: Properly protect OPP list
Thierry Reding
1
-1
/
+7
2015-09-15
clk: tegra: Unlock top rates for Tegra124 DFLL clock
Mikko Perttunen
1
-7
/
+8
2015-08-26
clk: tegra: Fix some static checker problems
Stephen Boyd
1
-3
/
+5
2015-07-16
clk: tegra: Add Tegra124 DFLL clocksource platform driver
Tuomas Tynkkynen
1
-3
/
+3
2015-07-16
clk: tegra: Add closed loop support for the DFLL
Tuomas Tynkkynen
1
-3
/
+663
2015-07-16
clk: tegra: Add library for the DFLL clock source (open-loop mode)
Tuomas Tynkkynen
1
-0
/
+1095