summaryrefslogtreecommitdiff
path: root/drivers/clk/samsung/clk-exynos5250.c
AgeCommit message (Expand)AuthorFilesLines
2014-01-08clk: exynos5250: add clock ID for div_pcm0Andrew Bresticker1-1/+1
2014-01-08clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda1-295/+264
2014-01-08clk: exynos5250: register APLL rate tableAndrew Bresticker1-1/+24
2013-12-30clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat1-1/+2
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa1-3/+5
2013-12-30clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa1-3/+3
2013-12-30clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa1-4/+12
2013-12-30clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa1-6/+8
2013-12-30clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa1-8/+17
2013-12-30clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa1-122/+123
2013-12-30clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa1-102/+188
2013-12-30clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan1-1/+2
2013-12-30clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan1-1/+4
2013-12-30clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan1-1/+1
2013-12-30clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker1-2/+2
2013-09-07clk: samsung: exynos5250: Simplify registration of PLL rate tablesTomasz Figa1-10/+2
2013-08-29clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma1-2/+2
2013-08-09clk: exynos5250: Fix incorrect placement of __initdataSachin Kamat1-5/+5
2013-08-09clk: exynos5250: Make exynos5250_plls staticSachin Kamat1-1/+1
2013-08-03clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCVikas Sajjan1-0/+38
2013-08-03clk: samsung: Reorder MUX registration for mout_vpllsrcVikas Sajjan1-1/+6
2013-08-03clk: samsung: Add support to register rate_table for samsung pllsYadwinder Singh Brar1-7/+7
2013-08-03clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll()Yadwinder Singh Brar1-19/+41
2013-07-31clk/exynos5250: add sclk_hdmiphy in the list of special clocksRahul Sharma1-2/+2
2013-07-31clk/exynos5250: add mout_hdmi mux clock for hdmiRahul Sharma1-1/+4
2013-07-30clk: exynos5250: Add G2D gate clockSachin Kamat1-1/+4
2013-07-26clk: exynos5250: Staticize local symbolsSachin Kamat1-7/+7
2013-07-03Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-2/+3
2013-06-18clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2Padmavathi Venna1-2/+3
2013-06-12clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera1-1/+1
2013-06-11clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera1-1/+1
2013-06-11clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera1-3/+3
2013-05-07Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds1-1/+0
2013-04-24clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}Tushar Behera1-8/+8
2013-04-20clk: exynos: prepare for multiplatformArnd Bergmann1-1/+0
2013-04-08clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera1-4/+4
2013-04-04clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala1-1/+9
2013-04-04clk: exynos4: Add support for SoC-specific register save listTomasz Figa1-1/+2
2013-03-25clk: exynos5250: register clocks using common clock frameworkThomas Abraham1-0/+514