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path: root/drivers/clk/meson/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2018-05-18clk: meson: use SPDX license identifiers consistentlyJerome Brunet1-12/+1
2018-03-13clk: meson: add ROUND_CLOSEST to the pll driverJerome Brunet1-4/+13
2018-03-13clk: meson: improve pll driver results with fracJerome Brunet1-47/+90
2018-03-13clk: meson: remove special gp0 lock loopJerome Brunet1-11/+1
2018-03-13clk: meson: migrate plls clocks to clk_regmapJerome Brunet1-150/+93
2018-02-12clk: meson: fix rate calculation of plls with a fractional partJerome Brunet1-1/+0
2018-02-12clk: meson: add od3 to the pll driverJerome Brunet1-3/+16
2018-02-12clk: meson: use the frac parameter width instead of a constantJerome Brunet1-1/+1
2018-02-12clk: meson: remove unnecessary rounding in the pll clockJerome Brunet1-8/+9
2018-02-12clk: meson: check pll rate param table before using itJerome Brunet1-0/+10
2017-04-04clk: meson: Add support for parameters for specific PLLsNeil Armstrong1-2/+51
2016-06-23clk: meson: fractional pll supportMichael Turquette1-2/+30
2016-06-23clk: meson8b: clean up pll clocksMichael Turquette1-61/+11
2015-06-06clk: meson: Add support for Meson clock controllerCarlo Caione1-0/+227