BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2006-03-20	[SPARC64]: Recognize "virtual-console" as input and output console device.	David S. Miller	2	-0/+11
2006-03-20	[SPARC64]: Do not try to synchronize %stick registers on SUN4V.	David S. Miller	1	-1/+5
2006-03-20	[SPARC64]: Do not try to write to %tick or %stick on SUN4V.	David S. Miller	1	-10/+16
2006-03-20	[SPARC64]: Fix mondo queue allocations.	David S. Miller	3	-30/+59
2006-03-20	[SPARC64]: Deal with PTE layout differences in SUN4V.	David S. Miller	11	-429/+645
2006-03-20	[SPARC64]: Register kernel TSB with hypervisor.	David S. Miller	2	-2/+72
2006-03-20	[SPARC64]: Fix some SUN4V TLB miss bugs.	David S. Miller	2	-13/+68
2006-03-20	[SPARC64]: Fix typo in sun4v_patch().	David S. Miller	1	-1/+1
2006-03-20	[SPARC64]: Fix sun4v early bootup.	David S. Miller	1	-15/+20
2006-03-20	[SPARC64]: Fix some Niagara memcpy() bugs.	David S. Miller	2	-4/+8
2006-03-20	[SPARC64]: Handle hypervisor case correctly in copy_tsb().	David S. Miller	1	-2/+9
2006-03-20	[SPARC64]: Fetch bootup time of day from Hypervisor.	David S. Miller	1	-8/+50
2006-03-20	[SPARC64]: Simplify sun4v TLB handling using macros.	David S. Miller	2	-87/+61
2006-03-20	[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.	David S. Miller	6	-162/+113
2006-03-20	[SPARC64]: First cut at SUN4V PCI IOMMU handling.	David S. Miller	4	-31/+550
2006-03-20	[SPARC64]: Fix hypervisor call arg passing.	David S. Miller	5	-53/+53
2006-03-20	[SPARC64]: Implement SUN4V PCI config space access.	David S. Miller	3	-4/+93
2006-03-20	[SPARC64]: More SUN4V PCI controller work.	David S. Miller	4	-1/+364
2006-03-20	[SPARC64]: Beginnings of SUN4V PCI controller support.	David S. Miller	4	-9/+107
2006-03-20	[SPARC64]: Fetch cpu mid properly on sun4v.	David S. Miller	1	-3/+20
2006-03-20	[SPARC64]: SUN4V memory exception trap handlers.	David S. Miller	4	-24/+325
2006-03-20	[SPARC64]: Hypervisor TSB context switching.	David S. Miller	2	-16/+74
2006-03-20	[SPARC64]: Implement sun4v TSB miss handlers.	David S. Miller	3	-9/+64
2006-03-20	[SPARC64]: kernel/cpu.c needs asm/spitfire.h	David S. Miller	1	-0/+1
2006-03-20	[SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.	David S. Miller	1	-1/+4
2006-03-20	[SPARC64]: Detect sun4v early in boot process.	David S. Miller	10	-80/+264
2006-03-20	[SPARC64]: Sun4v cross-call sending support.	David S. Miller	3	-2/+151
2006-03-20	[SPARC64]: Sun4v interrupt handling.	David S. Miller	5	-3/+554
2006-03-20	[SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.	David S. Miller	2	-1/+59
2006-03-20	[SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()	David S. Miller	1	-1/+12
2006-03-20	[SPARC64]: Patch up mmu context register writes for sun4v.	David S. Miller	8	-61/+166
2006-03-20	[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.	David S. Miller	2	-4/+28
2006-03-20	[SPARC64]: Niagara copy/clear page.	David S. Miller	3	-0/+114
2006-03-20	[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch	David S. Miller	7	-28/+28
2006-03-20	[SPARC64]: Initial sun4v TLB miss handling infrastructure.	David S. Miller	6	-16/+332
2006-03-20	[SPARC64]: Add missing memory barriers to instruction patching functions.	David S. Miller	1	-0/+7
2006-03-20	[SPARC64]: Sanitize %pstate writes for sun4v.	David S. Miller	6	-206/+82
2006-03-20	[SPARC64]: Kill all %pstate changes in context switch code.	David S. Miller	1	-1/+4
2006-03-20	[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.	David S. Miller	4	-3/+53
2006-03-20	[SPARC64]: Fill dead cycles on trap entry with real work.	David S. Miller	1	-12/+15
2006-03-20	[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.	David S. Miller	1	-0/+3
2006-03-20	[SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().	David S. Miller	5	-0/+474
2006-03-20	[SPARC64]: Add some hypervisor tlb_type checks.	David S. Miller	2	-8/+30
2006-03-20	[SPARC64]: SUN4V hypervisor TLB flush support code.	David S. Miller	1	-10/+214
2006-03-20	[SPARC64]: Refine register window trap handling.	David S. Miller	6	-439/+214
2006-03-20	[SPARC64]: Add explicit register args to trap state loading macros.	David S. Miller	5	-27/+20
2006-03-20	[SPARC64]: Refine code sequences to get the cpu id.	David S. Miller	6	-87/+73
2006-03-20	[SPARC64]: Turn off TSB growing for now.	David S. Miller	2	-15/+1
2006-03-20	[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.	David S. Miller	2	-18/+1
2006-03-20	[SPARC64]: Access TSB with physical addresses when possible.	David S. Miller	7	-47/+143