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2018-08-22Merge tag 'v4.17.18' into dev-4.17Joel Stanley67-282/+1201
2018-08-18x86/speculation/l1tf: Exempt zeroed PTEs from inversionSean Christopherson1-1/+10
2018-08-17x86/mm: Add TLB purge to free pmd/pte page interfacesToshi Kani1-6/+30
2018-08-17ioremap: Update pgtable free interfaces with addrChintan Pandya2-7/+9
2018-08-17crypto: x86/sha256-mb - fix digest copy in sha256_mb_mgr_get_comp_job_avx2()Eric Biggers1-1/+1
2018-08-17x86/mm: Disable ioremap free page handling on x86-PAEToshi Kani1-0/+19
2018-08-17xen/pv: Call get_cpu_address_sizes to set x86_virt/phys_bitsM. Vefa Bicakci3-1/+5
2018-08-17x86/mm/pti: Clear Global bit more aggressivelyDave Hansen2-10/+30
2018-08-17x86/platform/UV: Mark memblock related init code and data correctlyDou Liyang1-2/+2
2018-08-17x86: i8259: Add missing include fileGuenter Roeck1-0/+1
2018-08-17x86/l1tf: Fix build error seen if CONFIG_KVM_INTEL is disabledGuenter Roeck1-2/+1
2018-08-17arm: dts: aspeed: Romulus can use coprocessor for FSIBenjamin Herrenschmidt1-2/+10
2018-08-17arm: dts: aspeed: Change how power9 chips are represented on OpenPowerBenjamin Herrenschmidt6-216/+170
2018-08-15x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be presentBorislav Petkov4-17/+8
2018-08-15x86/init: fix build with CONFIG_SWAP=nVlastimil Babka1-0/+2
2018-08-15x86/smp: fix non-SMP broken build due to redefinition of apic_id_is_primary_t...Vlastimil Babka1-0/+2
2018-08-15x86/microcode: Allow late microcode loading with SMT disabledJosh Poimboeuf1-4/+12
2018-08-15x86/mm/kmmio: Make the tracer robust against L1TFAndi Kleen1-10/+15
2018-08-15x86/mm/pat: Make set_memory_np() L1TF safeAndi Kleen1-4/+4
2018-08-15x86/speculation/l1tf: Make pmd/pud_mknotpresent() invertAndi Kleen1-10/+12
2018-08-15x86/speculation/l1tf: Invert all not present mappingsAndi Kleen1-1/+1
2018-08-15cpu/hotplug: Fix SMT supported evaluationThomas Gleixner1-1/+1
2018-08-15KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentryPaolo Bonzini3-3/+27
2018-08-15x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentryPaolo Bonzini4-0/+13
2018-08-15x86/speculation: Simplify sysfs report of VMX L1TF vulnerabilityPaolo Bonzini1-3/+9
2018-08-15x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr()Nicolai Stange1-1/+0
2018-08-15x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1dNicolai Stange3-0/+5
2018-08-15x86: Don't include linux/irq.h from asm/hardirq.hNicolai Stange20-2/+19
2018-08-15x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1dNicolai Stange2-4/+36
2018-08-15x86/irq: Demote irq_cpustat_t::__softirq_pending to u16Nicolai Stange1-1/+1
2018-08-15x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush()Nicolai Stange1-4/+6
2018-08-15x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond'Nicolai Stange1-5/+5
2018-08-15x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush()Nicolai Stange1-7/+7
2018-08-15x86/KVM/VMX: Initialize the vmx_l1d_flush_pages' contentNicolai Stange1-3/+14
2018-08-15x86/bugs, kvm: Introduce boot-time control of L1TF mitigationsJiri Kosina3-13/+99
2018-08-15cpu/hotplug: Set CPU_SMT_NOT_SUPPORTED earlyThomas Gleixner1-0/+6
2018-08-15x86/kvm: Allow runtime control of L1D flushThomas Gleixner2-6/+9
2018-08-15x86/kvm: Serialize L1D flush parameter setterThomas Gleixner1-2/+6
2018-08-15x86/kvm: Add static key for flush alwaysThomas Gleixner1-5/+11
2018-08-15x86/kvm: Move l1tf setup functionThomas Gleixner1-47/+78
2018-08-15x86/l1tf: Handle EPT disabled state properThomas Gleixner3-45/+54
2018-08-15x86/kvm: Drop L1TF MSR list approachThomas Gleixner1-36/+7
2018-08-15x86/litf: Introduce vmx status variableThomas Gleixner3-13/+54
2018-08-15x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if requiredKonrad Rzeszutek Wilk1-5/+37
2018-08-15x86/KVM/VMX: Extend add_atomic_switch_msr() to allow VMENTER only MSRsKonrad Rzeszutek Wilk1-8/+14
2018-08-15x86/KVM/VMX: Separate the VMX AUTOLOAD guest/host number accountingKonrad Rzeszutek Wilk1-10/+19
2018-08-15x86/KVM/VMX: Add find_msr() helper functionKonrad Rzeszutek Wilk1-13/+18
2018-08-15x86/KVM/VMX: Split the VMX MSR LOAD structures to have an host/guest numbersKonrad Rzeszutek Wilk1-30/+35
2018-08-15x86/KVM/VMX: Add L1D flush logicPaolo Bonzini4-1/+34
2018-08-15x86/KVM/VMX: Add L1D MSR based flushPaolo Bonzini2-4/+17
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