BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-01-08	RISC-V: Make __NR_riscv_flush_icache visible to userspace	Palmer Dabbelt	2	-28/+1
2017-12-11	RISC-V: Resurrect smp_mb__after_spinlock()	Palmer Dabbelt	1	-0/+19
2017-12-02	RISC-V: Fixes for clean allmodconfig build	Palmer Dabbelt	6	-17/+22
2017-12-02	RISC-V: __io_writes should respect the length argument	Palmer Dabbelt	1	-1/+1
2017-12-02	RISC-V: User-Visible Changes	Palmer Dabbelt	7	-30/+140
2017-12-02	RISC-V: __io_writes should respect the length argument	Palmer Dabbelt	1	-1/+1
2017-11-30	RISC-V: Allow userspace to flush the instruction cache	Andrew Waterman	3	-0/+38
2017-11-30	RISC-V: Flush I$ when making a dirty page executable	Andrew Waterman	5	-30/+102
2017-11-30	RISC-V: Add missing include	Olof Johansson	1	-0/+1
2017-11-30	RISC-V: Use define for get_cycles like other architectures	Olof Johansson	1	-1/+2
2017-11-30	RISC-V: io.h: type fixes for warnings	Olof Johansson	1	-7/+9
2017-11-30	RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros	Olof Johansson	2	-9/+9
2017-11-30	RISC-V: use generic serial.h	Olof Johansson	1	-0/+1
2017-11-29	RISC-V: remove spin_unlock_wait()	Palmer Dabbelt	1	-9/+0
2017-11-29	RISC-V: `sfence.vma` orderes the instruction cache	Palmer Dabbelt	1	-1/+4
2017-11-29	RISC-V: Add READ_ONCE in arch_spin_is_locked()	Palmer Dabbelt	1	-1/+1
2017-11-29	RISC-V: __test_and_op_bit_ord should be strongly ordered	Palmer Dabbelt	1	-1/+1
2017-11-29	RISC-V: Remove smb_mb__{before,after}_spinlock()	Palmer Dabbelt	1	-8/+0
2017-11-29	RISC-V: Remove __smp_bp__{before,after}_atomic	Palmer Dabbelt	1	-15/+0
2017-11-29	RISC-V: Comment on why {,cmp}xchg is ordered how it is	Palmer Dabbelt	1	-2/+7
2017-11-29	RISC-V: Remove unused arguments from ATOMIC_OP	Palmer Dabbelt	1	-47/+47
2017-11-15	Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...	Linus Torvalds	48	-0/+4509
2017-09-27	RISC-V: Build Infrastructure	Palmer Dabbelt	1	-0/+61
2017-09-27	RISC-V: User-facing API	Palmer Dabbelt	5	-0/+303
2017-09-27	RISC-V: Paging and MMU	Palmer Dabbelt	7	-0/+910
2017-09-27	RISC-V: Device, timer, IRQs, and the SBI	Palmer Dabbelt	7	-0/+364
2017-09-27	RISC-V: Task implementation	Palmer Dabbelt	6	-0/+328
2017-09-27	RISC-V: ELF and module implementation	Palmer Dabbelt	3	-0/+150
2017-09-27	RISC-V: Generic library routines and assembly	Palmer Dabbelt	6	-0/+822
2017-09-27	RISC-V: Atomic and Locking Code	Palmer Dabbelt	10	-0/+1423
2017-09-27	RISC-V: Init and Halt Code	Palmer Dabbelt	3	-0/+162