index
:
BMC/Intel-BMC/linux.git
dev
dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
powerpc
/
kernel
/
mce_power.c
Age
Commit message (
Expand
)
Author
Files
Lines
2017-03-10
powerpc/64s: POWER9 machine check handler
Nicholas Piggin
1
-0
/
+231
2017-03-10
powerpc/64s: allow machine check handler to set severity and initiator
Nicholas Piggin
1
-0
/
+6
2016-05-11
powerpc/mm/radix: Fix CONFIG_PPC_MMU_STD_64 typo
Valentin Rothberg
1
-5
/
+5
2016-05-11
powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code
Aneesh Kumar K.V
1
-0
/
+10
2016-05-01
powerpc/mm/radix: Add tlbflush routines
Aneesh Kumar K.V
1
-0
/
+3
2016-02-22
powerpc: Add POWER9 cputable entry
Michael Neuling
1
-9
/
+8
2015-03-16
powerpc/book3s: Fix flush_tlb cpu_spec hook to take a generic argument.
Mahesh Salgaonkar
1
-2
/
+51
2014-12-05
powerpc/book3s: Fix partial invalidation of TLBs in MCE code.
Mahesh Salgaonkar
1
-2
/
+2
2014-03-07
powerpc/book3s: Recover from MC in sapphire on SCOM read via MMIO.
Mahesh Salgaonkar
1
-4
/
+33
2013-12-30
powerpc: Fix endian issues in power7/8 machine check handler
Anton Blanchard
1
-3
/
+3
2013-12-05
powerpc/book3s: Decode and save machine check event.
Mahesh Salgaonkar
1
-8
/
+108
2013-12-05
powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power8.
Mahesh Salgaonkar
1
-0
/
+34
2013-12-05
powerpc/book3s: Flush SLB/TLBs if we get SLB/TLB machine check errors on power7.
Mahesh Salgaonkar
1
-0
/
+150