| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 | Thomas Gleixner | 1 | -5/+1 |
| 2017-11-03 | openrisc: add tick timer multi-core sync logic | Stafford Horne | 1 | -2/+13 |
| 2017-11-03 | openrisc: initial SMP support | Stefan Kristiansson | 1 | -20/+31 |
| 2016-12-25 | clocksource: Use a plain u64 instead of cycle_t | Thomas Gleixner | 1 | -2/+2 |
| 2015-08-10 | openrisc/time: Migrate to new 'set-state' interface | Viresh Kumar | 1 | -24/+0 |
| 2012-02-17 | openrisc: Set shortest clock event to 100 ticks | Jonas Bonn | 1 | -8/+5 |
| 2011-07-22 | OpenRISC: Timekeeping | Jonas Bonn | 1 | -0/+181 |
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index : BMC/Intel-BMC/linux.git | |
| Intel OpenBMC Linux kernel source tree (mirror) | Andrey V.Kosteltsev |
| summaryrefslogtreecommitdiff |