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path: root/arch/mips/include/asm/mipsregs.h
AgeCommit message (Expand)AuthorFilesLines
2018-06-19MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratumTokunori Ikegami1-0/+3
2018-05-15MIPS: Probe for MIPS MT perf counters per TCMatt Redfearn1-0/+5
2018-02-19MIPS: Add crc instruction support flag to elf_hwcapMarcin Nowakowski1-0/+1
2018-01-22MIPS: XPA: Standardise readx/writex accessorsJames Hogan1-10/+10
2018-01-22MIPS: XPA: Allow use of $0 (zero) to MTHC0James Hogan1-2/+2
2018-01-22MIPS: XPA: Use XPA instructions in assemblyJames Hogan1-10/+16
2018-01-22MIPS: VZ: Pass GC0 register names in $n formatJames Hogan1-188/+188
2018-01-22MIPS: VZ: Update helpers to use new asm macrosJames Hogan1-127/+37
2018-01-22MIPS: Add helpers for assembler macro instructionsJames Hogan1-0/+83
2018-01-10MIPS: mipsregs.h: Make read_c0_prid use const accessorJames Hogan1-1/+1
2018-01-10MIPS: mipsregs.h: Add read const Cop0 macrosJames Hogan1-10/+27
2017-11-09MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split'Maciej W. Rozycki1-8/+6
2017-09-21MIPS: Fix input modify in __write_64bit_c0_split()James Hogan1-6/+9
2017-08-30MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton1-0/+13
2017-07-05MIPS: MIPS16e2: Identify ASE presenceMaciej W. Rozycki1-0/+1
2017-03-28KVM: MIPS/VZ: Handle Octeon III guest.PRid registerJames Hogan1-0/+2
2017-03-28MIPS: Add Octeon III register accessors & definitionsJames Hogan1-0/+36
2017-03-28MIPS: Add some missing guest CP0 accessors & defsJames Hogan1-2/+14
2017-03-28MIPS: Separate MAAR V bit into VL and VH for XPAJames Hogan1-1/+7
2017-02-14MIPS: Unify perf counter register definitionsJames Hogan1-0/+33
2016-11-24MIPS: Mask out limit field when calculating wired entry countPaul Burton1-0/+6
2016-09-29MIPS: Stop setting I6400 FTLBPPaul Burton1-2/+0
2016-06-16MIPS: Add define for Config.VI (virtual icache) bitJames Hogan1-0/+1
2016-06-16MIPS: Clean up RDHWR handlingJames Hogan1-1/+19
2016-05-28MIPS: Add 64-bit HTW fieldsJames Hogan1-0/+8
2016-05-28MIPS: Simplify DSP instruction encoding macrosJames Hogan1-90/+17
2016-05-28MIPS: Add missing tlbinvf/XPA microMIPS encodingsJames Hogan1-5/+7
2016-05-28MIPS: Add missing VZ accessor microMIPS encodingsJames Hogan1-9/+18
2016-05-28MIPS: Add inline asm encoding helpersJames Hogan1-0/+27
2016-05-28MIPS: Fix write_gc0_* macros when writing zeroJames Hogan1-2/+2
2016-05-28MIPS: Add definitions of SegCtl registers and use themMatt Redfearn1-0/+3
2016-05-17MIPS: Fix VZ probe gas errors with binutils <2.24James Hogan1-180/+293
2016-05-13MIPS: Add guest CP0 accessorsJames Hogan1-11/+330
2016-05-13MIPS: Add register definitions for VZ ASE registersJames Hogan1-0/+117
2016-05-13MIPS: Avoid magic numbers probing kscratch_maskJames Hogan1-1/+2
2016-05-13MIPS: Add defs & probing of [X]ContextConfigJames Hogan1-0/+6
2016-05-13MIPS: Add defs & probing of BadInstr[P] registersJames Hogan1-0/+3
2016-05-13MIPS: Add defs & probing of extended CP0_EBaseJames Hogan1-0/+3
2016-05-13MIPS: Define & use CP0_EBase bit definitionsJames Hogan1-1/+9
2016-05-13MIPS: Add & use CP0_EntryHi ASID definitionsJames Hogan1-0/+2
2016-05-13MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen1-0/+6
2016-05-13MIPS: Loongson: Invalidate special TLBs when neededHuacai Chen1-0/+9
2016-05-13MIPS: Loongson: Add Loongson-3A R2 basic supportHuacai Chen1-0/+2
2016-05-13MIPS: Add and use watch register field definitionsJames Hogan1-0/+18
2016-05-13MIPS: Add and use CAUSEF_WP definitionJames Hogan1-0/+2
2016-05-13MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton1-0/+1
2016-01-24MIPS: Update trap codesJames Hogan1-2/+10
2016-01-24MIPS: Move Cause.ExcCode trap codes to mipsregs.hJames Hogan1-0/+24
2016-01-24MIPS: Move definition of DC bit to mipsregs.hJames Hogan1-0/+2
2015-11-11MIPS: Tidy EntryLo bit definitions, add PFNPaul Burton1-9/+3