BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 151	Thomas Gleixner	1	-10/+1
2018-09-05	ARM: zynq: Convert to using %pOFn instead of device_node.name	Rob Herring	1	-1/+1
2016-02-09	ARM: zynq: address L2 cache data corruption	Josh Cartwright	1	-0/+4
2015-05-18	ARM: zynq: Drop use of slcr_unlock in zynq_slcr_system_restart	Josh Cartwright	1	-7/+0
2015-05-18	ARM: zynq: Use restart_handler mechanism for slcr reset	Josh Cartwright	1	-2/+19
2015-01-29	ARM: zynq: Simplify SLCR initialization	Michal Simek	1	-28/+7
2014-09-16	ARM: zynq: Synchronise zynq_cpu_die/kill	Soren Brinkmann	1	-1/+42
2014-05-20	ARM: zynq: Add support for SOC_BUS	Michal Simek	1	-0/+19
2014-02-10	ARM: zynq: Introduce zynq_slcr_unlock()	Michal Simek	1	-2/+14
2014-02-10	ARM: zynq: Add and use zynq_slcr_read/write() helper functions	Michal Simek	1	-8/+48
2014-02-10	ARM: zynq: Make zynq_slcr_base static	Steffen Trumtrar	1	-1/+1
2014-02-10	ARM: zynq: Hang iomapped slcr address on device_node	Steffen Trumtrar	1	-0/+2
2014-02-10	ARM: zynq: Split slcr in two parts	Michal Simek	1	-2/+24
2014-02-05	ARM: zynq: Move clock_init from slcr to common	Steffen Trumtrar	1	-2/+0
2013-07-26	arm: zynq: slcr: Use read-modify-write for register writes	Soren Brinkmann	1	-8/+8
2013-07-26	arm: zynq: slcr: Clean up #defines	Soren Brinkmann	1	-13/+12
2013-07-26	arm: zynq: slcr: Remove redundant header #includes	Soren Brinkmann	1	-10/+0
2013-05-27	arm: zynq: Migrate platform to clock controller	Soren Brinkmann	1	-1/+1
2013-04-04	arm: zynq: Add smp support	Michal Simek	1	-0/+29
2013-04-04	arm: zynq: Add support for system reset	Michal Simek	1	-0/+27
2013-04-04	arm: zynq: Move slcr initialization to separate file	Michal Simek	1	-0/+69