diff options
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 275 |
1 files changed, 1 insertions, 274 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index 95932cc88460..152e70db4a81 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -29,280 +29,7 @@ #include "amd_shared.h" #include "cgs_common.h" #include "dm_pp_interface.h" - -extern const struct amd_ip_funcs pp_ip_funcs; -extern const struct amd_pm_funcs pp_dpm_funcs; - -enum amd_pp_sensors { - AMDGPU_PP_SENSOR_GFX_SCLK = 0, - AMDGPU_PP_SENSOR_VDDNB, - AMDGPU_PP_SENSOR_VDDGFX, - AMDGPU_PP_SENSOR_UVD_VCLK, - AMDGPU_PP_SENSOR_UVD_DCLK, - AMDGPU_PP_SENSOR_VCE_ECCLK, - AMDGPU_PP_SENSOR_GPU_LOAD, - AMDGPU_PP_SENSOR_GFX_MCLK, - AMDGPU_PP_SENSOR_GPU_TEMP, - AMDGPU_PP_SENSOR_VCE_POWER, - AMDGPU_PP_SENSOR_UVD_POWER, - AMDGPU_PP_SENSOR_GPU_POWER, -}; - -enum amd_pp_task { - AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, - AMD_PP_TASK_ENABLE_USER_STATE, - AMD_PP_TASK_READJUST_POWER_STATE, - AMD_PP_TASK_COMPLETE_INIT, - AMD_PP_TASK_MAX -}; - -struct amd_pp_init { - struct cgs_device *device; - uint32_t chip_family; - uint32_t chip_id; - bool pm_en; - uint32_t feature_mask; -}; - -enum amd_pp_display_config_type{ - AMD_PP_DisplayConfigType_None = 0, - AMD_PP_DisplayConfigType_DP54 , - AMD_PP_DisplayConfigType_DP432 , - AMD_PP_DisplayConfigType_DP324 , - AMD_PP_DisplayConfigType_DP27, - AMD_PP_DisplayConfigType_DP243, - AMD_PP_DisplayConfigType_DP216, - AMD_PP_DisplayConfigType_DP162, - AMD_PP_DisplayConfigType_HDMI6G , - AMD_PP_DisplayConfigType_HDMI297 , - AMD_PP_DisplayConfigType_HDMI162, - AMD_PP_DisplayConfigType_LVDS, - AMD_PP_DisplayConfigType_DVI, - AMD_PP_DisplayConfigType_WIRELESS, - AMD_PP_DisplayConfigType_VGA -}; - -struct single_display_configuration -{ - uint32_t controller_index; - uint32_t controller_id; - uint32_t signal_type; - uint32_t display_state; - /* phy id for the primary internal transmitter */ - uint8_t primary_transmitter_phyi_d; - /* bitmap with the active lanes */ - uint8_t primary_transmitter_active_lanemap; - /* phy id for the secondary internal transmitter (for dual-link dvi) */ - uint8_t secondary_transmitter_phy_id; - /* bitmap with the active lanes */ - uint8_t secondary_transmitter_active_lanemap; - /* misc phy settings for SMU. */ - uint32_t config_flags; - uint32_t display_type; - uint32_t view_resolution_cx; - uint32_t view_resolution_cy; - enum amd_pp_display_config_type displayconfigtype; - uint32_t vertical_refresh; /* for active display */ -}; - -#define MAX_NUM_DISPLAY 32 - -struct amd_pp_display_configuration { - bool nb_pstate_switch_disable;/* controls NB PState switch */ - bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ - bool cpu_pstate_disable; - uint32_t cpu_pstate_separation_time; - - uint32_t num_display; /* total number of display*/ - uint32_t num_path_including_non_display; - uint32_t crossfire_display_index; - uint32_t min_mem_set_clock; - uint32_t min_core_set_clock; - /* unit 10KHz x bit*/ - uint32_t min_bus_bandwidth; - /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ - uint32_t min_core_set_clock_in_sr; - - struct single_display_configuration displays[MAX_NUM_DISPLAY]; - - uint32_t vrefresh; /* for active display*/ - - uint32_t min_vblank_time; /* for active display*/ - bool multi_monitor_in_sync; - /* Controller Index of primary display - used in MCLK SMC switching hang - * SW Workaround*/ - uint32_t crtc_index; - /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ - uint32_t line_time_in_us; - bool invalid_vblank_time; - - uint32_t display_clk; - /* - * for given display configuration if multimonitormnsync == false then - * Memory clock DPMS with this latency or below is allowed, DPMS with - * higher latency not allowed. - */ - uint32_t dce_tolerable_mclk_in_active_latency; - uint32_t min_dcef_set_clk; - uint32_t min_dcef_deep_sleep_set_clk; -}; - -struct amd_pp_simple_clock_info { - uint32_t engine_max_clock; - uint32_t memory_max_clock; - uint32_t level; -}; - -enum PP_DAL_POWERLEVEL { - PP_DAL_POWERLEVEL_INVALID = 0, - PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_PERFORMANCE, - - PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, - PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, - PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, - PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, - PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, - PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, - PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, - PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, -}; - -struct amd_pp_clock_info { - uint32_t min_engine_clock; - uint32_t max_engine_clock; - uint32_t min_memory_clock; - uint32_t max_memory_clock; - uint32_t min_bus_bandwidth; - uint32_t max_bus_bandwidth; - uint32_t max_engine_clock_in_sr; - uint32_t min_engine_clock_in_sr; - enum PP_DAL_POWERLEVEL max_clocks_state; -}; - -enum amd_pp_clock_type { - amd_pp_disp_clock = 1, - amd_pp_sys_clock, - amd_pp_mem_clock, - amd_pp_dcef_clock, - amd_pp_soc_clock, - amd_pp_pixel_clock, - amd_pp_phy_clock, - amd_pp_dcf_clock, - amd_pp_dpp_clock, - amd_pp_f_clock = amd_pp_dcef_clock, -}; - -#define MAX_NUM_CLOCKS 16 - -struct amd_pp_clocks { - uint32_t count; - uint32_t clock[MAX_NUM_CLOCKS]; - uint32_t latency[MAX_NUM_CLOCKS]; -}; - - -enum { - PP_GROUP_UNKNOWN = 0, - PP_GROUP_GFX = 1, - PP_GROUP_SYS, - PP_GROUP_MAX -}; - -struct pp_states_info { - uint32_t nums; - uint32_t states[16]; -}; - -struct pp_gpu_power { - uint32_t vddc_power; - uint32_t vddci_power; - uint32_t max_gpu_power; - uint32_t average_gpu_power; -}; - -struct pp_display_clock_request { - enum amd_pp_clock_type clock_type; - uint32_t clock_freq_in_khz; -}; - -#define PP_GROUP_MASK 0xF0000000 -#define PP_GROUP_SHIFT 28 - -#define PP_BLOCK_MASK 0x0FFFFF00 -#define PP_BLOCK_SHIFT 8 - -#define PP_BLOCK_GFX_CG 0x01 -#define PP_BLOCK_GFX_MG 0x02 -#define PP_BLOCK_GFX_3D 0x04 -#define PP_BLOCK_GFX_RLC 0x08 -#define PP_BLOCK_GFX_CP 0x10 -#define PP_BLOCK_SYS_BIF 0x01 -#define PP_BLOCK_SYS_MC 0x02 -#define PP_BLOCK_SYS_ROM 0x04 -#define PP_BLOCK_SYS_DRM 0x08 -#define PP_BLOCK_SYS_HDP 0x10 -#define PP_BLOCK_SYS_SDMA 0x20 - -#define PP_STATE_MASK 0x0000000F -#define PP_STATE_SHIFT 0 -#define PP_STATE_SUPPORT_MASK 0x000000F0 -#define PP_STATE_SUPPORT_SHIFT 0 - -#define PP_STATE_CG 0x01 -#define PP_STATE_LS 0x02 -#define PP_STATE_DS 0x04 -#define PP_STATE_SD 0x08 -#define PP_STATE_SUPPORT_CG 0x10 -#define PP_STATE_SUPPORT_LS 0x20 -#define PP_STATE_SUPPORT_DS 0x40 -#define PP_STATE_SUPPORT_SD 0x80 - -#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\ - block << PP_BLOCK_SHIFT |\ - support << PP_STATE_SUPPORT_SHIFT |\ - state << PP_STATE_SHIFT) - -struct amd_powerplay { - struct cgs_device *cgs_device; - void *pp_handle; - const struct amd_ip_funcs *ip_funcs; - const struct amd_pm_funcs *pp_funcs; -}; - -int amd_powerplay_reset(void *handle); - -int amd_powerplay_display_configuration_change(void *handle, - const struct amd_pp_display_configuration *input); - -int amd_powerplay_get_display_power_level(void *handle, - struct amd_pp_simple_clock_info *output); - -int amd_powerplay_get_current_clocks(void *handle, - struct amd_pp_clock_info *output); - -int amd_powerplay_get_clock_by_type(void *handle, - enum amd_pp_clock_type type, - struct amd_pp_clocks *clocks); - -int amd_powerplay_get_clock_by_type_with_latency(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_latency *clocks); - -int amd_powerplay_get_clock_by_type_with_voltage(void *handle, - enum amd_pp_clock_type type, - struct pp_clock_levels_with_voltage *clocks); - -int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle, - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); - -int amd_powerplay_display_clock_voltage_request(void *handle, - struct pp_display_clock_request *clock); - -int amd_powerplay_get_display_mode_validation_clocks(void *handle, - struct amd_pp_simple_clock_info *output); +#include "kgd_pp_interface.h" #endif /* _AMD_POWERPLAY_H_ */ |