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path: root/drivers/clk/mediatek/clk-mt2701.c
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Diffstat (limited to 'drivers/clk/mediatek/clk-mt2701.c')
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 6d2f82fa4339..6f26e6a37a6b 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -787,8 +787,12 @@ static int mtk_infrasys_init(struct platform_device *pdev)
infra_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
+ if (r)
+ return r;
- return r;
+ mtk_register_reset_controller(node, 2, 0x30);
+
+ return 0;
}
static const struct mtk_gate_regs peri0_cg_regs = {
@@ -906,8 +910,12 @@ static int mtk_pericfg_init(struct platform_device *pdev)
&mt2701_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ return r;
- return r;
+ mtk_register_reset_controller(node, 2, 0x0);
+
+ return 0;
}
#define MT8590_PLL_FMAX (2000 * MHZ)