diff options
Diffstat (limited to 'arch/arm/mach-s3c24xx')
| -rw-r--r-- | arch/arm/mach-s3c24xx/Kconfig | 22 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/clock-s3c2440.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/common.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/cpufreq.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/dma-s3c2410.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/dma-s3c2412.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/dma-s3c2440.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/dma-s3c2443.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/include/mach/dma.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/include/mach/irqs.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/mach-rx1950.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-s3c24xx/regs-dsc.h | 203 |
12 files changed, 23 insertions, 234 deletions
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index 0a8663c5f2ba..f2f7088bfd22 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -37,7 +37,6 @@ config CPU_S3C2410 config CPU_S3C2412 bool "SAMSUNG S3C2412" - depends on ARCH_S3C24XX select CPU_ARM926T select CPU_LLSERIAL_S3C2440 select S3C2412_DMA if S3C24XX_DMA @@ -48,7 +47,6 @@ config CPU_S3C2412 config CPU_S3C2416 bool "SAMSUNG S3C2416/S3C2450" - depends on ARCH_S3C24XX select CPU_ARM926T select CPU_LLSERIAL_S3C2440 select S3C2416_PM if PM @@ -86,7 +84,6 @@ config CPU_S3C244X config CPU_S3C2443 bool "SAMSUNG S3C2443" - depends on ARCH_S3C24XX select CPU_ARM920T select CPU_LLSERIAL_S3C2440 select S3C2443_COMMON @@ -139,7 +136,6 @@ config S3C24XX_SETUP_TS config S3C24XX_DMA bool "S3C2410 DMA support" - depends on ARCH_S3C24XX select S3C_DMA help S3C2410 DMA support. This is needed for drivers like sound which @@ -148,7 +144,7 @@ config S3C24XX_DMA config S3C2410_DMA_DEBUG bool "S3C2410 DMA support debug" - depends on ARCH_S3C24XX && S3C2410_DMA + depends on S3C2410_DMA help Enable debugging output for the DMA code. This option sends info to the kernel log, at priority KERN_DEBUG. @@ -239,7 +235,7 @@ if CPU_S3C2410 config S3C2410_CPUFREQ bool - depends on CPU_FREQ_S3C24XX && CPU_S3C2410 + depends on CPU_FREQ_S3C24XX select S3C2410_CPUFREQ_UTILS help CPU Frequency scaling support for S3C2410 @@ -326,7 +322,6 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" - select MACH_N35 select S3C_DEV_NAND select S3C_DEV_USB_HOST help @@ -386,14 +381,13 @@ if CPU_S3C2412 config CPU_S3C2412_ONLY bool - depends on ARCH_S3C24XX && !CPU_S3C2410 && \ - !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \ - !CPU_S3C2443 && CPU_S3C2412 + depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ + !CPU_S3C2442 && !CPU_S3C2443 default y config S3C2412_CPUFREQ bool - depends on CPU_FREQ_S3C24XX && CPU_S3C2412 + depends on CPU_FREQ_S3C24XX default y select S3C2412_IOTIMING help @@ -649,7 +643,6 @@ comment "S3C2442 Boards" config MACH_NEO1973_GTA02 bool "Openmoko GTA02 / Freerunner phone" select I2C - select MACH_NEO1973 select MFD_PCF50633 select PCF50633_GPIO select POWER_SUPPLY @@ -670,10 +663,7 @@ config MACH_RX1950 help Say Y here if you're using HP iPAQ rx1950 -config SMDK2440_CPU2442 - bool "SMDM2440 with S3C2442 CPU module" - -endif # CPU_S3C2440 +endif # CPU_S3C2442 if CPU_S3C2443 || CPU_S3C2416 diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index 04b87ec92537..1069b5680826 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c @@ -123,6 +123,11 @@ static struct clk s3c2440_clk_ac97 = { .ctrlbit = S3C2440_CLKCON_AC97, }; +#define S3C24XX_VA_UART0 (S3C_VA_UART) +#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 ) +#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 ) +#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 ) + static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) { unsigned long ucon0, ucon1, ucon2, divisor; diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index d97533d21ac4..c157103ed8eb 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -236,6 +236,11 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) /* Serial port registrations */ +#define S3C2410_PA_UART0 (S3C24XX_PA_UART) +#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 ) +#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 ) +#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 ) + static struct resource s3c2410_uart0_resource[] = { [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K), [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \ diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c index 5f181e733eee..3c0e78ede0da 100644 --- a/arch/arm/mach-s3c24xx/cpufreq.c +++ b/arch/arm/mach-s3c24xx/cpufreq.c @@ -204,7 +204,6 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, freqs.old = cpu_cur.freq; freqs.new = cpu_new.freq; - freqs.freqs.cpu = 0; freqs.freqs.old = cpu_cur.freq.armclk / 1000; freqs.freqs.new = cpu_new.freq.armclk / 1000; @@ -218,9 +217,7 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); /* start the frequency change */ - - if (policy) - cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE); + cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE); /* If hclk is staying the same, then we do not need to * re-write the IO or the refresh timings whilst we are changing @@ -264,8 +261,7 @@ static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, local_irq_restore(flags); /* notify everyone we've done this */ - if (policy) - cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE); + cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE); s3c_freq_dbg("%s: finished\n", __func__); return 0; diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c index a6c94b820954..30aa53ff07a6 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2410.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c @@ -25,10 +25,8 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <plat/regs-ac97.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> -#include <plat/regs-iis.h> #include <plat/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = { diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c index c0e8c3f5057e..ab1700ec8e64 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2412.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c @@ -25,10 +25,8 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <plat/regs-ac97.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> -#include <plat/regs-iis.h> #include <plat/regs-spi.h> #define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID } diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c index 1c08eccd9425..cd25de28804c 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2440.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c @@ -25,10 +25,8 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <plat/regs-ac97.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> -#include <plat/regs-iis.h> #include <plat/regs-spi.h> static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = { diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c index 000e4c69fce9..5fe3539dc2b5 100644 --- a/arch/arm/mach-s3c24xx/dma-s3c2443.c +++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c @@ -25,10 +25,8 @@ #include <plat/regs-serial.h> #include <mach/regs-gpio.h> -#include <plat/regs-ac97.h> #include <plat/regs-dma.h> #include <mach/regs-lcd.h> -#include <plat/regs-iis.h> #include <plat/regs-spi.h> #define MAP(x) { \ diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h index 6b72d5a4b377..b55da1d8cd8f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/arch/arm/mach-s3c24xx/include/mach/dma.h @@ -24,7 +24,6 @@ */ enum dma_ch { - DMACH_DT_PROP = -1, /* not yet supported, do not use */ DMACH_XD0 = 0, DMACH_XD1, DMACH_SDI, diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c24xx/include/mach/irqs.h index 43cada8019b4..b6dd4cb5a2ec 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c24xx/include/mach/irqs.h @@ -192,10 +192,8 @@ #if defined(CONFIG_CPU_S3C2416) #define NR_IRQS (IRQ_S3C2416_I2S1 + 1) -#elif defined(CONFIG_CPU_S3C2443) -#define NR_IRQS (IRQ_S3C2443_AC97+1) #else -#define NR_IRQS (IRQ_S3C2440_AC97+1) +#define NR_IRQS (IRQ_S3C2443_AC97 + 1) #endif /* compatibility define. */ diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index e4d67a33ebee..44ca018e1f96 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c @@ -56,7 +56,6 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/pm.h> -#include <plat/regs-iic.h> #include <plat/regs-serial.h> #include <plat/samsung-time.h> diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h index 98fd4a05587c..61b3d1387d76 100644 --- a/arch/arm/mach-s3c24xx/regs-dsc.h +++ b/arch/arm/mach-s3c24xx/regs-dsc.h @@ -1,5 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h - * +/* * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> * http://www.simtec.co.uk/products/SWLINUX/ * @@ -12,209 +11,15 @@ #ifndef __ASM_ARCH_REGS_DSC_H -#define __ASM_ARCH_REGS_DSC_H "2440-dsc" +#define __ASM_ARCH_REGS_DSC_H __FILE__ -#if defined(CONFIG_CPU_S3C2412) +/* S3C2412 */ #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) #define S3C2412_DSC1 S3C2410_GPIOREG(0xe0) -#endif - -#if defined(CONFIG_CPU_S3C2416) -#define S3C2416_DSC0 S3C2410_GPIOREG(0xc0) -#define S3C2416_DSC1 S3C2410_GPIOREG(0xc4) -#define S3C2416_DSC2 S3C2410_GPIOREG(0xc8) -#define S3C2416_DSC3 S3C2410_GPIOREG(0x110) - -#define S3C2416_SELECT_DSC0 (0 << 30) -#define S3C2416_SELECT_DSC1 (1 << 30) -#define S3C2416_SELECT_DSC2 (2 << 30) -#define S3C2416_SELECT_DSC3 (3 << 30) - -#define S3C2416_DSC_GETSHIFT(x) (x & 30) - -#define S3C2416_DSC0_CF (S3C2416_SELECT_DSC0 | 28) -#define S3C2416_DSC0_CF_5mA (0 << 28) -#define S3C2416_DSC0_CF_10mA (1 << 28) -#define S3C2416_DSC0_CF_15mA (2 << 28) -#define S3C2416_DSC0_CF_21mA (3 << 28) -#define S3C2416_DSC0_CF_MASK (3 << 28) - -#define S3C2416_DSC0_nRBE (S3C2416_SELECT_DSC0 | 26) -#define S3C2416_DSC0_nRBE_5mA (0 << 26) -#define S3C2416_DSC0_nRBE_10mA (1 << 26) -#define S3C2416_DSC0_nRBE_15mA (2 << 26) -#define S3C2416_DSC0_nRBE_21mA (3 << 26) -#define S3C2416_DSC0_nRBE_MASK (3 << 26) - -#define S3C2416_DSC0_nROE (S3C2416_SELECT_DSC0 | 24) -#define S3C2416_DSC0_nROE_5mA (0 << 24) -#define S3C2416_DSC0_nROE_10mA (1 << 24) -#define S3C2416_DSC0_nROE_15mA (2 << 24) -#define S3C2416_DSC0_nROE_21mA (3 << 24) -#define S3C2416_DSC0_nROE_MASK (3 << 24) - -#endif - -#if defined(CONFIG_CPU_S3C244X) +/* S3C2440 */ #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) -#define S3C2440_SELECT_DSC0 (0) -#define S3C2440_SELECT_DSC1 (1<<31) - -#define S3C2440_DSC_GETSHIFT(x) ((x) & 31) - -#define S3C2440_DSC0_DISABLE (1<<31) - -#define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) -#define S3C2440_DSC0_ADDR_12mA (0<<8) -#define S3C2440_DSC0_ADDR_10mA (1<<8) -#define S3C2440_DSC0_ADDR_8mA (2<<8) -#define S3C2440_DSC0_ADDR_6mA (3<<8) -#define S3C2440_DSC0_ADDR_MASK (3<<8) - -/* D24..D31 */ -#define S3C2440_DSC0_DATA3 (S3C2440_SELECT_DSC0 | 6) -#define S3C2440_DSC0_DATA3_12mA (0<<6) -#define S3C2440_DSC0_DATA3_10mA (1<<6) -#define S3C2440_DSC0_DATA3_8mA (2<<6) -#define S3C2440_DSC0_DATA3_6mA (3<<6) -#define S3C2440_DSC0_DATA3_MASK (3<<6) - -/* D16..D23 */ -#define S3C2440_DSC0_DATA2 (S3C2440_SELECT_DSC0 | 4) -#define S3C2440_DSC0_DATA2_12mA (0<<4) -#define S3C2440_DSC0_DATA2_10mA (1<<4) -#define S3C2440_DSC0_DATA2_8mA (2<<4) -#define S3C2440_DSC0_DATA2_6mA (3<<4) -#define S3C2440_DSC0_DATA2_MASK (3<<4) - -/* D8..D15 */ -#define S3C2440_DSC0_DATA1 (S3C2440_SELECT_DSC0 | 2) -#define S3C2440_DSC0_DATA1_12mA (0<<2) -#define S3C2440_DSC0_DATA1_10mA (1<<2) -#define S3C2440_DSC0_DATA1_8mA (2<<2) -#define S3C2440_DSC0_DATA1_6mA (3<<2) -#define S3C2440_DSC0_DATA1_MASK (3<<2) - -/* D0..D7 */ -#define S3C2440_DSC0_DATA0 (S3C2440_SELECT_DSC0 | 0) -#define S3C2440_DSC0_DATA0_12mA (0<<0) -#define S3C2440_DSC0_DATA0_10mA (1<<0) -#define S3C2440_DSC0_DATA0_8mA (2<<0) -#define S3C2440_DSC0_DATA0_6mA (3<<0) -#define S3C2440_DSC0_DATA0_MASK (3<<0) - -#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) -#define S3C2440_DSC1_SCK1_12mA (0<<28) -#define S3C2440_DSC1_SCK1_10mA (1<<28) -#define S3C2440_DSC1_SCK1_8mA (2<<28) -#define S3C2440_DSC1_SCK1_6mA (3<<28) -#define S3C2440_DSC1_SCK1_MASK (3<<28) - -#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) -#define S3C2440_DSC1_SCK0_12mA (0<<26) -#define S3C2440_DSC1_SCK0_10mA (1<<26) -#define S3C2440_DSC1_SCK0_8mA (2<<26) -#define S3C2440_DSC1_SCK0_6mA (3<<26) -#define S3C2440_DSC1_SCK0_MASK (3<<26) - -#define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) -#define S3C2440_DSC1_SCKE_10mA (0<<24) -#define S3C2440_DSC1_SCKE_8mA (1<<24) -#define S3C2440_DSC1_SCKE_6mA (2<<24) -#define S3C2440_DSC1_SCKE_4mA (3<<24) -#define S3C2440_DSC1_SCKE_MASK (3<<24) - -/* SDRAM nRAS/nCAS */ -#define S3C2440_DSC1_SDR (S3C2440_SELECT_DSC1 | 22) -#define S3C2440_DSC1_SDR_10mA (0<<22) -#define S3C2440_DSC1_SDR_8mA (1<<22) -#define S3C2440_DSC1_SDR_6mA (2<<22) -#define S3C2440_DSC1_SDR_4mA (3<<22) -#define S3C2440_DSC1_SDR_MASK (3<<22) - -/* NAND Flash Controller */ -#define S3C2440_DSC1_NFC (S3C2440_SELECT_DSC1 | 20) -#define S3C2440_DSC1_NFC_10mA (0<<20) -#define S3C2440_DSC1_NFC_8mA (1<<20) -#define S3C2440_DSC1_NFC_6mA (2<<20) -#define S3C2440_DSC1_NFC_4mA (3<<20) -#define S3C2440_DSC1_NFC_MASK (3<<20) - -/* nBE[0..3] */ -#define S3C2440_DSC1_nBE (S3C2440_SELECT_DSC1 | 18) -#define S3C2440_DSC1_nBE_10mA (0<<18) -#define S3C2440_DSC1_nBE_8mA (1<<18) -#define S3C2440_DSC1_nBE_6mA (2<<18) -#define S3C2440_DSC1_nBE_4mA (3<<18) -#define S3C2440_DSC1_nBE_MASK (3<<18) - -#define S3C2440_DSC1_WOE (S3C2440_SELECT_DSC1 | 16) -#define S3C2440_DSC1_WOE_10mA (0<<16) -#define S3C2440_DSC1_WOE_8mA (1<<16) -#define S3C2440_DSC1_WOE_6mA (2<<16) -#define S3C2440_DSC1_WOE_4mA (3<<16) -#define S3C2440_DSC1_WOE_MASK (3<<16) - -#define S3C2440_DSC1_CS7 (S3C2440_SELECT_DSC1 | 14) -#define S3C2440_DSC1_CS7_10mA (0<<14) -#define S3C2440_DSC1_CS7_8mA (1<<14) -#define S3C2440_DSC1_CS7_6mA (2<<14) -#define S3C2440_DSC1_CS7_4mA (3<<14) -#define S3C2440_DSC1_CS7_MASK (3<<14) - -#define S3C2440_DSC1_CS6 (S3C2440_SELECT_DSC1 | 12) -#define S3C2440_DSC1_CS6_10mA (0<<12) -#define S3C2440_DSC1_CS6_8mA (1<<12) -#define S3C2440_DSC1_CS6_6mA (2<<12) -#define S3C2440_DSC1_CS6_4mA (3<<12) -#define S3C2440_DSC1_CS6_MASK (3<<12) - -#define S3C2440_DSC1_CS5 (S3C2440_SELECT_DSC1 | 10) -#define S3C2440_DSC1_CS5_10mA (0<<10) -#define S3C2440_DSC1_CS5_8mA (1<<10) -#define S3C2440_DSC1_CS5_6mA (2<<10) -#define S3C2440_DSC1_CS5_4mA (3<<10) -#define S3C2440_DSC1_CS5_MASK (3<<10) - -#define S3C2440_DSC1_CS4 (S3C2440_SELECT_DSC1 | 8) -#define S3C2440_DSC1_CS4_10mA (0<<8) -#define S3C2440_DSC1_CS4_8mA (1<<8) -#define S3C2440_DSC1_CS4_6mA (2<<8) -#define S3C2440_DSC1_CS4_4mA (3<<8) -#define S3C2440_DSC1_CS4_MASK (3<<8) - -#define S3C2440_DSC1_CS3 (S3C2440_SELECT_DSC1 | 6) -#define S3C2440_DSC1_CS3_10mA (0<<6) -#define S3C2440_DSC1_CS3_8mA (1<<6) -#define S3C2440_DSC1_CS3_6mA (2<<6) -#define S3C2440_DSC1_CS3_4mA (3<<6) -#define S3C2440_DSC1_CS3_MASK (3<<6) - -#define S3C2440_DSC1_CS2 (S3C2440_SELECT_DSC1 | 4) -#define S3C2440_DSC1_CS2_10mA (0<<4) -#define S3C2440_DSC1_CS2_8mA (1<<4) -#define S3C2440_DSC1_CS2_6mA (2<<4) -#define S3C2440_DSC1_CS2_4mA (3<<4) -#define S3C2440_DSC1_CS2_MASK (3<<4) - -#define S3C2440_DSC1_CS1 (S3C2440_SELECT_DSC1 | 2) -#define S3C2440_DSC1_CS1_10mA (0<<2) -#define S3C2440_DSC1_CS1_8mA (1<<2) -#define S3C2440_DSC1_CS1_6mA (2<<2) -#define S3C2440_DSC1_CS1_4mA (3<<2) -#define S3C2440_DSC1_CS1_MASK (3<<2) - -#define S3C2440_DSC1_CS0 (S3C2440_SELECT_DSC1 | 0) -#define S3C2440_DSC1_CS0_10mA (0<<0) -#define S3C2440_DSC1_CS0_8mA (1<<0) -#define S3C2440_DSC1_CS0_6mA (2<<0) -#define S3C2440_DSC1_CS0_4mA (3<<0) -#define S3C2440_DSC1_CS0_MASK (3<<0) - -#endif /* CONFIG_CPU_S3C2440 */ - #endif /* __ASM_ARCH_REGS_DSC_H */ |