diff options
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/dma/nbpfaxi.txt | 8 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt | 12 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/dma/snps-dma.txt | 2 | ||||
| -rw-r--r-- | Documentation/dmaengine/client.txt | 16 | ||||
| -rw-r--r-- | Documentation/dmaengine/dmatest.txt | 10 | ||||
| -rw-r--r-- | Documentation/dmaengine/provider.txt | 2 | ||||
| -rw-r--r-- | Documentation/dmaengine/pxa_dma.txt | 2 |
8 files changed, 35 insertions, 18 deletions
diff --git a/Documentation/devicetree/bindings/dma/nbpfaxi.txt b/Documentation/devicetree/bindings/dma/nbpfaxi.txt index d5e2522b9ec1..d2e1e62e346a 100644 --- a/Documentation/devicetree/bindings/dma/nbpfaxi.txt +++ b/Documentation/devicetree/bindings/dma/nbpfaxi.txt @@ -23,6 +23,14 @@ Required properties #define NBPF_SLAVE_RQ_LEVEL 4 Optional properties: +- max-burst-mem-read: limit burst size for memory reads + (DMA_MEM_TO_MEM/DMA_MEM_TO_DEV) to this value, specified in bytes, rather + than using the maximum burst size allowed by the hardware's buffer size. +- max-burst-mem-write: limit burst size for memory writes + (DMA_DEV_TO_MEM/DMA_MEM_TO_MEM) to this value, specified in bytes, rather + than using the maximum burst size allowed by the hardware's buffer size. + If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM + will use the lower value. You can use dma-channels and dma-requests as described in dma.txt, although they won't be used, this information is derived from the compatibility string. diff --git a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt index fd5618bd8fbc..55492c264d17 100644 --- a/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt +++ b/Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt @@ -5,13 +5,13 @@ memcpy and memset capabilities. It has been designed for virtualized environments. Each HIDMA HW instance consists of multiple DMA channels. These channels -share the same bandwidth. The bandwidth utilization can be parititioned +share the same bandwidth. The bandwidth utilization can be partitioned among channels based on the priority and weight assignments. There are only two priority levels and 15 weigh assignments possible. Other parameters here determine how much of the system bus this HIDMA -instance can use like maximum read/write request and and number of bytes to +instance can use like maximum read/write request and number of bytes to read/write in a single burst. Main node required properties: @@ -47,12 +47,18 @@ When the OS is not in control of the management interface (i.e. it's a guest), the channel nodes appear on their own, not under a management node. Required properties: -- compatible: must contain "qcom,hidma-1.0" +- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1" +for MSI capable HW. - reg: Addresses for the transfer and event channel - interrupts: Should contain the event interrupt - desc-count: Number of asynchronous requests this channel can handle - iommus: required a iommu node +Optional properties for MSI: +- msi-parent : See the generic MSI binding described in + devicetree/bindings/interrupt-controller/msi.txt for a description of the + msi-parent property. + Example: Hypervisor OS configuration: diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt index 5f2ce669789a..3316a9c2e638 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt @@ -24,6 +24,7 @@ Required Properties: - "renesas,dmac-r8a7793" (R-Car M2-N) - "renesas,dmac-r8a7794" (R-Car E2) - "renesas,dmac-r8a7795" (R-Car H3) + - "renesas,dmac-r8a7796" (R-Car M3-W) - reg: base address and length of the registers block for the DMAC diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt index 0f5583293c9c..4775c66f4508 100644 --- a/Documentation/devicetree/bindings/dma/snps-dma.txt +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt @@ -27,6 +27,8 @@ Optional properties: that services interrupts for this device - is_private: The device channels should be marked as private and not for by the general purpose DMA channel allocator. False if not passed. +- multi-block: Multi block transfers supported by hardware. Array property with + one cell per channel. 0: not supported, 1 (default): supported. Example: diff --git a/Documentation/dmaengine/client.txt b/Documentation/dmaengine/client.txt index 9e33189745f0..c72b4563de10 100644 --- a/Documentation/dmaengine/client.txt +++ b/Documentation/dmaengine/client.txt @@ -37,8 +37,8 @@ The slave DMA usage consists of following steps: 2. Set slave and controller specific parameters Next step is always to pass some specific information to the DMA - driver. Most of the generic information which a slave DMA can use - is in struct dma_slave_config. This allows the clients to specify + driver. Most of the generic information which a slave DMA can use + is in struct dma_slave_config. This allows the clients to specify DMA direction, DMA addresses, bus widths, DMA burst lengths etc for the peripheral. @@ -52,7 +52,7 @@ The slave DMA usage consists of following steps: struct dma_slave_config *config) Please see the dma_slave_config structure definition in dmaengine.h - for a detailed explanation of the struct members. Please note + for a detailed explanation of the struct members. Please note that the 'direction' member will be going away as it duplicates the direction given in the prepare call. @@ -101,7 +101,7 @@ The slave DMA usage consists of following steps: desc = dmaengine_prep_slave_sg(chan, sgl, nr_sg, direction, flags); Once a descriptor has been obtained, the callback information can be - added and the descriptor must then be submitted. Some DMA engine + added and the descriptor must then be submitted. Some DMA engine drivers may hold a spinlock between a successful preparation and submission so it is important that these two operations are closely paired. @@ -138,7 +138,7 @@ The slave DMA usage consists of following steps: activity via other DMA engine calls not covered in this document. dmaengine_submit() will not start the DMA operation, it merely adds - it to the pending queue. For this, see step 5, dma_async_issue_pending. + it to the pending queue. For this, see step 5, dma_async_issue_pending. 5. Issue pending DMA requests and wait for callback notification @@ -184,13 +184,13 @@ Further APIs: 3. int dmaengine_resume(struct dma_chan *chan) - Resume a previously paused DMA channel. It is invalid to resume a + Resume a previously paused DMA channel. It is invalid to resume a channel which is not currently paused. 4. enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) - This can be used to check the status of the channel. Please see + This can be used to check the status of the channel. Please see the documentation in include/linux/dmaengine.h for a more complete description of this API. @@ -200,7 +200,7 @@ Further APIs: Note: Not all DMA engine drivers can return reliable information for - a running DMA channel. It is recommended that DMA engine users + a running DMA channel. It is recommended that DMA engine users pause or stop (via dmaengine_terminate_all()) the channel before using this API. diff --git a/Documentation/dmaengine/dmatest.txt b/Documentation/dmaengine/dmatest.txt index dd77a81bdb80..fb683c72dea8 100644 --- a/Documentation/dmaengine/dmatest.txt +++ b/Documentation/dmaengine/dmatest.txt @@ -34,7 +34,7 @@ command: % ls -1 /sys/class/dma/ Once started a message like "dmatest: Started 1 threads using dma0chan0" is -emitted. After that only test failure messages are reported until the test +emitted. After that only test failure messages are reported until the test stops. Note that running a new test will not stop any in progress test. @@ -43,11 +43,11 @@ The following command returns the state of the test. % cat /sys/module/dmatest/parameters/run To wait for test completion userpace can poll 'run' until it is false, or use -the wait parameter. Specifying 'wait=1' when loading the module causes module +the wait parameter. Specifying 'wait=1' when loading the module causes module initialization to pause until a test run has completed, while reading /sys/module/dmatest/parameters/wait waits for any running test to complete -before returning. For example, the following scripts wait for 42 tests -to complete before exiting. Note that if 'iterations' is set to 'infinite' then +before returning. For example, the following scripts wait for 42 tests +to complete before exiting. Note that if 'iterations' is set to 'infinite' then waiting is disabled. Example: @@ -81,7 +81,7 @@ Example of output: The message format is unified across the different types of errors. A number in the parens represents additional information, e.g. error code, error counter, -or status. A test thread also emits a summary line at completion listing the +or status. A test thread also emits a summary line at completion listing the number of tests executed, number that failed, and a result code. Example: diff --git a/Documentation/dmaengine/provider.txt b/Documentation/dmaengine/provider.txt index c4fd47540b31..e33bc1c8ed2c 100644 --- a/Documentation/dmaengine/provider.txt +++ b/Documentation/dmaengine/provider.txt @@ -384,7 +384,7 @@ where to put them) - The descriptor should be prepared for reuse by invoking dmaengine_desc_set_reuse() which will set DMA_CTRL_REUSE. - dmaengine_desc_set_reuse() will succeed only when channel support - reusable descriptor as exhibited by capablities + reusable descriptor as exhibited by capabilities - As a consequence, if a device driver wants to skip the dma_map_sg() and dma_unmap_sg() in between 2 transfers, because the DMA'd data wasn't used, it can resubmit the transfer right after its completion. diff --git a/Documentation/dmaengine/pxa_dma.txt b/Documentation/dmaengine/pxa_dma.txt index 413ef9cfaa4d..0736d44b5438 100644 --- a/Documentation/dmaengine/pxa_dma.txt +++ b/Documentation/dmaengine/pxa_dma.txt @@ -29,7 +29,7 @@ Constraints d) Bandwidth guarantee The PXA architecture has 4 levels of DMAs priorities : high, normal, low. - The high prorities get twice as much bandwidth as the normal, which get twice + The high priorities get twice as much bandwidth as the normal, which get twice as much as the low priorities. A driver should be able to request a priority, especially the real-time ones such as pxa_camera with (big) throughputs. |