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Diffstat (limited to 'Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt')
-rw-r--r-- | Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt deleted file mode 100644 index d57e9df25f4f..000000000000 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ /dev/null @@ -1,48 +0,0 @@ -* Amlogic Meson SAR (Successive Approximation Register) A/D converter - -Required properties: -- compatible: depending on the SoC this should be one of: - - "amlogic,meson8-saradc" for Meson8 - - "amlogic,meson8b-saradc" for Meson8b - - "amlogic,meson8m2-saradc" for Meson8m2 - - "amlogic,meson-gxbb-saradc" for GXBB - - "amlogic,meson-gxl-saradc" for GXL - - "amlogic,meson-gxm-saradc" for GXM - - "amlogic,meson-axg-saradc" for AXG - - "amlogic,meson-g12a-saradc" for AXG - along with the generic "amlogic,meson-saradc" -- reg: the physical base address and length of the registers -- interrupts: the interrupt indicating end of sampling -- clocks: phandle and clock identifier (see clock-names) -- clock-names: mandatory clocks: - - "clkin" for the reference clock (typically XTAL) - - "core" for the SAR ADC core clock - optional clocks: - - "adc_clk" for the ADC (sampling) clock - - "adc_sel" for the ADC (sampling) clock mux -- vref-supply: the regulator supply for the ADC reference voltage -- #io-channel-cells: must be 1, see ../iio-bindings.txt - -Optional properties: -- amlogic,hhi-sysctrl: phandle to the syscon which contains the 5th bit - of the TSC (temperature sensor coefficient) on - Meson8b and Meson8m2 (which used to calibrate the - temperature sensor) -- nvmem-cells: phandle to the temperature_calib eFuse cells -- nvmem-cell-names: if present (to enable the temperature sensor - calibration) this must contain "temperature_calib" - - -Example: - saradc: adc@8680 { - compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; - #io-channel-cells = <1>; - reg = <0x0 0x8680 0x0 0x34>; - interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; - clocks = <&xtal>, - <&clkc CLKID_SAR_ADC>, - <&clkc CLKID_SANA>, - <&clkc CLKID_SAR_ADC_CLK>, - <&clkc CLKID_SAR_ADC_SEL>; - clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; - }; |