diff options
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_ttm.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index bd287c2728c8..3f713c1b5dc1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -29,6 +29,9 @@ #include "nouveau_gem.h" #include "drm_legacy.h" + +#include <core/tegra.h> + static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { @@ -353,16 +356,26 @@ nouveau_ttm_init(struct nouveau_drm *drm) if (drm->agp.bridge || !dma_supported(dev->dev, DMA_BIT_MASK(bits))) bits = 32; + } else if (device->func->tegra) { + struct nvkm_device_tegra *tegra = device->func->tegra(device); - ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); - if (ret) - return ret; + /* + * If the platform can use a IOMMU, then the addressable DMA + * space is constrained by the IOMMU bit + */ + if (tegra->func->iommu_bit) + bits = min(bits, tegra->func->iommu_bit); - ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); - if (ret) - dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); } + ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + return ret; + + ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); + ret = nouveau_ttm_global_init(drm); if (ret) return ret; |