diff options
| author | Lyude <cpaul@redhat.com> | 2016-02-04 18:43:21 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2016-02-10 19:02:42 +0300 |
| commit | 39748841a719c9b4ca41cedc299ca7605a22051c (patch) | |
| tree | 23826b840489ced6d9832a54e30d3aa51c645d3e /net/rfkill | |
| parent | 3d849b02336be103d312c1574d6f7314d5c0bc9f (diff) | |
| download | linux-39748841a719c9b4ca41cedc299ca7605a22051c.tar.xz | |
drm/i915/skl: Fix typo in DPLL_CFGCR1 definition
We accidentally point both cfgcr registers for the second shared DPLL to
the same location in i915_reg.h. This results in a lot of hw pipe state
mismatches whenever we try to do a modeset that requires allocating the
DPLL to a CRTC:
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x80000168, found 0x000004a5)
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 108000, found 49500)
[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 108000, found 49500)
This usually ends up causing blank monitors, since the DPLL never can
get set to the right clock.
Fixes: 086f8e84a085 ("drm/i915: Prefix raw register defines with underscore")
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1454600601-21900-1-git-send-email-cpaul@redhat.com
(cherry picked from commit da3b891b0fb88605bb2d16adaf1ef2a1f16403ba)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'net/rfkill')
0 files changed, 0 insertions, 0 deletions