summaryrefslogtreecommitdiff
path: root/net/ax25/ax25_iface.c
diff options
context:
space:
mode:
authorPaolo Bonzini <pbonzini@redhat.com>2019-10-27 18:23:23 +0300
committerPaolo Bonzini <pbonzini@redhat.com>2019-10-31 14:13:44 +0300
commit9167ab79936206118cc60e47dcb926c3489f3bd5 (patch)
tree62e3c3208dadfa655c87e9917fff8e4ea2cdc7a8 /net/ax25/ax25_iface.c
parenta97b0e773e492ae319a7e981e98962a1060215f9 (diff)
downloadlinux-9167ab79936206118cc60e47dcb926c3489f3bd5.tar.xz
KVM: vmx, svm: always run with EFER.NXE=1 when shadow paging is active
VMX already does so if the host has SMEP, in order to support the combination of CR0.WP=1 and CR4.SMEP=1. However, it is perfectly safe to always do so, and in fact VMX already ends up running with EFER.NXE=1 on old processors that lack the "load EFER" controls, because it may help avoiding a slow MSR write. Removing all the conditionals simplifies the code. SVM does not have similar code, but it should since recent AMD processors do support SMEP. So this patch also makes the code for the two vendors more similar while fixing NPT=0, CR0.WP=1 and CR4.SMEP=1 on AMD processors. Cc: stable@vger.kernel.org Cc: Joerg Roedel <jroedel@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'net/ax25/ax25_iface.c')
0 files changed, 0 insertions, 0 deletions