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| author | Alexander Sverdlin <alexander.sverdlin@nokia.com> | 2019-07-12 15:14:39 +0300 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-08-21 11:09:46 +0300 |
| commit | 913787ca40b9b5981bea1d1157cdd8cb23e12b54 (patch) | |
| tree | 8f09e40d9811c0ecef76c65f1fd900c27f684274 /mm/slub.c | |
| parent | 313aca5a9c781a19537e6cc882511c13eff3bdba (diff) | |
| download | linux-913787ca40b9b5981bea1d1157cdd8cb23e12b54.tar.xz | |
mtd: spi-nor: intel-spi: Whitelist 4B read commands
spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
Flash chips up to 64Mbytes.
D-1500 Integrated PCH documenation however has inconsistencies regarding
FADDR register width and says nothing about particular commands issued
to support 64Mbytes of Flash.
Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
read operations work just fine after SPINOR_OP_READ_4B and
SPINOR_OP_READ_FAST_4B are white-listed (currently only
SPINOR_OP_READ_FAST_4B is used and only for Macronix).
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'mm/slub.c')
0 files changed, 0 insertions, 0 deletions