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authorYishai Hadas <yishaih@nvidia.com>2020-11-21 02:03:33 +0300
committerSaeed Mahameed <saeedm@nvidia.com>2020-11-27 05:43:48 +0300
commit959af5569f57d189b5c4fccae45f16d5ff01aa39 (patch)
tree401f164da356308382c057ca67c3ab6f11627aea /include
parent21adf05d4584c99a07a604224b9cfeddcc6bc47c (diff)
downloadlinux-959af5569f57d189b5c4fccae45f16d5ff01aa39.tar.xz
net/mlx5: Expose other function ifc bits
Expose other function ifc bits to enable setting HCA caps on behalf of other function. In addition, expose vhca_resource_manager bit to control whether the other function functionality is supported by firmware. Signed-off-by: Yishai Hadas <yishaih@nvidia.com> Reviewed-by: Parav Pandit <parav@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 96888f9f822d..3e337386faa8 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1249,7 +1249,8 @@ enum mlx5_fc_bulk_alloc_bitmask {
#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
struct mlx5_ifc_cmd_hca_cap_bits {
- u8 reserved_at_0[0x20];
+ u8 reserved_at_0[0x1f];
+ u8 vhca_resource_manager[0x1];
u8 reserved_at_20[0x3];
u8 event_on_vhca_state_teardown_request[0x1];
@@ -4247,7 +4248,11 @@ struct mlx5_ifc_set_hca_cap_in_bits {
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
- u8 reserved_at_40[0x40];
+ u8 other_function[0x1];
+ u8 reserved_at_41[0xf];
+ u8 function_id[0x10];
+
+ u8 reserved_at_60[0x20];
union mlx5_ifc_hca_cap_union_bits capability;
};