diff options
| author | Keerthy <j-keerthy@ti.com> | 2017-01-13 07:20:12 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2017-01-26 12:00:21 +0300 |
| commit | b5cf3fd827d2e11355c126b44ea625650ebf4d39 (patch) | |
| tree | ea1b09015291512b2e8e36590f60a727a7ed2575 /include/linux/platform_data/gpio-davinci.h | |
| parent | 53d333ac93911dab22d12a78b0a6414f9afb0117 (diff) | |
| download | linux-b5cf3fd827d2e11355c126b44ea625650ebf4d39.tar.xz | |
gpio: davinci: Redesign driver to accommodate ngpios in one gpio chip
The Davinci GPIO driver is implemented to work with one monolithic
Davinci GPIO platform device which may have up to Y(144) gpios.
The Davinci GPIO driver instantiates number of GPIO chips with
max 32 gpio pins per each during initialization and one IRQ domain.
So, the current GPIO's opjects structure is:
<platform device> Davinci GPIO controller
|- <gpio0_chip0> ------|
... |--- irq_domain (hwirq [0..143])
|- <gpio0_chipN> ------|
Current driver creates one chip for every 32 GPIOs in a controller.
This was a limitation earlier now there is no need for that. Hence
redesigning the driver to create one gpio chip for all the ngpio
in the controller.
|- <gpio0_chip0> ------|--- irq_domain (hwirq [0..143]).
The previous discussion on this can be found here:
https://www.spinics.net/lists/linux-omap/msg132869.html
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'include/linux/platform_data/gpio-davinci.h')
| -rw-r--r-- | include/linux/platform_data/gpio-davinci.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/include/linux/platform_data/gpio-davinci.h b/include/linux/platform_data/gpio-davinci.h index 18127c4aa4ba..c62a9438976d 100644 --- a/include/linux/platform_data/gpio-davinci.h +++ b/include/linux/platform_data/gpio-davinci.h @@ -21,19 +21,27 @@ #include <asm-generic/gpio.h> +#define MAX_REGS_BANKS 5 + struct davinci_gpio_platform_data { u32 ngpio; u32 gpio_unbanked; }; +struct davinci_gpio_irq_data { + void __iomem *regs; + struct davinci_gpio_controller *chip; + int bank_num; +}; + struct davinci_gpio_controller { struct gpio_chip chip; struct irq_domain *irq_domain; /* Serialize access to GPIO registers */ spinlock_t lock; - void __iomem *regs; + void __iomem *regs[MAX_REGS_BANKS]; int gpio_unbanked; - unsigned gpio_irq; + unsigned int base_irq; }; /* |