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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2018-01-29 11:55:14 +0300 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2018-01-29 11:55:14 +0300 |
| commit | c8f22b02a8bbc74525d17dd37d39bdf599e68a79 (patch) | |
| tree | b1f5b65b7d5c6c37bddd517f203fef59fe79e375 /include/linux/mtd | |
| parent | 0aede42e98e0dfc64534617332b6a120cfcfe850 (diff) | |
| parent | 23bae78e8a57f0249ed9e3f9c3f40fc1499ce0d4 (diff) | |
| download | linux-c8f22b02a8bbc74525d17dd37d39bdf599e68a79.tar.xz | |
Merge tag 'spi-nor/for-4.16' of git://git.infradead.org/linux-mtd into mtd/next
Pull spi-nor changes from Cyrille Pitchen:
"
This pull-request contains the following notable changes:
Core changes:
* Add support to new ISSI and Cypress/Spansion memory parts.
* Fix support of Micron memories by checking error bits in the FSR.
* Fix update of block-protection bits by reading back the SR.
* Restore the internal state of the SPI flash memory when removing the
device.
Driver changes:
* Maintenance for Freescale, Intel and Metiatek drivers.
* Add support of the direct access mode for the Cadence QSPI controller.
"
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index d0c66a0975cf..de36969eb359 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -61,6 +61,7 @@ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ +#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */ @@ -130,7 +131,10 @@ #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ /* Flag Status Register bits */ -#define FSR_READY BIT(7) +#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */ +#define FSR_E_ERR BIT(5) /* Erase operation status */ +#define FSR_P_ERR BIT(4) /* Program operation status */ +#define FSR_PT_ERR BIT(1) /* Protection error bit */ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ @@ -399,4 +403,10 @@ struct spi_nor_hwcaps { int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); +/** + * spi_nor_restore_addr_mode() - restore the status of SPI NOR + * @nor: the spi_nor structure + */ +void spi_nor_restore(struct spi_nor *nor); + #endif |