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authorAndre Przywara <andre.przywara@arm.com>2016-01-26 18:31:15 +0300
committerChristoffer Dall <christoffer.dall@linaro.org>2016-05-20 16:39:59 +0300
commit621ecd8d2123bc13e140b519e01a18200aeb614c (patch)
tree45c6233e220991ed99275f5a1b60a33b8d4a35a1 /include/kvm
parent78a714aba030395e72d03f0ff8a4c1481956e808 (diff)
downloadlinux-621ecd8d2123bc13e140b519e01a18200aeb614c.tar.xz
KVM: arm/arm64: vgic-new: Add GICv3 SGI system register trap handler
In contrast to GICv2 SGIs in a GICv3 implementation are not triggered by a MMIO write, but with a system register write. KVM knows about that register already, we just need to implement the handler and wire it up to the core KVM/ARM code. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'include/kvm')
-rw-r--r--include/kvm/vgic/vgic.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/kvm/vgic/vgic.h b/include/kvm/vgic/vgic.h
index ff3f9c2abd95..00e3dca10a63 100644
--- a/include/kvm/vgic/vgic.h
+++ b/include/kvm/vgic/vgic.h
@@ -209,6 +209,14 @@ bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu);
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
+#ifdef CONFIG_KVM_ARM_VGIC_V3
+void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
+#else
+static inline void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
+{
+}
+#endif
+
/**
* kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
*