diff options
| author | Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> | 2018-04-26 20:22:32 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-16 01:02:23 +0300 |
| commit | e76e56823a318ca580be4cfc5a6a9269bc70abea (patch) | |
| tree | ba82caea099972bae97ddcd24867f14a76cfc933 /include/dt-bindings/clock | |
| parent | dcb899c47da9ff32e5156ddb9b2867f63ff7c4d0 (diff) | |
| download | linux-e76e56823a318ca580be4cfc5a6a9269bc70abea.tar.xz | |
clk:aspeed: Fix reset bits for PCI/VGA and PECI
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/aspeed-clock.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 513c1b4af7a8..4d01804e7c43 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -45,7 +45,7 @@ #define ASPEED_RESET_JTAG_MASTER 3 #define ASPEED_RESET_MIC 4 #define ASPEED_RESET_PWM 5 -#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_PECI 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 |