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| author | Jianguo Sun <sunjianguo1@huawei.com> | 2018-05-04 11:56:30 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-05-16 01:12:06 +0300 |
| commit | 80820a7bc8eb92bee8dab36668dfc567062b0ccf (patch) | |
| tree | 3c40ddd5f9b54529da953e5c4442d525273fc7b8 /include/dt-bindings/clock | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
| download | linux-80820a7bc8eb92bee8dab36668dfc567062b0ccf.tar.xz | |
clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
There are two USB3 host controllers on Hi3798CV200 SoC.
This commit adds missing clocks for them.
Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/histb-clock.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index fab30b3f78b2..136de24733be 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -62,6 +62,14 @@ #define HISTB_USB2_PHY1_REF_CLK 40 #define HISTB_USB2_PHY2_REF_CLK 41 #define HISTB_COMBPHY0_CLK 42 +#define HISTB_USB3_BUS_CLK 43 +#define HISTB_USB3_UTMI_CLK 44 +#define HISTB_USB3_PIPE_CLK 45 +#define HISTB_USB3_SUSPEND_CLK 46 +#define HISTB_USB3_BUS_CLK1 47 +#define HISTB_USB3_UTMI_CLK1 48 +#define HISTB_USB3_PIPE_CLK1 49 +#define HISTB_USB3_SUSPEND_CLK1 50 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 |