diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2021-02-22 01:10:36 +0300 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2021-02-22 01:10:36 +0300 |
| commit | de1617578849acab8e16c9ffdce39b91fb50639d (patch) | |
| tree | 913a330d92a5ce327a48531f58c78b0d72a109a7 /drivers | |
| parent | 66f73fb3facd42d0a7c899d7f4c712332b28499a (diff) | |
| parent | 8f202f8e9ff38e29694a4bc0a519b4e03c1726ee (diff) | |
| download | linux-de1617578849acab8e16c9ffdce39b91fb50639d.tar.xz | |
Merge tag 'media/v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- some core fixes in VB2 mem2mem support
- some improvements and cleanups in V4L2 async kAPI
- newer controls in V4L2 API for H-264 and HEVC codecs
- allegro-dvt driver was promoted from staging
- new i2c sendor drivers: imx334, ov5648, ov8865
- new automobile camera module: rdacm21
- ipu3 cio2 driver started gained support for some ACPI BIOSes
- new ATSC frontend: MaxLinear mxl692 VSB tuner/demod
- the SMIA/CCS driver gained more support for CSS standard
- several driver fixes, updates and improvements
* tag 'media/v5.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (362 commits)
media: v4l: async: Fix kerneldoc documentation for async functions
media: i2c: max9271: Add MODULE_* macros
media: i2c: Kconfig: Make MAX9271 a module
media: imx334: 'ret' is uninitialized, should have been PTR_ERR()
media: i2c: Add imx334 camera sensor driver
media: dt-bindings: media: Add bindings for imx334
media: ov8856: Configure sensor for GRBG Bayer for all modes
media: i2c: imx219: Implement V4L2_CID_LINK_FREQ control
media: ov5675: fix vflip/hflip control
media: ipu3-cio2: Build bridge only if ACPI is enabled
media: Remove the legacy v4l2-clk API
media: ov6650: Use the generic clock framework
media: mt9m111: Use the generic clock framework
media: ov9640: Use the generic clock framework
media: pxa_camera: Drop the v4l2-clk clock register
media: mach-pxa: Register the camera sensor fixed-rate clock
media: i2c: imx258: get clock from device properties and enable it via runtime PM
media: i2c: imx258: simplify getting state container
media: i2c: imx258: add support for binding via device tree
media: dt-bindings: media: imx258: add bindings for IMX258 sensor
...
Diffstat (limited to 'drivers')
230 files changed, 20213 insertions, 3789 deletions
diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c index cdbc6bf9e4ef..682edd913b3b 100644 --- a/drivers/acpi/utils.c +++ b/drivers/acpi/utils.c @@ -823,12 +823,13 @@ bool acpi_dev_present(const char *hid, const char *uid, s64 hrv) EXPORT_SYMBOL(acpi_dev_present); /** - * acpi_dev_get_first_match_dev - Return the first match of ACPI device + * acpi_dev_get_next_match_dev - Return the next match of ACPI device + * @adev: Pointer to the previous acpi_device matching this @hid, @uid and @hrv * @hid: Hardware ID of the device. * @uid: Unique ID of the device, pass NULL to not check _UID * @hrv: Hardware Revision of the device, pass -1 to not check _HRV * - * Return the first match of ACPI device if a matching device was present + * Return the next match of ACPI device if another matching device was present * at the moment of invocation, or NULL otherwise. * * The caller is responsible to call put_device() on the returned device. @@ -836,8 +837,9 @@ EXPORT_SYMBOL(acpi_dev_present); * See additional information in acpi_dev_present() as well. */ struct acpi_device * -acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) +acpi_dev_get_next_match_dev(struct acpi_device *adev, const char *hid, const char *uid, s64 hrv) { + struct device *start = adev ? &adev->dev : NULL; struct acpi_dev_match_info match = {}; struct device *dev; @@ -845,9 +847,29 @@ acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) match.uid = uid; match.hrv = hrv; - dev = bus_find_device(&acpi_bus_type, NULL, &match, acpi_dev_match_cb); + dev = bus_find_device(&acpi_bus_type, start, &match, acpi_dev_match_cb); return dev ? to_acpi_device(dev) : NULL; } +EXPORT_SYMBOL(acpi_dev_get_next_match_dev); + +/** + * acpi_dev_get_first_match_dev - Return the first match of ACPI device + * @hid: Hardware ID of the device. + * @uid: Unique ID of the device, pass NULL to not check _UID + * @hrv: Hardware Revision of the device, pass -1 to not check _HRV + * + * Return the first match of ACPI device if a matching device was present + * at the moment of invocation, or NULL otherwise. + * + * The caller is responsible to call put_device() on the returned device. + * + * See additional information in acpi_dev_present() as well. + */ +struct acpi_device * +acpi_dev_get_first_match_dev(const char *hid, const char *uid, s64 hrv) +{ + return acpi_dev_get_next_match_dev(NULL, hid, uid, hrv); +} EXPORT_SYMBOL(acpi_dev_get_first_match_dev); /* diff --git a/drivers/base/property.c b/drivers/base/property.c index 35b95c6ac0c6..1421e9548857 100644 --- a/drivers/base/property.c +++ b/drivers/base/property.c @@ -837,9 +837,15 @@ EXPORT_SYMBOL_GPL(fwnode_handle_put); /** * fwnode_device_is_available - check if a device is available for use * @fwnode: Pointer to the fwnode of the device. + * + * For fwnode node types that don't implement the .device_is_available() + * operation, this function returns true. */ bool fwnode_device_is_available(const struct fwnode_handle *fwnode) { + if (!fwnode_has_op(fwnode, device_is_available)) + return true; + return fwnode_call_bool_op(fwnode, device_is_available); } EXPORT_SYMBOL_GPL(fwnode_device_is_available); @@ -1209,7 +1215,14 @@ fwnode_graph_get_endpoint_by_id(const struct fwnode_handle *fwnode, best_ep_id = fwnode_ep.id; } - return best_ep; + if (best_ep) + return best_ep; + + if (fwnode && !IS_ERR_OR_NULL(fwnode->secondary)) + return fwnode_graph_get_endpoint_by_id(fwnode->secondary, port, + endpoint, flags); + + return NULL; } EXPORT_SYMBOL_GPL(fwnode_graph_get_endpoint_by_id); diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c index 45cf8c879d71..37179a8b1ceb 100644 --- a/drivers/base/swnode.c +++ b/drivers/base/swnode.c @@ -457,14 +457,18 @@ software_node_get_next_child(const struct fwnode_handle *fwnode, struct swnode *c = to_swnode(child); if (!p || list_empty(&p->children) || - (c && list_is_last(&c->entry, &p->children))) + (c && list_is_last(&c->entry, &p->children))) { + fwnode_handle_put(child); return NULL; + } if (c) c = list_next_entry(c, entry); else c = list_first_entry(&p->children, struct swnode, entry); - return &c->fwnode; + + fwnode_handle_put(child); + return fwnode_handle_get(&c->fwnode); } static struct fwnode_handle * @@ -550,6 +554,115 @@ software_node_get_reference_args(const struct fwnode_handle *fwnode, return 0; } +static struct fwnode_handle * +swnode_graph_find_next_port(const struct fwnode_handle *parent, + struct fwnode_handle *port) +{ + struct fwnode_handle *old = port; + + while ((port = software_node_get_next_child(parent, old))) { + /* + * fwnode ports have naming style "port@", so we search for any + * children that follow that convention. + */ + if (!strncmp(to_swnode(port)->node->name, "port@", + strlen("port@"))) + return port; + old = port; + } + + return NULL; +} + +static struct fwnode_handle * +software_node_graph_get_next_endpoint(const struct fwnode_handle *fwnode, + struct fwnode_handle *endpoint) +{ + struct swnode *swnode = to_swnode(fwnode); + struct fwnode_handle *parent; + struct fwnode_handle *port; + + if (!swnode) + return NULL; + + if (endpoint) { + port = software_node_get_parent(endpoint); + parent = software_node_get_parent(port); + } else { + parent = software_node_get_named_child_node(fwnode, "ports"); + if (!parent) + parent = software_node_get(&swnode->fwnode); + + port = swnode_graph_find_next_port(parent, NULL); + } + + for (; port; port = swnode_graph_find_next_port(parent, port)) { + endpoint = software_node_get_next_child(port, endpoint); + if (endpoint) { + fwnode_handle_put(port); + break; + } + } + + fwnode_handle_put(parent); + + return endpoint; +} + +static struct fwnode_handle * +software_node_graph_get_remote_endpoint(const struct fwnode_handle *fwnode) +{ + struct swnode *swnode = to_swnode(fwnode); + const struct software_node_ref_args *ref; + const struct property_entry *prop; + + if (!swnode) + return NULL; + + prop = property_entry_get(swnode->node->properties, "remote-endpoint"); + if (!prop || prop->type != DEV_PROP_REF || prop->is_inline) + return NULL; + + ref = prop->pointer; + + return software_node_get(software_node_fwnode(ref[0].node)); +} + +static struct fwnode_handle * +software_node_graph_get_port_parent(struct fwnode_handle *fwnode) +{ + struct swnode *swnode = to_swnode(fwnode); + + swnode = swnode->parent; + if (swnode && !strcmp(swnode->node->name, "ports")) + swnode = swnode->parent; + + return swnode ? software_node_get(&swnode->fwnode) : NULL; +} + +static int +software_node_graph_parse_endpoint(const struct fwnode_handle *fwnode, + struct fwnode_endpoint *endpoint) +{ + struct swnode *swnode = to_swnode(fwnode); + const char *parent_name = swnode->parent->node->name; + int ret; + + if (strlen("port@") >= strlen(parent_name) || + strncmp(parent_name, "port@", strlen("port@"))) + return -EINVAL; + + /* Ports have naming style "port@n", we need to select the n */ + ret = kstrtou32(parent_name + strlen("port@"), 10, &endpoint->port); + if (ret) + return ret; + + endpoint->id = swnode->id; + endpoint->local_fwnode = fwnode; + + return 0; +} + static const struct fwnode_operations software_node_ops = { .get = software_node_get, .put = software_node_put, @@ -561,7 +674,11 @@ static const struct fwnode_operations software_node_ops = { .get_parent = software_node_get_parent, .get_next_child_node = software_node_get_next_child, .get_named_child_node = software_node_get_named_child_node, - .get_reference_args = software_node_get_reference_args + .get_reference_args = software_node_get_reference_args, + .graph_get_next_endpoint = software_node_graph_get_next_endpoint, + .graph_get_remote_endpoint = software_node_graph_get_remote_endpoint, + .graph_get_port_parent = software_node_graph_get_port_parent, + .graph_parse_endpoint = software_node_graph_parse_endpoint, }; /* -------------------------------------------------------------------------- */ @@ -702,7 +819,11 @@ out_err: * software_node_register_nodes - Register an array of software nodes * @nodes: Zero terminated array of software nodes to be registered * - * Register multiple software nodes at once. + * Register multiple software nodes at once. If any node in the array + * has its .parent pointer set (which can only be to another software_node), + * then its parent **must** have been registered before it is; either outside + * of this function or by ordering the array such that parent comes before + * child. */ int software_node_register_nodes(const struct software_node *nodes) { @@ -710,14 +831,23 @@ int software_node_register_nodes(const struct software_node *nodes) int i; for (i = 0; nodes[i].name; i++) { - ret = software_node_register(&nodes[i]); - if (ret) { - software_node_unregister_nodes(nodes); - return ret; + const struct software_node *parent = nodes[i].parent; + + if (parent && !software_node_to_swnode(parent)) { + ret = -EINVAL; + goto err_unregister_nodes; } + + ret = software_node_register(&nodes[i]); + if (ret) + goto err_unregister_nodes; } return 0; + +err_unregister_nodes: + software_node_unregister_nodes(nodes); + return ret; } EXPORT_SYMBOL_GPL(software_node_register_nodes); @@ -725,18 +855,23 @@ EXPORT_SYMBOL_GPL(software_node_register_nodes); * software_node_unregister_nodes - Unregister an array of software nodes * @nodes: Zero terminated array of software nodes to be unregistered * - * Unregister multiple software nodes at once. + * Unregister multiple software nodes at once. If parent pointers are set up + * in any of the software nodes then the array **must** be ordered such that + * parents come before their children. * - * NOTE: Be careful using this call if the nodes had parent pointers set up in - * them before registering. If so, it is wiser to remove the nodes - * individually, in the correct order (child before parent) instead of relying - * on the sequential order of the list of nodes in the array. + * NOTE: If you are uncertain whether the array is ordered such that + * parents will be unregistered before their children, it is wiser to + * remove the nodes individually, in the correct order (child before + * parent). */ void software_node_unregister_nodes(const struct software_node *nodes) { - int i; + unsigned int i = 0; + + while (nodes[i].name) + i++; - for (i = 0; nodes[i].name; i++) + while (i--) software_node_unregister(&nodes[i]); } EXPORT_SYMBOL_GPL(software_node_unregister_nodes); @@ -771,16 +906,23 @@ EXPORT_SYMBOL_GPL(software_node_register_node_group); * software_node_unregister_node_group - Unregister a group of software nodes * @node_group: NULL terminated array of software node pointers to be unregistered * - * Unregister multiple software nodes at once. + * Unregister multiple software nodes at once. The array will be unwound in + * reverse order (i.e. last entry first) and thus if any members of the array are + * children of another member then the children must appear later in the list such + * that they are unregistered first. */ -void software_node_unregister_node_group(const struct software_node **node_group) +void software_node_unregister_node_group( + const struct software_node **node_group) { - unsigned int i; + unsigned int i = 0; if (!node_group) return; - for (i = 0; node_group[i]; i++) + while (node_group[i]) + i++; + + while (i--) software_node_unregister(node_group[i]); } EXPORT_SYMBOL_GPL(software_node_unregister_node_group); diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c index d5d5d28d0b36..79fa36de8a04 100644 --- a/drivers/media/cec/core/cec-adap.c +++ b/drivers/media/cec/core/cec-adap.c @@ -1296,7 +1296,7 @@ static int cec_config_log_addr(struct cec_adapter *adap, /* * If we are unable to get an OK or a NACK after max_retries attempts * (and note that each attempt already consists of four polls), then - * then we assume that something is really weird and that it is not a + * we assume that something is really weird and that it is not a * good idea to try and claim this logical address. */ if (i == max_retries) @@ -1735,7 +1735,7 @@ int __cec_s_log_addrs(struct cec_adapter *adap, const u8 feature_sz = ARRAY_SIZE(log_addrs->features[0]); u8 *features = log_addrs->features[i]; bool op_is_dev_features = false; - unsigned j; + unsigned int j; log_addrs->log_addr[i] = CEC_LOG_ADDR_INVALID; if (log_addrs->log_addr_type[i] > CEC_LOG_ADDR_TYPE_UNREGISTERED) { diff --git a/drivers/media/cec/core/cec-api.c b/drivers/media/cec/core/cec-api.c index f922a2196b2b..769e6b4cddce 100644 --- a/drivers/media/cec/core/cec-api.c +++ b/drivers/media/cec/core/cec-api.c @@ -40,7 +40,7 @@ static __poll_t cec_poll(struct file *filp, poll_wait(filp, &fh->wait, poll); if (!cec_is_registered(adap)) - return EPOLLERR | EPOLLHUP; + return EPOLLERR | EPOLLHUP | EPOLLPRI; mutex_lock(&adap->lock); if (adap->is_configured && adap->transmit_queue_sz < CEC_MAX_MSG_TX_QUEUE_SZ) diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c index 89e38392509c..02281d13505f 100644 --- a/drivers/media/common/videobuf2/videobuf2-core.c +++ b/drivers/media/common/videobuf2/videobuf2-core.c @@ -2374,13 +2374,20 @@ __poll_t vb2_core_poll(struct vb2_queue *q, struct file *file, struct vb2_buffer *vb = NULL; unsigned long flags; + /* + * poll_wait() MUST be called on the first invocation on all the + * potential queues of interest, even if we are not interested in their + * events during this first call. Failure to do so will result in + * queue's events to be ignored because the poll_table won't be capable + * of adding new wait queues thereafter. + */ + poll_wait(file, &q->done_wq, wait); + if (!q->is_output && !(req_events & (EPOLLIN | EPOLLRDNORM))) return 0; if (q->is_output && !(req_events & (EPOLLOUT | EPOLLWRNORM))) return 0; - poll_wait(file, &q->done_wq, wait); - /* * Start file I/O emulator only if streaming API has not been used yet. */ diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c index 3f61f5863bf7..7e96f67c60ba 100644 --- a/drivers/media/common/videobuf2/videobuf2-v4l2.c +++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c @@ -487,11 +487,6 @@ static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct media_device *md !q->ops->buf_out_validate)) return -EINVAL; - if (b->request_fd < 0) { - dprintk(q, 1, "%s: request_fd < 0\n", opname); - return -EINVAL; - } - req = media_request_get_by_fd(mdev, b->request_fd); if (IS_ERR(req)) { dprintk(q, 1, "%s: invalid request_fd\n", opname); diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index 06ea30a689d7..fb35697dd93c 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -984,6 +984,7 @@ static int dvb_frontend_check_parameters(struct dvb_frontend *fe) fe->ops.info.symbol_rate_max); return -EINVAL; } + break; default: break; } diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig index 643b851a6b60..3468b07b62fe 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig @@ -515,7 +515,7 @@ config DVB_RTL2830 config DVB_RTL2832 tristate "Realtek RTL2832 DVB-T" depends on DVB_CORE && I2C && I2C_MUX - select REGMAP + select REGMAP_I2C default m if !MEDIA_SUBDRV_AUTOSELECT help Say Y when you want to support this frontend. @@ -708,6 +708,15 @@ config DVB_S5H1411 An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want to support this frontend. +config DVB_MXL692 + tristate "MaxLinear MXL692 based" + depends on DVB_CORE && I2C + default m if !MEDIA_SUBDRV_AUTOSELECT + help + MaxLinear MxL692 is a combo tuner-demodulator that + supports ATSC 8VSB and QAM modes. Say Y when you want to + support this frontend. + comment "ISDB-T (terrestrial) frontends" depends on DVB_CORE diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile index e9179162658c..b9f47d68e14e 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_DVB_S5H1420) += s5h1420.o obj-$(CONFIG_DVB_LGDT330X) += lgdt330x.o obj-$(CONFIG_DVB_LGDT3305) += lgdt3305.o obj-$(CONFIG_DVB_LGDT3306A) += lgdt3306a.o +obj-$(CONFIG_DVB_MXL692) += mxl692.o obj-$(CONFIG_DVB_LG2160) += lg2160.o obj-$(CONFIG_DVB_CX24123) += cx24123.o obj-$(CONFIG_DVB_LNBH25) += lnbh25.o diff --git a/drivers/media/dvb-frontends/af9033.c b/drivers/media/dvb-frontends/af9033.c index 6a8d78b6edac..785c49b3d307 100644 --- a/drivers/media/dvb-frontends/af9033.c +++ b/drivers/media/dvb-frontends/af9033.c @@ -125,6 +125,7 @@ static int af9033_init(struct dvb_frontend *fe) if (i == ARRAY_SIZE(clock_adc_lut)) { dev_err(&client->dev, "Couldn't find ADC config for clock %d\n", dev->cfg.clock); + ret = -ENODEV; goto err; } @@ -852,6 +853,7 @@ static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr) *snr = *snr * 0xffff / 32; break; default: + ret = -EINVAL; goto err; } } diff --git a/drivers/media/dvb-frontends/cx24120.c b/drivers/media/dvb-frontends/cx24120.c index 2464b63fe0cf..d8acd582c711 100644 --- a/drivers/media/dvb-frontends/cx24120.c +++ b/drivers/media/dvb-frontends/cx24120.c @@ -363,6 +363,7 @@ static void cx24120_check_cmd(struct cx24120_state *state, u8 id) case CMD_DISEQC_BURST: cx24120_msg_mpeg_output_global_config(state, 0); /* Old driver would do a msleep(100) here */ + return; default: return; } diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index 758c95bc3b11..5431f922f55e 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -3338,7 +3338,7 @@ static int cxd2841er_set_frontend_s(struct dvb_frontend *fe) cxd2841er_tuner_set(fe); cxd2841er_tune_done(priv); - timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150; + timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150; i = 0; do { diff --git a/drivers/media/dvb-frontends/dib0090.c b/drivers/media/dvb-frontends/dib0090.c index 08a85831e917..903da33642df 100644 --- a/drivers/media/dvb-frontends/dib0090.c +++ b/drivers/media/dvb-frontends/dib0090.c @@ -1765,6 +1765,8 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front dib0090_write_reg(state, 0x1f, 0x7); *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ state->calibrate &= ~DC_CAL; + break; + default: break; } diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index a57470bf71bf..d7fc2595f15b 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -3294,6 +3294,7 @@ static int dvbt_sc_command(struct drxk_state *state, case OFDM_SC_RA_RAM_CMD_USER_IO: case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM: status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0)); + break; /* All commands yielding 0 results */ case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING: case OFDM_SC_RA_RAM_CMD_SET_TIMER: diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index 39cbb3ea1c9d..b294ba87e934 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -390,6 +390,7 @@ static int m88rs2000_tab_set(struct m88rs2000_state *state, case 0xff: if (tab[i].reg == 0xaa && tab[i].val == 0xff) return 0; + break; case 0x00: break; default: diff --git a/drivers/media/dvb-frontends/mxl692.c b/drivers/media/dvb-frontends/mxl692.c new file mode 100644 index 000000000000..86af831c0176 --- /dev/null +++ b/drivers/media/dvb-frontends/mxl692.c @@ -0,0 +1,1378 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the MaxLinear MxL69x family of combo tuners/demods + * + * Copyright (C) 2020 Brad Love <brad@nextdimension.cc> + * + * based on code: + * Copyright (c) 2016 MaxLinear, Inc. All rights reserved + * which was released under GPL V2 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/mutex.h> +#include <linux/i2c-mux.h> +#include <linux/string.h> +#include <linux/firmware.h> + +#include "mxl692.h" +#include "mxl692_defs.h" + +static const struct dvb_frontend_ops mxl692_ops; + +struct mxl692_dev { + struct dvb_frontend fe; + struct i2c_client *i2c_client; + struct mutex i2c_lock; /* i2c command mutex */ + enum MXL_EAGLE_DEMOD_TYPE_E demod_type; + enum MXL_EAGLE_POWER_MODE_E power_mode; + u32 current_frequency; + int device_type; + int seqnum; + int init_done; +}; + +static int mxl692_i2c_write(struct mxl692_dev *dev, u8 *buffer, u16 buf_len) +{ + int ret = 0; + struct i2c_msg msg = { + .addr = dev->i2c_client->addr, + .flags = 0, + .buf = buffer, + .len = buf_len + }; + + ret = i2c_transfer(dev->i2c_client->adapter, &msg, 1); + if (ret != 1) + dev_dbg(&dev->i2c_client->dev, "i2c write error!\n"); + + return ret; +} + +static int mxl692_i2c_read(struct mxl692_dev *dev, u8 *buffer, u16 buf_len) +{ + int ret = 0; + struct i2c_msg msg = { + .addr = dev->i2c_client->addr, + .flags = I2C_M_RD, + .buf = buffer, + .len = buf_len + }; + + ret = i2c_transfer(dev->i2c_client->adapter, &msg, 1); + if (ret != 1) + dev_dbg(&dev->i2c_client->dev, "i2c read error!\n"); + + return ret; +} + +static int convert_endian(u32 size, u8 *d) +{ + u32 i; + + for (i = 0; i < (size & ~3); i += 4) { + d[i + 0] ^= d[i + 3]; + d[i + 3] ^= d[i + 0]; + d[i + 0] ^= d[i + 3]; + + d[i + 1] ^= d[i + 2]; + d[i + 2] ^= d[i + 1]; + d[i + 1] ^= d[i + 2]; + } + + switch (size & 3) { + case 0: + case 1: + /* do nothing */ + break; + case 2: + d[i + 0] ^= d[i + 1]; + d[i + 1] ^= d[i + 0]; + d[i + 0] ^= d[i + 1]; + break; + + case 3: + d[i + 0] ^= d[i + 2]; + d[i + 2] ^= d[i + 0]; + d[i + 0] ^= d[i + 2]; + break; + } + return size; +} + +static int convert_endian_n(int n, u32 size, u8 *d) +{ + int i, count = 0; + + for (i = 0; i < n; i += size) + count += convert_endian(size, d + i); + return count; +} + +static void mxl692_tx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer) +{ +#ifdef __BIG_ENDIAN + return; +#endif + buffer += MXL_EAGLE_HOST_MSG_HEADER_SIZE; /* skip API header */ + + switch (opcode) { + case MXL_EAGLE_OPCODE_DEVICE_INTR_MASK_SET: + case MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET: + case MXL_EAGLE_OPCODE_SMA_TRANSMIT_SET: + buffer += convert_endian(sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_PARAMS_SET: + buffer += 5; + buffer += convert_endian(2 * sizeof(u32), buffer); + break; + default: + /* no swapping - all get opcodes */ + /* ATSC/OOB no swapping */ + break; + } +} + +static void mxl692_rx_swap(enum MXL_EAGLE_OPCODE_E opcode, u8 *buffer) +{ +#ifdef __BIG_ENDIAN + return; +#endif + buffer += MXL_EAGLE_HOST_MSG_HEADER_SIZE; /* skip API header */ + + switch (opcode) { + case MXL_EAGLE_OPCODE_TUNER_AGC_STATUS_GET: + buffer++; + buffer += convert_endian(2 * sizeof(u16), buffer); + break; + case MXL_EAGLE_OPCODE_ATSC_STATUS_GET: + buffer += convert_endian_n(2, sizeof(u16), buffer); + buffer += convert_endian(sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET: + buffer += convert_endian(3 * sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_FFE_TAPS_GET: + buffer += convert_endian_n(24, sizeof(u16), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_STATUS_GET: + buffer += 8; + buffer += convert_endian_n(2, sizeof(u16), buffer); + buffer += convert_endian(sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_ERROR_COUNTERS_GET: + buffer += convert_endian(7 * sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_CONSTELLATION_VALUE_GET: + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_START_GET: + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET: + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_END_GET: + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_START_GET: + buffer += convert_endian_n(24, sizeof(u16), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_END_GET: + buffer += convert_endian_n(8, sizeof(u16), buffer); + break; + case MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_FFE_GET: + buffer += convert_endian_n(17, sizeof(u16), buffer); + break; + case MXL_EAGLE_OPCODE_OOB_ERROR_COUNTERS_GET: + buffer += convert_endian(3 * sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_OOB_STATUS_GET: + buffer += convert_endian_n(2, sizeof(u16), buffer); + buffer += convert_endian(sizeof(u32), buffer); + break; + case MXL_EAGLE_OPCODE_SMA_RECEIVE_GET: + buffer += convert_endian(sizeof(u32), buffer); + break; + default: + /* no swapping - all set opcodes */ + break; + } +} + +static u32 mxl692_checksum(u8 *buffer, u32 size) +{ + u32 ix, div_size; + u32 cur_cksum = 0; + __be32 *buf; + + div_size = DIV_ROUND_UP(size, 4); + + buf = (__be32 *)buffer; + for (ix = 0; ix < div_size; ix++) + cur_cksum += be32_to_cpu(buf[ix]); + + cur_cksum ^= 0xDEADBEEF; + + return cur_cksum; +} + +static int mxl692_validate_fw_header(struct mxl692_dev *dev, + const u8 *buffer, u32 buf_len) +{ + int status = 0; + u32 ix, temp; + __be32 *local_buf = NULL; + u8 temp_cksum = 0; + const u8 fw_hdr[] = { 0x4D, 0x31, 0x10, 0x02, 0x40, 0x00, 0x00, 0x80 }; + + if (memcmp(buffer, fw_hdr, 8) != 0) { + status = -EINVAL; + goto err_finish; + } + + local_buf = (__be32 *)(buffer + 8); + temp = be32_to_cpu(*local_buf); + + if ((buf_len - 16) != temp >> 8) { + status = -EINVAL; + goto err_finish; + } + + for (ix = 16; ix < buf_len; ix++) + temp_cksum += buffer[ix]; + + if (temp_cksum != buffer[11]) + status = -EINVAL; + +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "failed\n"); + return status; +} + +static int mxl692_write_fw_block(struct mxl692_dev *dev, const u8 *buffer, + u32 buf_len, u32 *index) +{ + int status = 0; + u32 ix = 0, total_len = 0, addr = 0, chunk_len = 0, prevchunk_len = 0; + u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL; + int payload_max = MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_MHEADER_SIZE; + + ix = *index; + + if (buffer[ix] == 0x53) { + total_len = buffer[ix + 1] << 16 | buffer[ix + 2] << 8 | buffer[ix + 3]; + total_len = (total_len + 3) & ~3; + addr = buffer[ix + 4] << 24 | buffer[ix + 5] << 16 | + buffer[ix + 6] << 8 | buffer[ix + 7]; + ix += MXL_EAGLE_FW_SEGMENT_HEADER_SIZE; + + while ((total_len > 0) && (status == 0)) { + plocal_buf = local_buf; + chunk_len = (total_len < payload_max) ? total_len : payload_max; + + *plocal_buf++ = 0xFC; + *plocal_buf++ = chunk_len + sizeof(u32); + + *(u32 *)plocal_buf = addr + prevchunk_len; +#ifdef __BIG_ENDIAN + convert_endian(sizeof(u32), plocal_buf); +#endif + plocal_buf += sizeof(u32); + + memcpy(plocal_buf, &buffer[ix], chunk_len); + convert_endian(chunk_len, plocal_buf); + if (mxl692_i2c_write(dev, local_buf, + (chunk_len + MXL_EAGLE_I2C_MHEADER_SIZE)) < 0) { + status = -EREMOTEIO; + break; + } + + prevchunk_len += chunk_len; + total_len -= chunk_len; + ix += chunk_len; + } + *index = ix; + } else { + status = -EINVAL; + } + + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + + return status; +} + +static int mxl692_memwrite(struct mxl692_dev *dev, u32 addr, + u8 *buffer, u32 size) +{ + int status = 0, total_len = 0; + u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL; + + total_len = size; + total_len = (total_len + 3) & ~3; /* 4 byte alignment */ + + if (total_len > (MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_MHEADER_SIZE)) + dev_dbg(&dev->i2c_client->dev, "hrmph?\n"); + + plocal_buf = local_buf; + + *plocal_buf++ = 0xFC; + *plocal_buf++ = total_len + sizeof(u32); + + *(u32 *)plocal_buf = addr; + plocal_buf += sizeof(u32); + + memcpy(plocal_buf, buffer, total_len); +#ifdef __BIG_ENDIAN + convert_endian(sizeof(u32) + total_len, local_buf + 2); +#endif + if (mxl692_i2c_write(dev, local_buf, + (total_len + MXL_EAGLE_I2C_MHEADER_SIZE)) < 0) { + status = -EREMOTEIO; + goto err_finish; + } + + return status; +err_finish: + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_memread(struct mxl692_dev *dev, u32 addr, + u8 *buffer, u32 size) +{ + int status = 0; + u8 local_buf[MXL_EAGLE_I2C_MHEADER_SIZE] = {}, *plocal_buf = NULL; + + plocal_buf = local_buf; + + *plocal_buf++ = 0xFB; + *plocal_buf++ = sizeof(u32); + *(u32 *)plocal_buf = addr; +#ifdef __BIG_ENDIAN + convert_endian(sizeof(u32), plocal_buf); +#endif + mutex_lock(&dev->i2c_lock); + + if (mxl692_i2c_write(dev, local_buf, MXL_EAGLE_I2C_MHEADER_SIZE) > 0) { + size = (size + 3) & ~3; /* 4 byte alignment */ + status = mxl692_i2c_read(dev, buffer, (u16)size) < 0 ? -EREMOTEIO : 0; +#ifdef __BIG_ENDIAN + if (status == 0) + convert_endian(size, buffer); +#endif + } else { + status = -EREMOTEIO; + } + + mutex_unlock(&dev->i2c_lock); + + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + + return status; +} + +static const char *mxl692_opcode_string(u8 opcode) +{ + if (opcode >= 0 && opcode <= MXL_EAGLE_OPCODE_INTERNAL) + return MXL_EAGLE_OPCODE_STRING[opcode]; + + return "invalid opcode"; +} + +static int mxl692_opwrite(struct mxl692_dev *dev, u8 *buffer, + u32 size) +{ + int status = 0, total_len = 0; + u8 local_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}, *plocal_buf = NULL; + struct MXL_EAGLE_HOST_MSG_HEADER_T *tx_hdr = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)buffer; + + total_len = size; + total_len = (total_len + 3) & ~3; /* 4 byte alignment */ + + if (total_len > (MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_PHEADER_SIZE)) + dev_dbg(&dev->i2c_client->dev, "hrmph?\n"); + + plocal_buf = local_buf; + + *plocal_buf++ = 0xFE; + *plocal_buf++ = (u8)total_len; + + memcpy(plocal_buf, buffer, total_len); + convert_endian(total_len, plocal_buf); + + if (mxl692_i2c_write(dev, local_buf, + (total_len + MXL_EAGLE_I2C_PHEADER_SIZE)) < 0) { + status = -EREMOTEIO; + goto err_finish; + } +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "opcode %s err %d\n", + mxl692_opcode_string(tx_hdr->opcode), status); + return status; +} + +static int mxl692_opread(struct mxl692_dev *dev, u8 *buffer, + u32 size) +{ + int status = 0; + u32 ix = 0; + u8 local_buf[MXL_EAGLE_I2C_PHEADER_SIZE] = {}; + + local_buf[0] = 0xFD; + local_buf[1] = 0; + + if (mxl692_i2c_write(dev, local_buf, MXL_EAGLE_I2C_PHEADER_SIZE) > 0) { + size = (size + 3) & ~3; /* 4 byte alignment */ + + /* Read in 4 byte chunks */ + for (ix = 0; ix < size; ix += 4) { + if (mxl692_i2c_read(dev, buffer + ix, 4) < 0) { + dev_dbg(&dev->i2c_client->dev, "ix=%d size=%d\n", ix, size); + status = -EREMOTEIO; + goto err_finish; + } + } + convert_endian(size, buffer); + } else { + status = -EREMOTEIO; + } +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_i2c_writeread(struct mxl692_dev *dev, + u8 opcode, + u8 *tx_payload, + u8 tx_payload_size, + u8 *rx_payload, + u8 rx_payload_expected) +{ + int status = 0, timeout = 40; + u8 tx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + u32 resp_checksum = 0, resp_checksum_tmp = 0; + struct MXL_EAGLE_HOST_MSG_HEADER_T *tx_header; + struct MXL_EAGLE_HOST_MSG_HEADER_T *rx_header; + + mutex_lock(&dev->i2c_lock); + + if ((tx_payload_size + MXL_EAGLE_HOST_MSG_HEADER_SIZE) > + (MXL_EAGLE_MAX_I2C_PACKET_SIZE - MXL_EAGLE_I2C_PHEADER_SIZE)) { + status = -EINVAL; + goto err_finish; + } + + tx_header = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)tx_buf; + tx_header->opcode = opcode; + tx_header->seqnum = dev->seqnum++; + tx_header->payload_size = tx_payload_size; + tx_header->checksum = 0; + + if (dev->seqnum == 0) + dev->seqnum = 1; + + if (tx_payload && tx_payload_size > 0) + memcpy(&tx_buf[MXL_EAGLE_HOST_MSG_HEADER_SIZE], tx_payload, tx_payload_size); + + mxl692_tx_swap(opcode, tx_buf); + + tx_header->checksum = 0; + tx_header->checksum = mxl692_checksum(tx_buf, + MXL_EAGLE_HOST_MSG_HEADER_SIZE + tx_payload_size); +#ifdef __LITTLE_ENDIAN + convert_endian(4, (u8 *)&tx_header->checksum); /* cksum is big endian */ +#endif + /* send Tx message */ + status = mxl692_opwrite(dev, tx_buf, + tx_payload_size + MXL_EAGLE_HOST_MSG_HEADER_SIZE); + if (status) { + status = -EREMOTEIO; + goto err_finish; + } + + /* receive Rx message (polling) */ + rx_header = (struct MXL_EAGLE_HOST_MSG_HEADER_T *)rx_buf; + + do { + status = mxl692_opread(dev, rx_buf, + rx_payload_expected + MXL_EAGLE_HOST_MSG_HEADER_SIZE); + usleep_range(1000, 2000); + timeout--; + } while ((timeout > 0) && (status == 0) && + (rx_header->seqnum == 0) && + (rx_header->checksum == 0)); + + if (timeout == 0 || status) { + dev_dbg(&dev->i2c_client->dev, "timeout=%d status=%d\n", + timeout, status); + status = -ETIMEDOUT; + goto err_finish; + } + + if (rx_header->status) { + dev_dbg(&dev->i2c_client->dev, "rx header status code: %d\n", rx_header->status); + status = -EREMOTEIO; + goto err_finish; + } + + if (rx_header->seqnum != tx_header->seqnum || + rx_header->opcode != tx_header->opcode || + rx_header->payload_size != rx_payload_expected) { + dev_dbg(&dev->i2c_client->dev, "Something failed seq=%s opcode=%s pSize=%s\n", + rx_header->seqnum != tx_header->seqnum ? "X" : "0", + rx_header->opcode != tx_header->opcode ? "X" : "0", + rx_header->payload_size != rx_payload_expected ? "X" : "0"); + if (rx_header->payload_size != rx_payload_expected) + dev_dbg(&dev->i2c_client->dev, + "rx_header->payloadSize=%d rx_payload_expected=%d\n", + rx_header->payload_size, rx_payload_expected); + status = -EREMOTEIO; + goto err_finish; + } + + resp_checksum = rx_header->checksum; + rx_header->checksum = 0; + + resp_checksum_tmp = mxl692_checksum(rx_buf, + MXL_EAGLE_HOST_MSG_HEADER_SIZE + rx_header->payload_size); +#ifdef __LITTLE_ENDIAN + convert_endian(4, (u8 *)&resp_checksum_tmp); /* cksum is big endian */ +#endif + if (resp_checksum != resp_checksum_tmp) { + dev_dbg(&dev->i2c_client->dev, "rx checksum failure\n"); + status = -EREMOTEIO; + goto err_finish; + } + + mxl692_rx_swap(rx_header->opcode, rx_buf); + + if (rx_header->payload_size > 0) { + if (!rx_payload) { + dev_dbg(&dev->i2c_client->dev, "no rx payload?!?\n"); + status = -EREMOTEIO; + goto err_finish; + } + memcpy(rx_payload, rx_buf + MXL_EAGLE_HOST_MSG_HEADER_SIZE, + rx_header->payload_size); + } +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + + mutex_unlock(&dev->i2c_lock); + return status; +} + +static int mxl692_fwdownload(struct mxl692_dev *dev, + const u8 *firmware_buf, u32 buf_len) +{ + int status = 0; + u32 ix, reg_val = 0x1; + u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + struct MXL_EAGLE_DEV_STATUS_T *dev_status; + + if (buf_len < MXL_EAGLE_FW_HEADER_SIZE || + buf_len > MXL_EAGLE_FW_MAX_SIZE_IN_KB * 1000) + return -EINVAL; + + mutex_lock(&dev->i2c_lock); + + dev_dbg(&dev->i2c_client->dev, "\n"); + + status = mxl692_validate_fw_header(dev, firmware_buf, buf_len); + if (status) + goto err_finish; + + ix = 16; + status = mxl692_write_fw_block(dev, firmware_buf, buf_len, &ix); /* DRAM */ + if (status) + goto err_finish; + + status = mxl692_write_fw_block(dev, firmware_buf, buf_len, &ix); /* IRAM */ + if (status) + goto err_finish; + + /* release CPU from reset */ + status = mxl692_memwrite(dev, 0x70000018, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + mutex_unlock(&dev->i2c_lock); + + if (status == 0) { + /* verify FW is alive */ + usleep_range(MXL_EAGLE_FW_LOAD_TIME * 1000, (MXL_EAGLE_FW_LOAD_TIME + 5) * 1000); + dev_status = (struct MXL_EAGLE_DEV_STATUS_T *)&rx_buf; + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_DEVICE_STATUS_GET, + NULL, + 0, + (u8 *)dev_status, + sizeof(struct MXL_EAGLE_DEV_STATUS_T)); + } + + return status; +err_finish: + mutex_unlock(&dev->i2c_lock); + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_get_versions(struct mxl692_dev *dev) +{ + int status = 0; + struct MXL_EAGLE_DEV_VER_T dev_ver = {}; + static const char * const chip_id[] = {"N/A", "691", "248", "692"}; + + status = mxl692_i2c_writeread(dev, MXL_EAGLE_OPCODE_DEVICE_VERSION_GET, + NULL, + 0, + (u8 *)&dev_ver, + sizeof(struct MXL_EAGLE_DEV_VER_T)); + if (status) + return status; + + dev_info(&dev->i2c_client->dev, "MxL692_DEMOD Chip ID: %s\n", + chip_id[dev_ver.chip_id]); + + dev_info(&dev->i2c_client->dev, + "MxL692_DEMOD FW Version: %d.%d.%d.%d_RC%d\n", + dev_ver.firmware_ver[0], + dev_ver.firmware_ver[1], + dev_ver.firmware_ver[2], + dev_ver.firmware_ver[3], + dev_ver.firmware_ver[4]); + + return status; +} + +static int mxl692_reset(struct mxl692_dev *dev) +{ + int status = 0; + u32 dev_type = MXL_EAGLE_DEVICE_MAX, reg_val = 0x2; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + /* legacy i2c override */ + status = mxl692_memwrite(dev, 0x80000100, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* verify sku */ + status = mxl692_memread(dev, 0x70000188, (u8 *)&dev_type, sizeof(u32)); + if (status) + goto err_finish; + + if (dev_type != dev->device_type) + goto err_finish; + +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_config_regulators(struct mxl692_dev *dev, + enum MXL_EAGLE_POWER_SUPPLY_SOURCE_E power_supply) +{ + int status = 0; + u32 reg_val; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + /* configure main regulator according to the power supply source */ + status = mxl692_memread(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val &= 0x00FFFFFF; + reg_val |= (power_supply == MXL_EAGLE_POWER_SUPPLY_SOURCE_SINGLE) ? + 0x14000000 : 0x10000000; + + status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* configure digital regulator to high current mode */ + status = mxl692_memread(dev, 0x90000018, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val |= 0x800; + + status = mxl692_memwrite(dev, 0x90000018, (u8 *)®_val, sizeof(u32)); + +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_config_xtal(struct mxl692_dev *dev, + struct MXL_EAGLE_DEV_XTAL_T *dev_xtal) +{ + int status = 0; + u32 reg_val, reg_val1; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + status = mxl692_memread(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* set XTAL capacitance */ + reg_val &= 0xFFFFFFE0; + reg_val |= dev_xtal->xtal_cap; + + /* set CLK OUT */ + reg_val = dev_xtal->clk_out_enable ? (reg_val | 0x0100) : (reg_val & 0xFFFFFEFF); + + status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* set CLK OUT divider */ + reg_val = dev_xtal->clk_out_div_enable ? (reg_val | 0x0200) : (reg_val & 0xFFFFFDFF); + + status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* set XTAL sharing */ + reg_val = dev_xtal->xtal_sharing_enable ? (reg_val | 0x010400) : (reg_val & 0xFFFEFBFF); + + status = mxl692_memwrite(dev, 0x90000000, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + /* enable/disable XTAL calibration, based on master/slave device */ + status = mxl692_memread(dev, 0x90000030, (u8 *)®_val1, sizeof(u32)); + if (status) + goto err_finish; + + if (dev_xtal->xtal_calibration_enable) { + /* enable XTAL calibration and set XTAL amplitude to a higher value */ + reg_val1 &= 0xFFFFFFFD; + reg_val1 |= 0x30; + + status = mxl692_memwrite(dev, 0x90000030, (u8 *)®_val1, sizeof(u32)); + if (status) + goto err_finish; + } else { + /* disable XTAL calibration */ + reg_val1 |= 0x2; + + status = mxl692_memwrite(dev, 0x90000030, (u8 *)®_val1, sizeof(u32)); + if (status) + goto err_finish; + + /* set XTAL bias value */ + status = mxl692_memread(dev, 0x9000002c, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val &= 0xC0FFFFFF; + reg_val |= 0xA000000; + + status = mxl692_memwrite(dev, 0x9000002c, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + } + + /* start XTAL calibration */ + status = mxl692_memread(dev, 0x70000010, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val |= 0x8; + + status = mxl692_memwrite(dev, 0x70000010, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + status = mxl692_memread(dev, 0x70000018, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val |= 0x10; + + status = mxl692_memwrite(dev, 0x70000018, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + status = mxl692_memread(dev, 0x9001014c, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val &= 0xFFFFEFFF; + + status = mxl692_memwrite(dev, 0x9001014c, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + reg_val |= 0x1000; + + status = mxl692_memwrite(dev, 0x9001014c, (u8 *)®_val, sizeof(u32)); + if (status) + goto err_finish; + + usleep_range(45000, 55000); + +err_finish: + if (status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_powermode(struct mxl692_dev *dev, + enum MXL_EAGLE_POWER_MODE_E power_mode) +{ + int status = 0; + u8 mode = power_mode; + + dev_dbg(&dev->i2c_client->dev, "%s\n", + power_mode == MXL_EAGLE_POWER_MODE_SLEEP ? "sleep" : "active"); + + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_DEVICE_POWERMODE_SET, + &mode, + sizeof(u8), + NULL, + 0); + if (status) { + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; + } + + dev->power_mode = power_mode; + + return status; +} + +static int mxl692_init(struct dvb_frontend *fe) +{ + struct mxl692_dev *dev = fe->demodulator_priv; + struct i2c_client *client = dev->i2c_client; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int status = 0; + const struct firmware *firmware; + struct MXL_EAGLE_DEV_XTAL_T xtal_config = {}; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + if (dev->init_done) + goto warm; + + dev->seqnum = 1; + + status = mxl692_reset(dev); + if (status) + goto err; + + usleep_range(50 * 1000, 60 * 1000); /* was 1000! */ + + status = mxl692_config_regulators(dev, MXL_EAGLE_POWER_SUPPLY_SOURCE_DUAL); + if (status) + goto err; + + xtal_config.xtal_cap = 26; + xtal_config.clk_out_div_enable = 0; + xtal_config.clk_out_enable = 0; + xtal_config.xtal_calibration_enable = 0; + xtal_config.xtal_sharing_enable = 1; + status = mxl692_config_xtal(dev, &xtal_config); + if (status) + goto err; + + status = request_firmware(&firmware, MXL692_FIRMWARE, &client->dev); + if (status) { + dev_dbg(&dev->i2c_client->dev, "firmware missing? %s\n", + MXL692_FIRMWARE); + goto err; + } + + status = mxl692_fwdownload(dev, firmware->data, firmware->size); + if (status) + goto err_release_firmware; + + release_firmware(firmware); + + status = mxl692_get_versions(dev); + if (status) + goto err; + + dev->power_mode = MXL_EAGLE_POWER_MODE_SLEEP; +warm: + /* Config Device Power Mode */ + if (dev->power_mode != MXL_EAGLE_POWER_MODE_ACTIVE) { + status = mxl692_powermode(dev, MXL_EAGLE_POWER_MODE_ACTIVE); + if (status) + goto err; + + usleep_range(50 * 1000, 60 * 1000); /* was 500! */ + } + + /* Init stats here to indicate which stats are supported */ + c->cnr.len = 1; + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_error.len = 1; + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.len = 1; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->block_error.len = 1; + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + + dev->init_done = 1; + return 0; +err_release_firmware: + release_firmware(firmware); +err: + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_sleep(struct dvb_frontend *fe) +{ + struct mxl692_dev *dev = fe->demodulator_priv; + + if (dev->power_mode != MXL_EAGLE_POWER_MODE_SLEEP) + mxl692_powermode(dev, MXL_EAGLE_POWER_MODE_SLEEP); + + return 0; +} + +static int mxl692_set_frontend(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *p = &fe->dtv_property_cache; + struct mxl692_dev *dev = fe->demodulator_priv; + + int status = 0; + enum MXL_EAGLE_DEMOD_TYPE_E demod_type; + struct MXL_EAGLE_MPEGOUT_PARAMS_T mpeg_params = {}; + enum MXL_EAGLE_QAM_DEMOD_ANNEX_TYPE_E qam_annex = MXL_EAGLE_QAM_DEMOD_ANNEX_B; + struct MXL_EAGLE_QAM_DEMOD_PARAMS_T qam_params = {}; + struct MXL_EAGLE_TUNER_CHANNEL_PARAMS_T tuner_params = {}; + u8 op_param = 0; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + switch (p->modulation) { + case VSB_8: + demod_type = MXL_EAGLE_DEMOD_TYPE_ATSC; + break; + case QAM_AUTO: + case QAM_64: + case QAM_128: + case QAM_256: + demod_type = MXL_EAGLE_DEMOD_TYPE_QAM; + break; + default: + return -EINVAL; + } + + if (dev->current_frequency == p->frequency && dev->demod_type == demod_type) { + dev_dbg(&dev->i2c_client->dev, "already set up\n"); + return 0; + } + + dev->current_frequency = -1; + dev->demod_type = -1; + + op_param = demod_type; + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_DEVICE_DEMODULATOR_TYPE_SET, + &op_param, + sizeof(u8), + NULL, + 0); + if (status) { + dev_dbg(&dev->i2c_client->dev, + "DEVICE_DEMODULATOR_TYPE_SET...FAIL err 0x%x\n", status); + goto err; + } + + usleep_range(20 * 1000, 30 * 1000); /* was 500! */ + + mpeg_params.mpeg_parallel = 0; + mpeg_params.msb_first = MXL_EAGLE_DATA_SERIAL_MSB_1ST; + mpeg_params.mpeg_sync_pulse_width = MXL_EAGLE_DATA_SYNC_WIDTH_BIT; + mpeg_params.mpeg_valid_pol = MXL_EAGLE_CLOCK_POSITIVE; + mpeg_params.mpeg_sync_pol = MXL_EAGLE_CLOCK_POSITIVE; + mpeg_params.mpeg_clk_pol = MXL_EAGLE_CLOCK_NEGATIVE; + mpeg_params.mpeg3wire_mode_enable = 0; + mpeg_params.mpeg_clk_freq = MXL_EAGLE_MPEG_CLOCK_27MHZ; + + switch (demod_type) { + case MXL_EAGLE_DEMOD_TYPE_ATSC: + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET, + (u8 *)&mpeg_params, + sizeof(struct MXL_EAGLE_MPEGOUT_PARAMS_T), + NULL, + 0); + if (status) + goto err; + break; + case MXL_EAGLE_DEMOD_TYPE_QAM: + if (qam_annex == MXL_EAGLE_QAM_DEMOD_ANNEX_A) + mpeg_params.msb_first = MXL_EAGLE_DATA_SERIAL_LSB_1ST; + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET, + (u8 *)&mpeg_params, + sizeof(struct MXL_EAGLE_MPEGOUT_PARAMS_T), + NULL, + 0); + if (status) + goto err; + + qam_params.annex_type = qam_annex; + qam_params.qam_type = MXL_EAGLE_QAM_DEMOD_AUTO; + qam_params.iq_flip = MXL_EAGLE_DEMOD_IQ_AUTO; + if (p->modulation == QAM_64) + qam_params.symbol_rate_hz = 5057000; + else + qam_params.symbol_rate_hz = 5361000; + + qam_params.symbol_rate_256qam_hz = 5361000; + + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_QAM_PARAMS_SET, + (u8 *)&qam_params, + sizeof(struct MXL_EAGLE_QAM_DEMOD_PARAMS_T), + NULL, 0); + if (status) + goto err; + + break; + default: + break; + } + + usleep_range(20 * 1000, 30 * 1000); /* was 500! */ + + tuner_params.freq_hz = p->frequency; + tuner_params.bandwidth = MXL_EAGLE_TUNER_BW_6MHZ; + tuner_params.tune_mode = MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_VIEW; + + dev_dbg(&dev->i2c_client->dev, " Tuning Freq: %d %s\n", tuner_params.freq_hz, + demod_type == MXL_EAGLE_DEMOD_TYPE_ATSC ? "ATSC" : "QAM"); + + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET, + (u8 *)&tuner_params, + sizeof(struct MXL_EAGLE_TUNER_CHANNEL_PARAMS_T), + NULL, + 0); + if (status) + goto err; + + usleep_range(20 * 1000, 30 * 1000); /* was 500! */ + + switch (demod_type) { + case MXL_EAGLE_DEMOD_TYPE_ATSC: + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_ATSC_INIT_SET, + NULL, 0, NULL, 0); + if (status) + goto err; + break; + case MXL_EAGLE_DEMOD_TYPE_QAM: + status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_QAM_RESTART_SET, + NULL, 0, NULL, 0); + if (status) + goto err; + break; + default: + break; + } + + dev->demod_type = demod_type; + dev->current_frequency = p->frequency; + + return 0; +err: + dev_dbg(&dev->i2c_client->dev, "err %d\n", status); + return status; +} + +static int mxl692_get_frontend(struct dvb_frontend *fe, + struct dtv_frontend_properties *p) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + + p->modulation = c->modulation; + p->frequency = c->frequency; + + return 0; +} + +static int mxl692_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct mxl692_dev *dev = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *atsc_status; + struct MXL_EAGLE_QAM_DEMOD_STATUS_T *qam_status; + enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type; + int mxl_status = 0; + + *snr = 0; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + atsc_status = (struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *)&rx_buf; + qam_status = (struct MXL_EAGLE_QAM_DEMOD_STATUS_T *)&rx_buf; + + switch (demod_type) { + case MXL_EAGLE_DEMOD_TYPE_ATSC: + mxl_status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_ATSC_STATUS_GET, + NULL, + 0, + rx_buf, + sizeof(struct MXL_EAGLE_ATSC_DEMOD_STATUS_T)); + if (!mxl_status) { + *snr = (u16)(atsc_status->snr_db_tenths / 10); + c->cnr.stat[0].scale = FE_SCALE_DECIBEL; + c->cnr.stat[0].svalue = *snr; + } + break; + case MXL_EAGLE_DEMOD_TYPE_QAM: + mxl_status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_QAM_STATUS_GET, + NULL, + 0, + rx_buf, + sizeof(struct MXL_EAGLE_QAM_DEMOD_STATUS_T)); + if (!mxl_status) + *snr = (u16)(qam_status->snr_db_tenths / 10); + break; + case MXL_EAGLE_DEMOD_TYPE_OOB: + default: + break; + } + + if (mxl_status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status); + return mxl_status; +} + +static int mxl692_read_ber_ucb(struct dvb_frontend *fe) +{ + struct mxl692_dev *dev = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *atsc_errors; + enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type; + int mxl_status = 0; + u32 utmp; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + atsc_errors = (struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T *)&rx_buf; + + switch (demod_type) { + case MXL_EAGLE_DEMOD_TYPE_ATSC: + mxl_status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET, + NULL, + 0, + rx_buf, + sizeof(struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T)); + if (!mxl_status) { + if (atsc_errors->error_packets == 0) + utmp = 0; + else + utmp = ((atsc_errors->error_bytes / atsc_errors->error_packets) * + atsc_errors->total_packets); + /* ber */ + c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_error.stat[0].uvalue += atsc_errors->error_bytes; + c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; + c->post_bit_count.stat[0].uvalue += utmp; + /* ucb */ + c->block_error.stat[0].scale = FE_SCALE_COUNTER; + c->block_error.stat[0].uvalue += atsc_errors->error_packets; + + dev_dbg(&dev->i2c_client->dev, "%llu %llu\n", + c->post_bit_count.stat[0].uvalue, c->block_error.stat[0].uvalue); + } + break; + case MXL_EAGLE_DEMOD_TYPE_QAM: + case MXL_EAGLE_DEMOD_TYPE_OOB: + default: + break; + } + + if (mxl_status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status); + + return mxl_status; +} + +static int mxl692_read_status(struct dvb_frontend *fe, + enum fe_status *status) +{ + struct mxl692_dev *dev = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + u8 rx_buf[MXL_EAGLE_MAX_I2C_PACKET_SIZE] = {}; + struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *atsc_status; + struct MXL_EAGLE_QAM_DEMOD_STATUS_T *qam_status; + enum MXL_EAGLE_DEMOD_TYPE_E demod_type = dev->demod_type; + int mxl_status = 0; + *status = 0; + + dev_dbg(&dev->i2c_client->dev, "\n"); + + atsc_status = (struct MXL_EAGLE_ATSC_DEMOD_STATUS_T *)&rx_buf; + qam_status = (struct MXL_EAGLE_QAM_DEMOD_STATUS_T *)&rx_buf; + + switch (demod_type) { + case MXL_EAGLE_DEMOD_TYPE_ATSC: + mxl_status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_ATSC_STATUS_GET, + NULL, + 0, + rx_buf, + sizeof(struct MXL_EAGLE_ATSC_DEMOD_STATUS_T)); + if (!mxl_status && atsc_status->atsc_lock) { + *status |= FE_HAS_SIGNAL; + *status |= FE_HAS_CARRIER; + *status |= FE_HAS_VITERBI; + *status |= FE_HAS_SYNC; + *status |= FE_HAS_LOCK; + + c->cnr.stat[0].scale = FE_SCALE_DECIBEL; + c->cnr.stat[0].svalue = atsc_status->snr_db_tenths / 10; + } + break; + case MXL_EAGLE_DEMOD_TYPE_QAM: + mxl_status = mxl692_i2c_writeread(dev, + MXL_EAGLE_OPCODE_QAM_STATUS_GET, + NULL, + 0, + rx_buf, + sizeof(struct MXL_EAGLE_QAM_DEMOD_STATUS_T)); + if (!mxl_status && qam_status->qam_locked) { + *status |= FE_HAS_SIGNAL; + *status |= FE_HAS_CARRIER; + *status |= FE_HAS_VITERBI; + *status |= FE_HAS_SYNC; + *status |= FE_HAS_LOCK; + + c->cnr.stat[0].scale = FE_SCALE_DECIBEL; + c->cnr.stat[0].svalue = qam_status->snr_db_tenths / 10; + } + break; + case MXL_EAGLE_DEMOD_TYPE_OOB: + default: + break; + } + + if ((*status & FE_HAS_LOCK) == 0) { + /* No lock, reset all statistics */ + c->cnr.len = 1; + c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + return 0; + } + + if (mxl_status) + dev_dbg(&dev->i2c_client->dev, "err %d\n", mxl_status); + else + mxl_status = mxl692_read_ber_ucb(fe); + + return mxl_status; +} + +static const struct dvb_frontend_ops mxl692_ops = { + .delsys = { SYS_ATSC }, + .info = { + .name = "MaxLinear MxL692 VSB tuner-demodulator", + .frequency_min_hz = 54000000, + .frequency_max_hz = 858000000, + .frequency_stepsize_hz = 62500, + .caps = FE_CAN_8VSB + }, + + .init = mxl692_init, + .sleep = mxl692_sleep, + .set_frontend = mxl692_set_frontend, + .get_frontend = mxl692_get_frontend, + + .read_status = mxl692_read_status, + .read_snr = mxl692_read_snr, +}; + +static int mxl692_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct mxl692_config *config = client->dev.platform_data; + struct mxl692_dev *dev; + int ret = 0; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + ret = -ENOMEM; + dev_dbg(&client->dev, "kzalloc() failed\n"); + goto err; + } + + memcpy(&dev->fe.ops, &mxl692_ops, sizeof(struct dvb_frontend_ops)); + dev->fe.demodulator_priv = dev; + dev->i2c_client = client; + *config->fe = &dev->fe; + mutex_init(&dev->i2c_lock); + i2c_set_clientdata(client, dev); + + dev_info(&client->dev, "MaxLinear mxl692 successfully attached\n"); + + return 0; +err: + dev_dbg(&client->dev, "failed %d\n", ret); + return -ENODEV; +} + +static int mxl692_remove(struct i2c_client *client) +{ + struct mxl692_dev *dev = i2c_get_clientdata(client); + + dev->fe.demodulator_priv = NULL; + i2c_set_clientdata(client, NULL); + kfree(dev); + + return 0; +} + +static const struct i2c_device_id mxl692_id_table[] = { + {"mxl692", 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, mxl692_id_table); + +static struct i2c_driver mxl692_driver = { + .driver = { + .name = "mxl692", + }, + .probe = mxl692_probe, + .remove = mxl692_remove, + .id_table = mxl692_id_table, +}; + +module_i2c_driver(mxl692_driver); + +MODULE_AUTHOR("Brad Love <brad@nextdimension.cc>"); +MODULE_DESCRIPTION("MaxLinear MxL692 demodulator/tuner driver"); +MODULE_FIRMWARE(MXL692_FIRMWARE); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/mxl692.h b/drivers/media/dvb-frontends/mxl692.h new file mode 100644 index 000000000000..45bc48f1f12f --- /dev/null +++ b/drivers/media/dvb-frontends/mxl692.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Driver for the MaxLinear MxL69x family of tuners/demods + * + * Copyright (C) 2020 Brad Love <brad@nextdimension.cc> + * + * based on code: + * Copyright (c) 2016 MaxLinear, Inc. All rights reserved + * which was released under GPL V2 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MXL692_H_ +#define _MXL692_H_ + +#include <media/dvb_frontend.h> + +#define MXL692_FIRMWARE "dvb-demod-mxl692.fw" + +struct mxl692_config { + unsigned char id; + u8 i2c_addr; + /* + * frontend + * returned by driver + */ + struct dvb_frontend **fe; +}; + +#endif /* _MXL692_H_ */ diff --git a/drivers/media/dvb-frontends/mxl692_defs.h b/drivers/media/dvb-frontends/mxl692_defs.h new file mode 100644 index 000000000000..776ac407b4e7 --- /dev/null +++ b/drivers/media/dvb-frontends/mxl692_defs.h @@ -0,0 +1,548 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Driver for the MaxLinear MxL69x family of combo tuners/demods + * + * Copyright (C) 2020 Brad Love <brad@nextdimension.cc> + * + * based on code: + * Copyright (c) 2016 MaxLinear, Inc. All rights reserved + * which was released under GPL V2 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/***************************************************************************** + * Defines + ***************************************************************************** + */ +#define MXL_EAGLE_HOST_MSG_HEADER_SIZE 8 +#define MXL_EAGLE_FW_MAX_SIZE_IN_KB 76 +#define MXL_EAGLE_QAM_FFE_TAPS_LENGTH 16 +#define MXL_EAGLE_QAM_SPUR_TAPS_LENGTH 32 +#define MXL_EAGLE_QAM_DFE_TAPS_LENGTH 72 +#define MXL_EAGLE_ATSC_FFE_TAPS_LENGTH 4096 +#define MXL_EAGLE_ATSC_DFE_TAPS_LENGTH 384 +#define MXL_EAGLE_VERSION_SIZE 5 /* A.B.C.D-RCx */ +#define MXL_EAGLE_FW_LOAD_TIME 50 + +#define MXL_EAGLE_FW_MAX_SIZE_IN_KB 76 +#define MXL_EAGLE_FW_HEADER_SIZE 16 +#define MXL_EAGLE_FW_SEGMENT_HEADER_SIZE 8 +#define MXL_EAGLE_MAX_I2C_PACKET_SIZE 58 +#define MXL_EAGLE_I2C_MHEADER_SIZE 6 +#define MXL_EAGLE_I2C_PHEADER_SIZE 2 + +/* Enum of Eagle family devices */ +enum MXL_EAGLE_DEVICE_E { + MXL_EAGLE_DEVICE_691 = 1, /* Device Mxl691 */ + MXL_EAGLE_DEVICE_248 = 2, /* Device Mxl248 */ + MXL_EAGLE_DEVICE_692 = 3, /* Device Mxl692 */ + MXL_EAGLE_DEVICE_MAX, /* No such device */ +}; + +#define VER_A 1 +#define VER_B 1 +#define VER_C 1 +#define VER_D 3 +#define VER_E 6 + +/* Enum of Host to Eagle I2C protocol opcodes */ +enum MXL_EAGLE_OPCODE_E { + /* DEVICE */ + MXL_EAGLE_OPCODE_DEVICE_DEMODULATOR_TYPE_SET, + MXL_EAGLE_OPCODE_DEVICE_MPEG_OUT_PARAMS_SET, + MXL_EAGLE_OPCODE_DEVICE_POWERMODE_SET, + MXL_EAGLE_OPCODE_DEVICE_GPIO_DIRECTION_SET, + MXL_EAGLE_OPCODE_DEVICE_GPO_LEVEL_SET, + MXL_EAGLE_OPCODE_DEVICE_INTR_MASK_SET, + MXL_EAGLE_OPCODE_DEVICE_IO_MUX_SET, + MXL_EAGLE_OPCODE_DEVICE_VERSION_GET, + MXL_EAGLE_OPCODE_DEVICE_STATUS_GET, + MXL_EAGLE_OPCODE_DEVICE_GPI_LEVEL_GET, + + /* TUNER */ + MXL_EAGLE_OPCODE_TUNER_CHANNEL_TUNE_SET, + MXL_EAGLE_OPCODE_TUNER_LOCK_STATUS_GET, + MXL_EAGLE_OPCODE_TUNER_AGC_STATUS_GET, + + /* ATSC */ + MXL_EAGLE_OPCODE_ATSC_INIT_SET, + MXL_EAGLE_OPCODE_ATSC_ACQUIRE_CARRIER_SET, + MXL_EAGLE_OPCODE_ATSC_STATUS_GET, + MXL_EAGLE_OPCODE_ATSC_ERROR_COUNTERS_GET, + MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_DFE_TAPS_GET, + MXL_EAGLE_OPCODE_ATSC_EQUALIZER_FILTER_FFE_TAPS_GET, + + /* QAM */ + MXL_EAGLE_OPCODE_QAM_PARAMS_SET, + MXL_EAGLE_OPCODE_QAM_RESTART_SET, + MXL_EAGLE_OPCODE_QAM_STATUS_GET, + MXL_EAGLE_OPCODE_QAM_ERROR_COUNTERS_GET, + MXL_EAGLE_OPCODE_QAM_CONSTELLATION_VALUE_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_FFE_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_START_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_SPUR_END_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_TAPS_NUMBER_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_START_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET, + MXL_EAGLE_OPCODE_QAM_EQUALIZER_FILTER_DFE_END_GET, + + /* OOB */ + MXL_EAGLE_OPCODE_OOB_PARAMS_SET, + MXL_EAGLE_OPCODE_OOB_RESTART_SET, + MXL_EAGLE_OPCODE_OOB_ERROR_COUNTERS_GET, + MXL_EAGLE_OPCODE_OOB_STATUS_GET, + + /* SMA */ + MXL_EAGLE_OPCODE_SMA_INIT_SET, + MXL_EAGLE_OPCODE_SMA_PARAMS_SET, + MXL_EAGLE_OPCODE_SMA_TRANSMIT_SET, + MXL_EAGLE_OPCODE_SMA_RECEIVE_GET, + + /* DEBUG */ + MXL_EAGLE_OPCODE_INTERNAL, + + MXL_EAGLE_OPCODE_MAX = 70, +}; + +/* Enum of Host to Eagle I2C protocol opcodes */ +static const char * const MXL_EAGLE_OPCODE_STRING[] = { + /* DEVICE */ + "DEVICE_DEMODULATOR_TYPE_SET", + "DEVICE_MPEG_OUT_PARAMS_SET", + "DEVICE_POWERMODE_SET", + "DEVICE_GPIO_DIRECTION_SET", + "DEVICE_GPO_LEVEL_SET", + "DEVICE_INTR_MASK_SET", + "DEVICE_IO_MUX_SET", + "DEVICE_VERSION_GET", + "DEVICE_STATUS_GET", + "DEVICE_GPI_LEVEL_GET", + + /* TUNER */ + "TUNER_CHANNEL_TUNE_SET", + "TUNER_LOCK_STATUS_GET", + "TUNER_AGC_STATUS_GET", + + /* ATSC */ + "ATSC_INIT_SET", + "ATSC_ACQUIRE_CARRIER_SET", + "ATSC_STATUS_GET", + "ATSC_ERROR_COUNTERS_GET", + "ATSC_EQUALIZER_FILTER_DFE_TAPS_GET", + "ATSC_EQUALIZER_FILTER_FFE_TAPS_GET", + + /* QAM */ + "QAM_PARAMS_SET", + "QAM_RESTART_SET", + "QAM_STATUS_GET", + "QAM_ERROR_COUNTERS_GET", + "QAM_CONSTELLATION_VALUE_GET", + "QAM_EQUALIZER_FILTER_FFE_GET", + "QAM_EQUALIZER_FILTER_SPUR_START_GET", + "QAM_EQUALIZER_FILTER_SPUR_END_GET", + "QAM_EQUALIZER_FILTER_DFE_TAPS_NUMBER_GET", + "QAM_EQUALIZER_FILTER_DFE_START_GET", + "QAM_EQUALIZER_FILTER_DFE_MIDDLE_GET", + "QAM_EQUALIZER_FILTER_DFE_END_GET", + + /* OOB */ + "OOB_PARAMS_SET", + "OOB_RESTART_SET", + "OOB_ERROR_COUNTERS_GET", + "OOB_STATUS_GET", + + /* SMA */ + "SMA_INIT_SET", + "SMA_PARAMS_SET", + "SMA_TRANSMIT_SET", + "SMA_RECEIVE_GET", + + /* DEBUG */ + "INTERNAL", +}; + +/* Enum of Callabck function types */ +enum MXL_EAGLE_CB_TYPE_E { + MXL_EAGLE_CB_FW_DOWNLOAD = 0, +}; + +/* Enum of power supply types */ +enum MXL_EAGLE_POWER_SUPPLY_SOURCE_E { + MXL_EAGLE_POWER_SUPPLY_SOURCE_SINGLE, /* Single supply of 3.3V */ + MXL_EAGLE_POWER_SUPPLY_SOURCE_DUAL, /* Dual supply, 1.8V & 3.3V */ +}; + +/* Enum of I/O pad drive modes */ +enum MXL_EAGLE_IO_MUX_DRIVE_MODE_E { + MXL_EAGLE_IO_MUX_DRIVE_MODE_1X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_2X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_3X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_4X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_5X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_6X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_7X, + MXL_EAGLE_IO_MUX_DRIVE_MODE_8X, +}; + +/* Enum of demodulator types. Used for selection of demodulator + * type in relevant devices, e.g. ATSC vs. QAM in Mxl691 + */ +enum MXL_EAGLE_DEMOD_TYPE_E { + MXL_EAGLE_DEMOD_TYPE_QAM, /* Mxl248 or Mxl692 */ + MXL_EAGLE_DEMOD_TYPE_OOB, /* Mxl248 only */ + MXL_EAGLE_DEMOD_TYPE_ATSC /* Mxl691 or Mxl692 */ +}; + +/* Enum of power modes. Used for initial + * activation, or for activating sleep mode + */ +enum MXL_EAGLE_POWER_MODE_E { + MXL_EAGLE_POWER_MODE_SLEEP, + MXL_EAGLE_POWER_MODE_ACTIVE +}; + +/* Enum of GPIOs, used in device GPIO APIs */ +enum MXL_EAGLE_GPIO_NUMBER_E { + MXL_EAGLE_GPIO_NUMBER_0, + MXL_EAGLE_GPIO_NUMBER_1, + MXL_EAGLE_GPIO_NUMBER_2, + MXL_EAGLE_GPIO_NUMBER_3, + MXL_EAGLE_GPIO_NUMBER_4, + MXL_EAGLE_GPIO_NUMBER_5, + MXL_EAGLE_GPIO_NUMBER_6 +}; + +/* Enum of GPIO directions, used in GPIO direction configuration API */ +enum MXL_EAGLE_GPIO_DIRECTION_E { + MXL_EAGLE_GPIO_DIRECTION_INPUT, + MXL_EAGLE_GPIO_DIRECTION_OUTPUT +}; + +/* Enum of GPIO level, used in device GPIO APIs */ +enum MXL_EAGLE_GPIO_LEVEL_E { + MXL_EAGLE_GPIO_LEVEL_LOW, + MXL_EAGLE_GPIO_LEVEL_HIGH, +}; + +/* Enum of I/O Mux function, used in device I/O mux configuration API */ +enum MXL_EAGLE_IOMUX_FUNCTION_E { + MXL_EAGLE_IOMUX_FUNC_FEC_LOCK, + MXL_EAGLE_IOMUX_FUNC_MERR, +}; + +/* Enum of MPEG Data format, used in MPEG and OOB output configuration */ +enum MXL_EAGLE_MPEG_DATA_FORMAT_E { + MXL_EAGLE_DATA_SERIAL_LSB_1ST = 0, + MXL_EAGLE_DATA_SERIAL_MSB_1ST, + + MXL_EAGLE_DATA_SYNC_WIDTH_BIT = 0, + MXL_EAGLE_DATA_SYNC_WIDTH_BYTE +}; + +/* Enum of MPEG Clock format, used in MPEG and OOB output configuration */ +enum MXL_EAGLE_MPEG_CLOCK_FORMAT_E { + MXL_EAGLE_CLOCK_ACTIVE_HIGH = 0, + MXL_EAGLE_CLOCK_ACTIVE_LOW, + + MXL_EAGLE_CLOCK_POSITIVE = 0, + MXL_EAGLE_CLOCK_NEGATIVE, + + MXL_EAGLE_CLOCK_IN_PHASE = 0, + MXL_EAGLE_CLOCK_INVERTED, +}; + +/* Enum of MPEG Clock speeds, used in MPEG output configuration */ +enum MXL_EAGLE_MPEG_CLOCK_RATE_E { + MXL_EAGLE_MPEG_CLOCK_54MHZ, + MXL_EAGLE_MPEG_CLOCK_40_5MHZ, + MXL_EAGLE_MPEG_CLOCK_27MHZ, + MXL_EAGLE_MPEG_CLOCK_13_5MHZ, +}; + +/* Enum of Interrupt mask bit, used in host interrupt configuration */ +enum MXL_EAGLE_INTR_MASK_BITS_E { + MXL_EAGLE_INTR_MASK_DEMOD = 0, + MXL_EAGLE_INTR_MASK_SMA_RX = 1, + MXL_EAGLE_INTR_MASK_WDOG = 31 +}; + +/* Enum of QAM Demodulator type, used in QAM configuration */ +enum MXL_EAGLE_QAM_DEMOD_ANNEX_TYPE_E { + MXL_EAGLE_QAM_DEMOD_ANNEX_B, /* J.83B */ + MXL_EAGLE_QAM_DEMOD_ANNEX_A, /* DVB-C */ +}; + +/* Enum of QAM Demodulator modulation, used in QAM configuration and status */ +enum MXL_EAGLE_QAM_DEMOD_QAM_TYPE_E { + MXL_EAGLE_QAM_DEMOD_QAM16, + MXL_EAGLE_QAM_DEMOD_QAM64, + MXL_EAGLE_QAM_DEMOD_QAM256, + MXL_EAGLE_QAM_DEMOD_QAM1024, + MXL_EAGLE_QAM_DEMOD_QAM32, + MXL_EAGLE_QAM_DEMOD_QAM128, + MXL_EAGLE_QAM_DEMOD_QPSK, + MXL_EAGLE_QAM_DEMOD_AUTO, +}; + +/* Enum of Demodulator IQ setup, used in QAM, OOB configuration and status */ +enum MXL_EAGLE_IQ_FLIP_E { + MXL_EAGLE_DEMOD_IQ_NORMAL, + MXL_EAGLE_DEMOD_IQ_FLIPPED, + MXL_EAGLE_DEMOD_IQ_AUTO, +}; + +/* Enum of OOB Demodulator symbol rates, used in OOB configuration */ +enum MXL_EAGLE_OOB_DEMOD_SYMB_RATE_E { + MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */ + MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */ + MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */ +}; + +/* Enum of tuner channel tuning mode */ +enum MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_E { + MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_VIEW, /* Normal "view" mode */ + MXL_EAGLE_TUNER_CHANNEL_TUNE_MODE_SCAN, /* Fast "scan" mode */ +}; + +/* Enum of tuner bandwidth */ +enum MXL_EAGLE_TUNER_BW_E { + MXL_EAGLE_TUNER_BW_6MHZ, + MXL_EAGLE_TUNER_BW_7MHZ, + MXL_EAGLE_TUNER_BW_8MHZ, +}; + +/* Enum of tuner bandwidth */ +enum MXL_EAGLE_JUNCTION_TEMPERATURE_E { + MXL_EAGLE_JUNCTION_TEMPERATURE_BELOW_0_CELSIUS = 0, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_0_TO_14_CELSIUS = 1, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_14_TO_28_CELSIUS = 3, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_28_TO_42_CELSIUS = 2, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_42_TO_57_CELSIUS = 6, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_57_TO_71_CELSIUS = 7, + MXL_EAGLE_JUNCTION_TEMPERATURE_BETWEEN_71_TO_85_CELSIUS = 5, + MXL_EAGLE_JUNCTION_TEMPERATURE_ABOVE_85_CELSIUS = 4, +}; + +/* Struct passed in optional callback used during FW download */ +struct MXL_EAGLE_FW_DOWNLOAD_CB_PAYLOAD_T { + u32 total_len; + u32 downloaded_len; +}; + +/* Struct used of I2C protocol between host and Eagle, internal use only */ +struct __packed MXL_EAGLE_HOST_MSG_HEADER_T { + u8 opcode; + u8 seqnum; + u8 payload_size; + u8 status; + u32 checksum; +}; + +/* Device version information struct */ +struct __packed MXL_EAGLE_DEV_VER_T { + u8 chip_id; + u8 firmware_ver[MXL_EAGLE_VERSION_SIZE]; + u8 mxlware_ver[MXL_EAGLE_VERSION_SIZE]; +}; + +/* Xtal configuration struct */ +struct __packed MXL_EAGLE_DEV_XTAL_T { + u8 xtal_cap; /* accepted range is 1..31 pF. Default is 26 */ + u8 clk_out_enable; + u8 clk_out_div_enable; /* clock out freq is xtal freq / 6 */ + u8 xtal_sharing_enable; /* if enabled set xtal_cap to 25 pF */ + u8 xtal_calibration_enable; /* enable for master, disable for slave */ +}; + +/* GPIO direction struct, internally used in GPIO configuration API */ +struct __packed MXL_EAGLE_DEV_GPIO_DIRECTION_T { + u8 gpio_number; + u8 gpio_direction; +}; + +/* GPO level struct, internally used in GPIO configuration API */ +struct __packed MXL_EAGLE_DEV_GPO_LEVEL_T { + u8 gpio_number; + u8 gpo_level; +}; + +/* Device Status struct */ +struct MXL_EAGLE_DEV_STATUS_T { + u8 temperature; + u8 demod_type; + u8 power_mode; + u8 cpu_utilization_percent; +}; + +/* Device interrupt configuration struct */ +struct __packed MXL_EAGLE_DEV_INTR_CFG_T { + u32 intr_mask; + u8 edge_trigger; + u8 positive_trigger; + u8 global_enable_interrupt; +}; + +/* MPEG pad drive parameters, used on MPEG output configuration */ +/* See MXL_EAGLE_IO_MUX_DRIVE_MODE_E */ +struct MXL_EAGLE_MPEG_PAD_DRIVE_T { + u8 pad_drv_mpeg_syn; + u8 pad_drv_mpeg_dat; + u8 pad_drv_mpeg_val; + u8 pad_drv_mpeg_clk; +}; + +/* MPEGOUT parameter struct, used in MPEG output configuration */ +struct MXL_EAGLE_MPEGOUT_PARAMS_T { + u8 mpeg_parallel; + u8 msb_first; + u8 mpeg_sync_pulse_width; /* See MXL_EAGLE_MPEG_DATA_FORMAT_E */ + u8 mpeg_valid_pol; + u8 mpeg_sync_pol; + u8 mpeg_clk_pol; + u8 mpeg3wire_mode_enable; + u8 mpeg_clk_freq; + struct MXL_EAGLE_MPEG_PAD_DRIVE_T mpeg_pad_drv; +}; + +/* QAM Demodulator parameters struct, used in QAM params configuration */ +struct __packed MXL_EAGLE_QAM_DEMOD_PARAMS_T { + u8 annex_type; + u8 qam_type; + u8 iq_flip; + u8 search_range_idx; + u8 spur_canceller_enable; + u32 symbol_rate_hz; + u32 symbol_rate_256qam_hz; +}; + +/* QAM Demodulator status */ +struct MXL_EAGLE_QAM_DEMOD_STATUS_T { + u8 annex_type; + u8 qam_type; + u8 iq_flip; + u8 interleaver_depth_i; + u8 interleaver_depth_j; + u8 qam_locked; + u8 fec_locked; + u8 mpeg_locked; + u16 snr_db_tenths; + s16 timing_offset; + s32 carrier_offset_hz; +}; + +/* QAM Demodulator error counters */ +struct MXL_EAGLE_QAM_DEMOD_ERROR_COUNTERS_T { + u32 corrected_code_words; + u32 uncorrected_code_words; + u32 total_code_words_received; + u32 corrected_bits; + u32 error_mpeg_frames; + u32 mpeg_frames_received; + u32 erasures; +}; + +/* QAM Demodulator constellation point */ +struct MXL_EAGLE_QAM_DEMOD_CONSTELLATION_VAL_T { + s16 i_value[12]; + s16 q_value[12]; +}; + +/* QAM Demodulator equalizer filter taps */ +struct MXL_EAGLE_QAM_DEMOD_EQU_FILTER_T { + s16 ffe_taps[MXL_EAGLE_QAM_FFE_TAPS_LENGTH]; + s16 spur_taps[MXL_EAGLE_QAM_SPUR_TAPS_LENGTH]; + s16 dfe_taps[MXL_EAGLE_QAM_DFE_TAPS_LENGTH]; + u8 ffe_leading_tap_index; + u8 dfe_taps_number; +}; + +/* OOB Demodulator parameters struct, used in OOB params configuration */ +struct __packed MXL_EAGLE_OOB_DEMOD_PARAMS_T { + u8 symbol_rate; + u8 iq_flip; + u8 clk_pol; +}; + +/* OOB Demodulator error counters */ +struct MXL_EAGLE_OOB_DEMOD_ERROR_COUNTERS_T { + u32 corrected_packets; + u32 uncorrected_packets; + u32 total_packets_received; +}; + +/* OOB status */ +struct __packed MXL_EAGLE_OOB_DEMOD_STATUS_T { + u16 snr_db_tenths; + s16 timing_offset; + s32 carrier_offsetHz; + u8 qam_locked; + u8 fec_locked; + u8 mpeg_locked; + u8 retune_required; + u8 iq_flip; +}; + +/* ATSC Demodulator status */ +struct __packed MXL_EAGLE_ATSC_DEMOD_STATUS_T { + s16 snr_db_tenths; + s16 timing_offset; + s32 carrier_offset_hz; + u8 frame_lock; + u8 atsc_lock; + u8 fec_lock; +}; + +/* ATSC Demodulator error counters */ +struct MXL_EAGLE_ATSC_DEMOD_ERROR_COUNTERS_T { + u32 error_packets; + u32 total_packets; + u32 error_bytes; +}; + +/* ATSC Demodulator equalizers filter taps */ +struct __packed MXL_EAGLE_ATSC_DEMOD_EQU_FILTER_T { + s16 ffe_taps[MXL_EAGLE_ATSC_FFE_TAPS_LENGTH]; + s8 dfe_taps[MXL_EAGLE_ATSC_DFE_TAPS_LENGTH]; +}; + +/* Tuner AGC Status */ +struct __packed MXL_EAGLE_TUNER_AGC_STATUS_T { + u8 locked; + u16 raw_agc_gain; /* AGC gain [dB] = rawAgcGain / 2^6 */ + s16 rx_power_db_hundredths; +}; + +/* Tuner channel tune parameters */ +struct __packed MXL_EAGLE_TUNER_CHANNEL_PARAMS_T { + u32 freq_hz; + u8 tune_mode; + u8 bandwidth; +}; + +/* Tuner channel lock indications */ +struct __packed MXL_EAGLE_TUNER_LOCK_STATUS_T { + u8 rf_pll_locked; + u8 ref_pll_locked; +}; + +/* Smart antenna parameters used in Smart antenna params configuration */ +struct __packed MXL_EAGLE_SMA_PARAMS_T { + u8 full_duplex_enable; + u8 rx_disable; + u8 idle_logic_high; +}; + +/* Smart antenna message format */ +struct __packed MXL_EAGLE_SMA_MESSAGE_T { + u32 payload_bits; + u8 total_num_bits; +}; + diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index 01dcc7f1b9b2..dcbeb9f5e12a 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -698,6 +698,7 @@ static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status) goto err; constellation = (u8tmp >> 2) & 0x03; /* [3:2] */ + ret = -EINVAL; if (constellation > CONSTELLATION_NUM - 1) goto err; diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 2b9d81e4794a..462c0e059754 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -813,6 +813,20 @@ config VIDEO_IMX319 To compile this driver as a module, choose M here: the module will be called imx319. +config VIDEO_IMX334 + tristate "Sony IMX334 sensor support" + depends on OF_GPIO + depends on I2C && VIDEO_V4L2 + select VIDEO_V4L2_SUBDEV_API + select MEDIA_CONTROLLER + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the Sony + IMX334 camera. + + To compile this driver as a module, choose M here: the + module will be called imx334. + config VIDEO_IMX355 tristate "Sony IMX355 sensor support" depends on I2C && VIDEO_V4L2 @@ -936,6 +950,19 @@ config VIDEO_OV5647 To compile this driver as a module, choose M here: the module will be called ov5647. +config VIDEO_OV5648 + tristate "OmniVision OV5648 sensor support" + depends on I2C && PM && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for the OmniVision + OV5648 camera. + + To compile this driver as a module, choose M here: the + module will be called ov5648. + config VIDEO_OV6650 tristate "OmniVision OV6650 sensor support" depends on I2C && VIDEO_V4L2 @@ -1000,6 +1027,7 @@ config VIDEO_OV772X tristate "OmniVision OV772x sensor support" depends on I2C && VIDEO_V4L2 select REGMAP_SCCB + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the OmniVision OV772x camera. @@ -1047,6 +1075,19 @@ config VIDEO_OV8856 To compile this driver as a module, choose M here: the module will be called ov8856. +config VIDEO_OV8865 + tristate "OmniVision OV8865 sensor support" + depends on I2C && PM && VIDEO_V4L2 + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + This is a Video4Linux2 sensor driver for OmniVision + OV8865 camera sensor. + + To compile this driver as a module, choose M here: the + module will be called ov8865. + config VIDEO_OV9640 tristate "OmniVision OV9640 sensor support" depends on I2C && VIDEO_V4L2 @@ -1199,12 +1240,16 @@ config VIDEO_NOON010PC30 source "drivers/media/i2c/m5mols/Kconfig" +config VIDEO_MAX9271_LIB + tristate + config VIDEO_RDACM20 tristate "IMI RDACM20 camera support" depends on I2C select V4L2_FWNODE select VIDEO_V4L2_SUBDEV_API select MEDIA_CONTROLLER + select VIDEO_MAX9271_LIB help This driver supports the IMI RDACM20 GMSL camera, used in ADAS systems. @@ -1212,6 +1257,20 @@ config VIDEO_RDACM20 This camera should be used in conjunction with a GMSL deserialiser such as the MAX9286. +config VIDEO_RDACM21 + tristate "IMI RDACM21 camera support" + depends on I2C + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + select MEDIA_CONTROLLER + select VIDEO_MAX9271_LIB + help + This driver supports the IMI RDACM21 GMSL camera, used in + ADAS systems. + + This camera should be used in conjunction with a GMSL + deserialiser such as the MAX9286. + config VIDEO_RJ54N1 tristate "Sharp RJ54N1CB0C sensor support" depends on I2C && VIDEO_V4L2 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index a3149dce21bb..0c067beca066 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -72,6 +72,7 @@ obj-$(CONFIG_VIDEO_OV2740) += ov2740.o obj-$(CONFIG_VIDEO_OV5640) += ov5640.o obj-$(CONFIG_VIDEO_OV5645) += ov5645.o obj-$(CONFIG_VIDEO_OV5647) += ov5647.o +obj-$(CONFIG_VIDEO_OV5648) += ov5648.o obj-$(CONFIG_VIDEO_OV5670) += ov5670.o obj-$(CONFIG_VIDEO_OV5675) += ov5675.o obj-$(CONFIG_VIDEO_OV5695) += ov5695.o @@ -82,6 +83,7 @@ obj-$(CONFIG_VIDEO_OV7670) += ov7670.o obj-$(CONFIG_VIDEO_OV772X) += ov772x.o obj-$(CONFIG_VIDEO_OV7740) += ov7740.o obj-$(CONFIG_VIDEO_OV8856) += ov8856.o +obj-$(CONFIG_VIDEO_OV8865) += ov8865.o obj-$(CONFIG_VIDEO_OV9640) += ov9640.o obj-$(CONFIG_VIDEO_OV9650) += ov9650.o obj-$(CONFIG_VIDEO_OV9734) += ov9734.o @@ -120,10 +122,12 @@ obj-$(CONFIG_VIDEO_IMX258) += imx258.o obj-$(CONFIG_VIDEO_IMX274) += imx274.o obj-$(CONFIG_VIDEO_IMX290) += imx290.o obj-$(CONFIG_VIDEO_IMX319) += imx319.o +obj-$(CONFIG_VIDEO_IMX334) += imx334.o obj-$(CONFIG_VIDEO_IMX355) += imx355.o obj-$(CONFIG_VIDEO_MAX9286) += max9286.o -rdacm20-camera_module-objs := rdacm20.o max9271.o -obj-$(CONFIG_VIDEO_RDACM20) += rdacm20-camera_module.o +obj-$(CONFIG_VIDEO_MAX9271_LIB) += max9271.o +obj-$(CONFIG_VIDEO_RDACM20) += rdacm20.o +obj-$(CONFIG_VIDEO_RDACM21) += rdacm21.o obj-$(CONFIG_VIDEO_ST_MIPID02) += st-mipid02.o obj-$(CONFIG_SDR_MAX2175) += max2175.o diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 58ca47e904a1..fcc39360cc50 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -17,20 +17,20 @@ #include "ccs-pll.h" /* Return an even number or one. */ -static inline uint32_t clk_div_even(uint32_t a) +static inline u32 clk_div_even(u32 a) { - return max_t(uint32_t, 1, a & ~1); + return max_t(u32, 1, a & ~1); } /* Return an even number or one. */ -static inline uint32_t clk_div_even_up(uint32_t a) +static inline u32 clk_div_even_up(u32 a) { if (a == 1) return 1; return (a + 1) & ~1; } -static inline uint32_t is_one_or_even(uint32_t a) +static inline u32 is_one_or_even(u32 a) { if (a == 1) return 1; @@ -40,13 +40,13 @@ static inline uint32_t is_one_or_even(uint32_t a) return 1; } -static inline uint32_t one_or_more(uint32_t a) +static inline u32 one_or_more(u32 a) { return a ?: 1; } -static int bounds_check(struct device *dev, uint32_t val, - uint32_t min, uint32_t max, const char *prefix, +static int bounds_check(struct device *dev, u32 val, + u32 min, u32 max, const char *prefix, char *str) { if (val >= min && val <= max) @@ -138,12 +138,12 @@ static void print_pll(struct device *dev, struct ccs_pll *pll) pll->flags & PLL_FL(OP_PIX_DDR) ? " op-pix-ddr" : ""); } -static uint32_t op_sys_ddr(uint32_t flags) +static u32 op_sys_ddr(u32 flags) { return flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0; } -static uint32_t op_pix_ddr(uint32_t flags) +static u32 op_pix_ddr(u32 flags) { return flags & CCS_PLL_FLAG_OP_PIX_DDR ? 1 : 0; } @@ -250,8 +250,8 @@ static int check_ext_bounds(struct device *dev, struct ccs_pll *pll) static void ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, - uint16_t min_vt_div, uint16_t max_vt_div, - uint16_t *min_sys_div, uint16_t *max_sys_div) + u16 min_vt_div, u16 max_vt_div, + u16 *min_sys_div, u16 *max_sys_div) { /* * Find limits for sys_clk_div. Not all values are possible with all @@ -259,11 +259,11 @@ ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, */ *min_sys_div = lim->vt_bk.min_sys_clk_div; dev_dbg(dev, "min_sys_div: %u\n", *min_sys_div); - *min_sys_div = max_t(uint16_t, *min_sys_div, + *min_sys_div = max_t(u16, *min_sys_div, DIV_ROUND_UP(min_vt_div, lim->vt_bk.max_pix_clk_div)); dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", *min_sys_div); - *min_sys_div = max_t(uint16_t, *min_sys_div, + *min_sys_div = max_t(u16, *min_sys_div, pll_fr->pll_op_clk_freq_hz / lim->vt_bk.max_sys_clk_freq_hz); dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", *min_sys_div); @@ -272,11 +272,11 @@ ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, *max_sys_div = lim->vt_bk.max_sys_clk_div; dev_dbg(dev, "max_sys_div: %u\n", *max_sys_div); - *max_sys_div = min_t(uint16_t, *max_sys_div, + *max_sys_div = min_t(u16, *max_sys_div, DIV_ROUND_UP(max_vt_div, lim->vt_bk.min_pix_clk_div)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", *max_sys_div); - *max_sys_div = min_t(uint16_t, *max_sys_div, + *max_sys_div = min_t(u16, *max_sys_div, DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", *max_sys_div); @@ -289,15 +289,15 @@ ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim, static inline int __ccs_pll_calculate_vt_tree(struct device *dev, const struct ccs_pll_limits *lim, - struct ccs_pll *pll, uint32_t mul, uint32_t div) + struct ccs_pll *pll, u32 mul, u32 div) { const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; const struct ccs_pll_branch_limits_bk *lim_bk = &lim->vt_bk; struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; struct ccs_pll_branch_bk *pll_bk = &pll->vt_bk; - uint32_t more_mul; - uint16_t best_pix_div = SHRT_MAX >> 1, best_div; - uint16_t vt_div, min_sys_div, max_sys_div, sys_div; + u32 more_mul; + u16 best_pix_div = SHRT_MAX >> 1, best_div; + u16 vt_div, min_sys_div, max_sys_div, sys_div; pll_fr->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz / pll_fr->pre_pll_clk_div; @@ -331,7 +331,7 @@ __ccs_pll_calculate_vt_tree(struct device *dev, for (sys_div = min_sys_div; sys_div <= max_sys_div; sys_div += 2 - (sys_div & 1)) { - uint16_t pix_div; + u16 pix_div; if (vt_div % sys_div) continue; @@ -379,9 +379,9 @@ static int ccs_pll_calculate_vt_tree(struct device *dev, { const struct ccs_pll_branch_limits_fr *lim_fr = &lim->vt_fr; struct ccs_pll_branch_fr *pll_fr = &pll->vt_fr; - uint16_t min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div; - uint32_t pre_mul, pre_div; + u16 min_pre_pll_clk_div = lim_fr->min_pre_pll_clk_div; + u16 max_pre_pll_clk_div = lim_fr->max_pre_pll_clk_div; + u32 pre_mul, pre_div; pre_div = gcd(pll->pixel_rate_csi, pll->ext_clk_freq_hz * pll->vt_lanes); @@ -390,11 +390,11 @@ static int ccs_pll_calculate_vt_tree(struct device *dev, /* Make sure PLL input frequency is within limits */ max_pre_pll_clk_div = - min_t(uint16_t, max_pre_pll_clk_div, + min_t(u16, max_pre_pll_clk_div, DIV_ROUND_UP(pll->ext_clk_freq_hz, lim_fr->min_pll_ip_clk_freq_hz)); - min_pre_pll_clk_div = max_t(uint16_t, min_pre_pll_clk_div, + min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div, pll->ext_clk_freq_hz / lim_fr->max_pll_ip_clk_freq_hz); @@ -406,7 +406,7 @@ static int ccs_pll_calculate_vt_tree(struct device *dev, pll_fr->pre_pll_clk_div += (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (pll_fr->pre_pll_clk_div & 1)) { - uint32_t mul, div; + u32 mul, div; int rval; div = gcd(pre_mul * pll_fr->pre_pll_clk_div, pre_div); @@ -440,13 +440,13 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr, struct ccs_pll_branch_bk *op_pll_bk, bool cphy, - uint32_t phy_const) + u32 phy_const) { - uint16_t sys_div; - uint16_t best_pix_div = SHRT_MAX >> 1; - uint16_t vt_op_binning_div; - uint16_t min_vt_div, max_vt_div, vt_div; - uint16_t min_sys_div, max_sys_div; + u16 sys_div; + u16 best_pix_div = SHRT_MAX >> 1; + u16 vt_op_binning_div; + u16 min_vt_div, max_vt_div, vt_div; + u16 min_sys_div, max_sys_div; if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) goto out_calc_pixel_rate; @@ -500,18 +500,18 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); - min_vt_div = max_t(uint16_t, min_vt_div, + min_vt_div = max_t(u16, min_vt_div, DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.max_pix_clk_freq_hz)); dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n", min_vt_div); - min_vt_div = max_t(uint16_t, min_vt_div, lim->vt_bk.min_pix_clk_div - * lim->vt_bk.min_sys_clk_div); + min_vt_div = max_t(u16, min_vt_div, lim->vt_bk.min_pix_clk_div + * lim->vt_bk.min_sys_clk_div); dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div); max_vt_div = lim->vt_bk.max_sys_clk_div * lim->vt_bk.max_pix_clk_div; dev_dbg(dev, "max_vt_div: %u\n", max_vt_div); - max_vt_div = min_t(uint16_t, max_vt_div, + max_vt_div = min_t(u16, max_vt_div, DIV_ROUND_UP(pll_fr->pll_op_clk_freq_hz, lim->vt_bk.min_pix_clk_freq_hz)); dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n", @@ -526,12 +526,12 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim, * divisor. */ for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) { - uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div; + u16 __max_sys_div = vt_div & 1 ? 1 : max_sys_div; for (sys_div = min_sys_div; sys_div <= __max_sys_div; sys_div += 2 - (sys_div & 1)) { - uint16_t pix_div; - uint16_t rounded_div; + u16 pix_div; + u16 rounded_div; pix_div = DIV_ROUND_UP(vt_div, sys_div); @@ -588,9 +588,9 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_fr *op_lim_fr, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, - struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t op_sys_clk_freq_hz_sdr, uint32_t l, - bool cphy, uint32_t phy_const) + struct ccs_pll_branch_bk *op_pll_bk, u32 mul, + u32 div, u32 op_sys_clk_freq_hz_sdr, u32 l, + bool cphy, u32 phy_const) { /* * Higher multipliers (and divisors) are often required than @@ -598,9 +598,9 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, * There are limits for all values in the clock tree. These * are the minimum and maximum multiplier for mul. */ - uint32_t more_mul_min, more_mul_max; - uint32_t more_mul_factor; - uint32_t i; + u32 more_mul_min, more_mul_max; + u32 more_mul_factor; + u32 i; /* * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be @@ -614,7 +614,7 @@ ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim, more_mul_max); /* Don't go above max pll op frequency. */ more_mul_max = - min_t(uint32_t, + min_t(u32, more_mul_max, op_lim_fr->max_pll_op_clk_freq_hz / (pll->ext_clk_freq_hz / @@ -706,14 +706,14 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, struct ccs_pll_branch_fr *op_pll_fr; struct ccs_pll_branch_bk *op_pll_bk; bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; - uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; - uint32_t op_sys_clk_freq_hz_sdr; - uint16_t min_op_pre_pll_clk_div; - uint16_t max_op_pre_pll_clk_div; - uint32_t mul, div; - uint32_t l = (!pll->op_bits_per_lane || - pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; - uint32_t i; + u32 phy_const = cphy ? CPHY_CONST : DPHY_CONST; + u32 op_sys_clk_freq_hz_sdr; + u16 min_op_pre_pll_clk_div; + u16 max_op_pre_pll_clk_div; + u32 mul, div; + u32 l = (!pll->op_bits_per_lane || + pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2; + u32 i; int rval = -EINVAL; if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) { @@ -791,11 +791,11 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); max_op_pre_pll_clk_div = - min_t(uint16_t, op_lim_fr->max_pre_pll_clk_div, + min_t(u16, op_lim_fr->max_pre_pll_clk_div, clk_div_even(pll->ext_clk_freq_hz / op_lim_fr->min_pll_ip_clk_freq_hz)); min_op_pre_pll_clk_div = - max_t(uint16_t, op_lim_fr->min_pre_pll_clk_div, + max_t(u16, op_lim_fr->min_pre_pll_clk_div, clk_div_even_up( DIV_ROUND_UP(pll->ext_clk_freq_hz, op_lim_fr->max_pll_ip_clk_freq_hz))); @@ -809,7 +809,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, dev_dbg(dev, "mul %u / div %u\n", mul, div); min_op_pre_pll_clk_div = - max_t(uint16_t, min_op_pre_pll_clk_div, + max_t(u16, min_op_pre_pll_clk_div, clk_div_even_up( mul / one_or_more( @@ -877,4 +877,4 @@ EXPORT_SYMBOL_GPL(ccs_pll_calculate); MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>"); MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator"); -MODULE_LICENSE("GPL v2"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index b97d7ff50ea5..6eb1b1c68e1e 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -44,10 +44,10 @@ * @pll_op_clk_freq_hz: PLL output clock frequency */ struct ccs_pll_branch_fr { - uint16_t pre_pll_clk_div; - uint16_t pll_multiplier; - uint32_t pll_ip_clk_freq_hz; - uint32_t pll_op_clk_freq_hz; + u16 pre_pll_clk_div; + u16 pll_multiplier; + u32 pll_ip_clk_freq_hz; + u32 pll_op_clk_freq_hz; }; /** @@ -61,10 +61,10 @@ struct ccs_pll_branch_fr { * @pix_clk_freq_hz: Pixel clock frequency */ struct ccs_pll_branch_bk { - uint16_t sys_clk_div; - uint16_t pix_clk_div; - uint32_t sys_clk_freq_hz; - uint32_t pix_clk_freq_hz; + u16 sys_clk_div; + u16 pix_clk_div; + u32 sys_clk_freq_hz; + u32 pix_clk_freq_hz; }; /** @@ -97,21 +97,21 @@ struct ccs_pll_branch_bk { */ struct ccs_pll { /* input values */ - uint8_t bus_type; - uint8_t op_lanes; - uint8_t vt_lanes; + u8 bus_type; + u8 op_lanes; + u8 vt_lanes; struct { - uint8_t lanes; + u8 lanes; } csi2; - uint8_t binning_horizontal; - uint8_t binning_vertical; - uint8_t scale_m; - uint8_t scale_n; - uint8_t bits_per_pixel; - uint8_t op_bits_per_lane; - uint16_t flags; - uint32_t link_freq; - uint32_t ext_clk_freq_hz; + u8 binning_horizontal; + u8 binning_vertical; + u8 scale_m; + u8 scale_n; + u8 bits_per_pixel; + u8 op_bits_per_lane; + u16 flags; + u32 link_freq; + u32 ext_clk_freq_hz; /* output values */ struct ccs_pll_branch_fr vt_fr; @@ -119,8 +119,8 @@ struct ccs_pll { struct ccs_pll_branch_fr op_fr; struct ccs_pll_branch_bk op_bk; - uint32_t pixel_rate_csi; - uint32_t pixel_rate_pixel_array; + u32 pixel_rate_csi; + u32 pixel_rate_pixel_array; }; /** @@ -136,14 +136,14 @@ struct ccs_pll { * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency */ struct ccs_pll_branch_limits_fr { - uint16_t min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div; - uint32_t min_pll_ip_clk_freq_hz; - uint32_t max_pll_ip_clk_freq_hz; - uint16_t min_pll_multiplier; - uint16_t max_pll_multiplier; - uint32_t min_pll_op_clk_freq_hz; - uint32_t max_pll_op_clk_freq_hz; + u16 min_pre_pll_clk_div; + u16 max_pre_pll_clk_div; + u32 min_pll_ip_clk_freq_hz; + u32 max_pll_ip_clk_freq_hz; + u16 min_pll_multiplier; + u16 max_pll_multiplier; + u32 min_pll_op_clk_freq_hz; + u32 max_pll_op_clk_freq_hz; }; /** @@ -159,14 +159,14 @@ struct ccs_pll_branch_limits_fr { * @max_pix_clk_freq_hz: Maximum pixel clock frequency */ struct ccs_pll_branch_limits_bk { - uint16_t min_sys_clk_div; - uint16_t max_sys_clk_div; - uint32_t min_sys_clk_freq_hz; - uint32_t max_sys_clk_freq_hz; - uint16_t min_pix_clk_div; - uint16_t max_pix_clk_div; - uint32_t min_pix_clk_freq_hz; - uint32_t max_pix_clk_freq_hz; + u16 min_sys_clk_div; + u16 max_sys_clk_div; + u32 min_sys_clk_freq_hz; + u32 max_sys_clk_freq_hz; + u16 min_pix_clk_div; + u16 max_pix_clk_div; + u32 min_pix_clk_freq_hz; + u32 max_pix_clk_freq_hz; }; /** @@ -183,8 +183,8 @@ struct ccs_pll_branch_limits_bk { */ struct ccs_pll_limits { /* Strict PLL limits */ - uint32_t min_ext_clk_freq_hz; - uint32_t max_ext_clk_freq_hz; + u32 min_ext_clk_freq_hz; + u32 max_ext_clk_freq_hz; struct ccs_pll_branch_limits_fr vt_fr; struct ccs_pll_branch_limits_bk vt_bk; @@ -192,8 +192,8 @@ struct ccs_pll_limits { struct ccs_pll_branch_limits_bk op_bk; /* Other relevant limits */ - uint32_t min_line_length_pck_bin; - uint32_t min_line_length_pck; + u32 min_line_length_pck_bin; + u32 min_line_length_pck; }; struct device; diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index b39ae5f8446b..15afbb4f5b31 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -28,6 +28,7 @@ #include <linux/v4l2-mediabus.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-device.h> +#include <uapi/linux/ccs.h> #include "ccs.h" @@ -382,15 +383,22 @@ static int ccs_pll_configure(struct ccs_sensor *sensor) if (rval < 0) return rval; - /* Lane op clock ratio does not apply here. */ - rval = ccs_write(sensor, REQUESTED_LINK_RATE, - DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, - 1000000 / 256 / 256) * - (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - sensor->pll.csi2.lanes : 1) << - (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? 1 : 0)); - if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) - return rval; + if (!(CCS_LIM(sensor, PHY_CTRL_CAPABILITY) & + CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL)) { + /* Lane op clock ratio does not apply here. */ + rval = ccs_write(sensor, REQUESTED_LINK_RATE, + DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz, + 1000000 / 256 / 256) * + (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + sensor->pll.csi2.lanes : 1) << + (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ? + 1 : 0)); + if (rval < 0) + return rval; + } + + if (sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS) + return 0; rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div); if (rval < 0) @@ -671,6 +679,49 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val); break; + + case V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN: + rval = ccs_write(sensor, ANALOG_LINEAR_GAIN_GLOBAL, ctrl->val); + + break; + + case V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN: + rval = ccs_write(sensor, ANALOG_EXPONENTIAL_GAIN_GLOBAL, + ctrl->val); + + break; + + case V4L2_CID_DIGITAL_GAIN: + if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) { + rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL, + ctrl->val); + break; + } + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_GREENR, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_RED, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_BLUE, + ctrl->val); + if (rval) + break; + + rval = ccs_write_addr(sensor, + SMIAPP_REG_U16_DIGITAL_GAIN_GREENB, + ctrl->val); + + break; case V4L2_CID_EXPOSURE: rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val); @@ -713,6 +764,19 @@ static int ccs_set_ctrl(struct v4l2_ctrl *ctrl) rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val); break; + case V4L2_CID_CCS_SHADING_CORRECTION: + rval = ccs_write(sensor, SHADING_CORRECTION_EN, + ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE : + 0); + + if (!rval && sensor->luminance_level) + v4l2_ctrl_activate(sensor->luminance_level, ctrl->val); + + break; + case V4L2_CID_CCS_LUMINANCE_CORRECTION_LEVEL: + rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val); + + break; case V4L2_CID_PIXEL_RATE: /* For v4l2_ctrl_s_ctrl_int64() used internally. */ rval = 0; @@ -739,19 +803,144 @@ static int ccs_init_controls(struct ccs_sensor *sensor) struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); int rval; - rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 12); + rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17); if (rval) return rval; sensor->pixel_array->ctrl_handler.lock = &sensor->mutex; - sensor->analog_gain = v4l2_ctrl_new_std( - &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops, - V4L2_CID_ANALOGUE_GAIN, - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), - max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U), - CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) { + case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: { + struct { + const char *name; + u32 id; + s32 value; + } const gain_ctrls[] = { + { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0, + CCS_LIM(sensor, ANALOG_GAIN_M0), }, + { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0, + CCS_LIM(sensor, ANALOG_GAIN_C0), }, + { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1, + CCS_LIM(sensor, ANALOG_GAIN_M1), }, + { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1, + CCS_LIM(sensor, ANALOG_GAIN_C1), }, + }; + struct v4l2_ctrl_config ctrl_cfg = { + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &ccs_ctrl_ops, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + .step = 1, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) { + ctrl_cfg.name = gain_ctrls[i].name; + ctrl_cfg.id = gain_ctrls[i].id; + ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def = + gain_ctrls[i].value; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX), + max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), + 1U), + CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN)); + } + break; + + case CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL: { + struct { + const char *name; + u32 id; + u16 min, max, step; + } const gain_ctrls[] = { + { + "Analogue Linear Gain", + V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN, + CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MIN), + CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MAX), + max(CCS_LIM(sensor, + ANALOG_LINEAR_GAIN_STEP_SIZE), + 1U), + }, + { + "Analogue Exponential Gain", + V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN, + CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MIN), + CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MAX), + max(CCS_LIM(sensor, + ANALOG_EXPONENTIAL_GAIN_STEP_SIZE), + 1U), + }, + }; + struct v4l2_ctrl_config ctrl_cfg = { + .type = V4L2_CTRL_TYPE_INTEGER, + .ops = &ccs_ctrl_ops, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) { + ctrl_cfg.name = gain_ctrls[i].name; + ctrl_cfg.min = ctrl_cfg.def = gain_ctrls[i].min; + ctrl_cfg.max = gain_ctrls[i].max; + ctrl_cfg.step = gain_ctrls[i].step; + ctrl_cfg.id = gain_ctrls[i].id; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + } + } + + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING | + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) { + const struct v4l2_ctrl_config ctrl_cfg = { + .name = "Shading Correction", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .id = V4L2_CID_CCS_SHADING_CORRECTION, + .ops = &ccs_ctrl_ops, + .max = 1, + .step = 1, + }; + + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + + if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) & + CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) { + const struct v4l2_ctrl_config ctrl_cfg = { + .name = "Luminance Correction Level", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .id = V4L2_CID_CCS_LUMINANCE_CORRECTION_LEVEL, + .ops = &ccs_ctrl_ops, + .max = 255, + .step = 1, + .def = 128, + }; + + sensor->luminance_level = + v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler, + &ctrl_cfg, NULL); + } + + if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL || + CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) == + SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL) + v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler, + &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN, + CCS_LIM(sensor, DIGITAL_GAIN_MIN), + CCS_LIM(sensor, DIGITAL_GAIN_MAX), + max(CCS_LIM(sensor, DIGITAL_GAIN_STEP_SIZE), + 1U), + 0x100); /* Exposure limits will be updated soon, use just something here. */ sensor->exposure = v4l2_ctrl_new_std( @@ -1001,7 +1190,7 @@ static void ccs_update_blanking(struct ccs_sensor *sensor) { struct v4l2_ctrl *vblank = sensor->vblank; struct v4l2_ctrl *hblank = sensor->hblank; - uint16_t min_fll, max_fll, min_llp, max_llp, min_lbp; + u16 min_fll, max_fll, min_llp, max_llp, min_lbp; int min, max; if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) { @@ -1322,6 +1511,28 @@ static int ccs_write_msr_regs(struct ccs_sensor *sensor) sensor->mdata.num_module_manufacturer_regs); } +static int ccs_update_phy_ctrl(struct ccs_sensor *sensor) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd); + u8 val; + + if (!sensor->ccs_limits) + return 0; + + if (CCS_LIM(sensor, PHY_CTRL_CAPABILITY) & + CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL) { + val = CCS_PHY_CTRL_AUTO; + } else if (CCS_LIM(sensor, PHY_CTRL_CAPABILITY) & + CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL) { + val = CCS_PHY_CTRL_UI; + } else { + dev_err(&client->dev, "manual PHY control not supported\n"); + return -EINVAL; + } + + return ccs_write(sensor, PHY_CTRL, val); +} + static int ccs_power_on(struct device *dev) { struct v4l2_subdev *subdev = dev_get_drvdata(dev); @@ -1333,7 +1544,6 @@ static int ccs_power_on(struct device *dev) struct ccs_sensor *sensor = container_of(ssd, struct ccs_sensor, ssds[0]); const struct ccs_device *ccsdev = device_get_match_data(dev); - unsigned int sleep; int rval; rval = regulator_bulk_enable(ARRAY_SIZE(ccs_regulators), @@ -1343,21 +1553,25 @@ static int ccs_power_on(struct device *dev) return rval; } - rval = clk_prepare_enable(sensor->ext_clk); - if (rval < 0) { - dev_dbg(dev, "failed to enable xclk\n"); - goto out_xclk_fail; - } + if (sensor->reset || sensor->xshutdown || sensor->ext_clk) { + unsigned int sleep; + + rval = clk_prepare_enable(sensor->ext_clk); + if (rval < 0) { + dev_dbg(dev, "failed to enable xclk\n"); + goto out_xclk_fail; + } - gpiod_set_value(sensor->reset, 0); - gpiod_set_value(sensor->xshutdown, 1); + gpiod_set_value(sensor->reset, 0); + gpiod_set_value(sensor->xshutdown, 1); - if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA) - sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk); - else - sleep = 5000; + if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA) + sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk); + else + sleep = 5000; - usleep_range(sleep, sleep); + usleep_range(sleep, sleep); + } /* * Failures to respond to the address change command have been noticed. @@ -1370,18 +1584,27 @@ static int ccs_power_on(struct device *dev) * is found. */ - if (sensor->hwcfg.i2c_addr_alt) { - rval = ccs_change_cci_addr(sensor); - if (rval) { - dev_err(dev, "cci address change error\n"); + if (!sensor->reset && !sensor->xshutdown) { + u8 retry = 100; + u32 reset; + + rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); + if (rval < 0) { + dev_err(dev, "software reset failed\n"); goto out_cci_addr_fail; } - } - rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON); - if (rval < 0) { - dev_err(dev, "software reset failed\n"); - goto out_cci_addr_fail; + do { + rval = ccs_read(sensor, SOFTWARE_RESET, &reset); + reset = !rval && reset == CCS_SOFTWARE_RESET_OFF; + if (reset) + break; + + usleep_range(1000, 2000); + } while (--retry); + + if (!reset) + return -EIO; } if (sensor->hwcfg.i2c_addr_alt) { @@ -1426,8 +1649,7 @@ static int ccs_power_on(struct device *dev) goto out_cci_addr_fail; } - /* DPHY control done by sensor based on requested link rate */ - rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI); + rval = ccs_update_phy_ctrl(sensor); if (rval < 0) goto out_cci_addr_fail; @@ -2908,7 +3130,8 @@ static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev) int i; int rval; - ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0, + FWNODE_GRAPH_ENDPOINT_NEXT); if (!ep) return -ENODEV; @@ -3080,6 +3303,11 @@ static int ccs_probe(struct i2c_client *client) return -EINVAL; } + if (!sensor->hwcfg.ext_clk) { + dev_err(&client->dev, "cannot work with xclk frequency 0\n"); + return -EINVAL; + } + sensor->reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(sensor->reset)) @@ -3148,6 +3376,10 @@ static int ccs_probe(struct i2c_client *client) goto out_free_ccs_limits; } + rval = ccs_update_phy_ctrl(sensor); + if (rval < 0) + goto out_free_ccs_limits; + /* * Handle Sensor Module orientation on the board. * diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c index 6555bd4b325a..45f2b2f55ec5 100644 --- a/drivers/media/i2c/ccs/ccs-data.c +++ b/drivers/media/i2c/ccs/ccs-data.c @@ -10,7 +10,6 @@ #include <linux/limits.h> #include <linux/mm.h> #include <linux/slab.h> -#include <linux/types.h> #include "ccs-data-defs.h" @@ -215,7 +214,7 @@ static int ccs_data_parse_regs(struct bin_container *bin, size_t *__num_regs, const void *payload, const void *endp, struct device *dev) { - struct ccs_reg *regs_base, *regs; + struct ccs_reg *regs_base = NULL, *regs = NULL; size_t num_regs = 0; u16 addr = 0; @@ -286,6 +285,9 @@ static int ccs_data_parse_regs(struct bin_container *bin, if (!bin->base) { bin_reserve(bin, len); } else if (__regs) { + if (!regs) + return -EIO; + regs->addr = addr; regs->len = len; regs->value = bin_alloc(bin, len); @@ -306,8 +308,12 @@ static int ccs_data_parse_regs(struct bin_container *bin, if (__num_regs) *__num_regs = num_regs; - if (bin->base && __regs) + if (bin->base && __regs) { + if (!regs_base) + return -EIO; + *__regs = regs_base; + } return 0; } @@ -426,7 +432,7 @@ static int ccs_data_parse_rules(struct bin_container *bin, size_t *__num_rules, const void *payload, const void *endp, struct device *dev) { - struct ccs_rule *rules_base, *rules = NULL, *next_rule; + struct ccs_rule *rules_base = NULL, *rules = NULL, *next_rule = NULL; size_t num_rules = 0; const void *__next_rule = payload; int rval; @@ -484,6 +490,9 @@ static int ccs_data_parse_rules(struct bin_container *bin, } else { unsigned int i; + if (!next_rule) + return -EIO; + rules = next_rule; next_rule++; @@ -556,6 +565,9 @@ static int ccs_data_parse_rules(struct bin_container *bin, bin_reserve(bin, sizeof(*rules) * num_rules); *__num_rules = num_rules; } else { + if (!rules_base) + return -EIO; + *__rules = rules_base; } @@ -691,7 +703,7 @@ static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_lo } for (i = 0; i < max_block_type_id; i++) { - struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup; + struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup = NULL; unsigned int j; if (!is_contained(__num_pixel_descs, endp)) @@ -722,6 +734,9 @@ static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_lo if (!bin->base) continue; + if (!pdgroup) + return -EIO; + pdesc = &pdgroup->descs[j]; pdesc->pixel_type = __pixel_desc->pixel_type; pdesc->small_offset_x = __pixel_desc->small_offset_x; diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h index 50d6508b24f3..c75d480c8792 100644 --- a/drivers/media/i2c/ccs/ccs-data.h +++ b/drivers/media/i2c/ccs/ccs-data.h @@ -10,6 +10,8 @@ #include <linux/types.h> +struct device; + /** * struct ccs_data_block_version - CCS static data version * @version_major: Major version number diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c index b776af2a3c33..25993445f4fe 100644 --- a/drivers/media/i2c/ccs/ccs-reg-access.c +++ b/drivers/media/i2c/ccs/ccs-reg-access.c @@ -17,11 +17,10 @@ #include "ccs.h" #include "ccs-limits.h" -static uint32_t float_to_u32_mul_1000000(struct i2c_client *client, - uint32_t phloat) +static u32 float_to_u32_mul_1000000(struct i2c_client *client, u32 phloat) { - int32_t exp; - uint64_t man; + s32 exp; + u64 man; if (phloat >= 0x80000000) { dev_err(&client->dev, "this is a negative number\n"); @@ -137,11 +136,11 @@ static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg, unsigned int ccs_reg_width(u32 reg) { if (reg & CCS_FL_16BIT) - return sizeof(uint16_t); + return sizeof(u16); if (reg & CCS_FL_32BIT) - return sizeof(uint32_t); + return sizeof(u32); - return sizeof(uint8_t); + return sizeof(u8); } static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val) @@ -205,7 +204,7 @@ static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs, size_t i; for (i = 0; i < num_regs; i++, regs++) { - uint8_t *data; + u8 *data; if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width) continue; @@ -216,13 +215,13 @@ static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs, data = ®s->value[CCS_REG_ADDR(reg) - regs->addr]; switch (width) { - case sizeof(uint8_t): + case sizeof(u8): *val = *data; break; - case sizeof(uint16_t): + case sizeof(u16): *val = get_unaligned_be16(data); break; - case sizeof(uint32_t): + case sizeof(u32): *val = get_unaligned_be32(data); break; default: @@ -387,12 +386,20 @@ int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs, for (j = 0; j < regs->len; j += msg.len - 2, regdata += msg.len - 2) { + char printbuf[(MAX_WRITE_LEN << 1) + + 1 /* \0 */] = { 0 }; int rval; msg.len = min(regs->len - j, MAX_WRITE_LEN); + bin2hex(printbuf, regdata, msg.len); + dev_dbg(&client->dev, + "writing msr reg 0x%4.4x value 0x%s\n", + regs->addr + j, printbuf); + put_unaligned_be16(regs->addr + j, buf); memcpy(buf + 2, regdata, msg.len); + msg.len += 2; rval = ccs_write_retry(client, &msg); diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h index 356b87c33405..6beac375cc48 100644 --- a/drivers/media/i2c/ccs/ccs.h +++ b/drivers/media/i2c/ccs/ccs.h @@ -84,11 +84,11 @@ struct ccs_hwconfig { unsigned short i2c_addr_dfl; /* Default i2c addr */ unsigned short i2c_addr_alt; /* Alternate i2c addr */ - uint32_t ext_clk; /* sensor external clk */ + u32 ext_clk; /* sensor external clk */ unsigned int lanes; /* Number of CSI-2 lanes */ - uint32_t csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */ - uint64_t *op_sys_clock; + u32 csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */ + u64 *op_sys_clock; enum ccs_module_board_orient module_board_orient; @@ -262,13 +262,13 @@ struct ccs_sensor { unsigned long *valid_link_freqs; /* Pixel array controls */ - struct v4l2_ctrl *analog_gain; struct v4l2_ctrl *exposure; struct v4l2_ctrl *hflip; struct v4l2_ctrl *vflip; struct v4l2_ctrl *vblank; struct v4l2_ctrl *hblank; struct v4l2_ctrl *pixel_rate_parray; + struct v4l2_ctrl *luminance_level; /* src controls */ struct v4l2_ctrl *link_freq; struct v4l2_ctrl *pixel_rate_csi; diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h index e80c110ebf3a..177e3e51207a 100644 --- a/drivers/media/i2c/ccs/smiapp-reg-defs.h +++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h @@ -535,6 +535,8 @@ #define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0 #define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1 +#define SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL 1 + #define SMIAPP_BINNING_CAPABILITY_NO 0 #define SMIAPP_BINNING_CAPABILITY_YES 1 diff --git a/drivers/media/i2c/imx219.c b/drivers/media/i2c/imx219.c index e7791a0848b3..6e3382b85a90 100644 --- a/drivers/media/i2c/imx219.c +++ b/drivers/media/i2c/imx219.c @@ -390,6 +390,10 @@ static const struct imx219_reg raw10_framefmt_regs[] = { {0x0309, 0x0a}, }; +static const s64 imx219_link_freq_menu[] = { + IMX219_DEFAULT_LINK_FREQ, +}; + static const char * const imx219_test_pattern_menu[] = { "Disabled", "Color Bars", @@ -547,6 +551,7 @@ struct imx219 { struct v4l2_ctrl_handler ctrl_handler; /* V4L2 Controls */ struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *link_freq; struct v4l2_ctrl *exposure; struct v4l2_ctrl *vflip; struct v4l2_ctrl *hflip; @@ -806,7 +811,9 @@ static int imx219_enum_mbus_code(struct v4l2_subdev *sd, if (code->index >= (ARRAY_SIZE(codes) / 4)) return -EINVAL; + mutex_lock(&imx219->mutex); code->code = imx219_get_format_code(imx219, codes[code->index * 4]); + mutex_unlock(&imx219->mutex); return 0; } @@ -816,11 +823,15 @@ static int imx219_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_frame_size_enum *fse) { struct imx219 *imx219 = to_imx219(sd); + u32 code; if (fse->index >= ARRAY_SIZE(supported_modes)) return -EINVAL; - if (fse->code != imx219_get_format_code(imx219, fse->code)) + mutex_lock(&imx219->mutex); + code = imx219_get_format_code(imx219, fse->code); + mutex_unlock(&imx219->mutex); + if (fse->code != code) return -EINVAL; fse->min_width = supported_modes[fse->index].width; @@ -1263,7 +1274,7 @@ static int imx219_init_controls(struct imx219 *imx219) int i, ret; ctrl_hdlr = &imx219->ctrl_handler; - ret = v4l2_ctrl_handler_init(ctrl_hdlr, 11); + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12); if (ret) return ret; @@ -1277,6 +1288,14 @@ static int imx219_init_controls(struct imx219 *imx219) IMX219_PIXEL_RATE, 1, IMX219_PIXEL_RATE); + imx219->link_freq = + v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(imx219_link_freq_menu) - 1, 0, + imx219_link_freq_menu); + if (imx219->link_freq) + imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + /* Initial vblank/hblank/exposure parameters based on current mode */ imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_VBLANK, IMX219_VBLANK_MIN, diff --git a/drivers/media/i2c/imx258.c b/drivers/media/i2c/imx258.c index df62c69a48c0..61d74b794582 100644 --- a/drivers/media/i2c/imx258.c +++ b/drivers/media/i2c/imx258.c @@ -2,6 +2,7 @@ // Copyright (C) 2018 Intel Corporation #include <linux/acpi.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/module.h> @@ -68,6 +69,9 @@ #define REG_CONFIG_MIRROR_FLIP 0x03 #define REG_CONFIG_FLIP_TEST_PATTERN 0x02 +/* Input clock frequency in Hz */ +#define IMX258_INPUT_CLOCK_FREQ 19200000 + struct imx258_reg { u16 address; u8 val; @@ -610,6 +614,8 @@ struct imx258 { /* Streaming on/off */ bool streaming; + + struct clk *clk; }; static inline struct imx258 *to_imx258(struct v4l2_subdev *_sd) @@ -972,6 +978,29 @@ static int imx258_stop_streaming(struct imx258 *imx258) return 0; } +static int imx258_power_on(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx258 *imx258 = to_imx258(sd); + int ret; + + ret = clk_prepare_enable(imx258->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static int imx258_power_off(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx258 *imx258 = to_imx258(sd); + + clk_disable_unprepare(imx258->clk); + + return 0; +} + static int imx258_set_stream(struct v4l2_subdev *sd, int enable) { struct imx258 *imx258 = to_imx258(sd); @@ -1018,8 +1047,7 @@ err_unlock: static int __maybe_unused imx258_suspend(struct device *dev) { - struct i2c_client *client = to_i2c_client(dev); - struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct v4l2_subdev *sd = dev_get_drvdata(dev); struct imx258 *imx258 = to_imx258(sd); if (imx258->streaming) @@ -1030,8 +1058,7 @@ static int __maybe_unused imx258_suspend(struct device *dev) static int __maybe_unused imx258_resume(struct device *dev) { - struct i2c_client *client = to_i2c_client(dev); - struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct v4l2_subdev *sd = dev_get_drvdata(dev); struct imx258 *imx258 = to_imx258(sd); int ret; @@ -1201,9 +1228,26 @@ static int imx258_probe(struct i2c_client *client) int ret; u32 val = 0; - device_property_read_u32(&client->dev, "clock-frequency", &val); - if (val != 19200000) + imx258 = devm_kzalloc(&client->dev, sizeof(*imx258), GFP_KERNEL); + if (!imx258) + return -ENOMEM; + + imx258->clk = devm_clk_get_optional(&client->dev, NULL); + if (!imx258->clk) { + dev_dbg(&client->dev, + "no clock provided, using clock-frequency property\n"); + + device_property_read_u32(&client->dev, "clock-frequency", &val); + if (val != IMX258_INPUT_CLOCK_FREQ) + return -EINVAL; + } else if (IS_ERR(imx258->clk)) { + return dev_err_probe(&client->dev, PTR_ERR(imx258->clk), + "error getting clock\n"); + } + if (clk_get_rate(imx258->clk) != IMX258_INPUT_CLOCK_FREQ) { + dev_err(&client->dev, "input clock frequency not supported\n"); return -EINVAL; + } /* * Check that the device is mounted upside down. The driver only @@ -1213,24 +1257,25 @@ static int imx258_probe(struct i2c_client *client) if (ret || val != 180) return -EINVAL; - imx258 = devm_kzalloc(&client->dev, sizeof(*imx258), GFP_KERNEL); - if (!imx258) - return -ENOMEM; - /* Initialize subdev */ v4l2_i2c_subdev_init(&imx258->sd, client, &imx258_subdev_ops); + /* Will be powered off via pm_runtime_idle */ + ret = imx258_power_on(&client->dev); + if (ret) + return ret; + /* Check module identity */ ret = imx258_identify_module(imx258); if (ret) - return ret; + goto error_identify; /* Set default mode to max resolution */ imx258->cur_mode = &supported_modes[0]; ret = imx258_init_controls(imx258); if (ret) - return ret; + goto error_identify; /* Initialize subdev */ imx258->sd.internal_ops = &imx258_internal_ops; @@ -1260,6 +1305,9 @@ error_media_entity: error_handler_free: imx258_free_controls(imx258); +error_identify: + imx258_power_off(&client->dev); + return ret; } @@ -1273,6 +1321,8 @@ static int imx258_remove(struct i2c_client *client) imx258_free_controls(imx258); pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + imx258_power_off(&client->dev); pm_runtime_set_suspended(&client->dev); return 0; @@ -1280,6 +1330,7 @@ static int imx258_remove(struct i2c_client *client) static const struct dev_pm_ops imx258_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(imx258_suspend, imx258_resume) + SET_RUNTIME_PM_OPS(imx258_power_off, imx258_power_on, NULL) }; #ifdef CONFIG_ACPI @@ -1291,11 +1342,18 @@ static const struct acpi_device_id imx258_acpi_ids[] = { MODULE_DEVICE_TABLE(acpi, imx258_acpi_ids); #endif +static const struct of_device_id imx258_dt_ids[] = { + { .compatible = "sony,imx258" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx258_dt_ids); + static struct i2c_driver imx258_i2c_driver = { .driver = { .name = "imx258", .pm = &imx258_pm_ops, .acpi_match_table = ACPI_PTR(imx258_acpi_ids), + .of_match_table = imx258_dt_ids, }, .probe_new = imx258_probe, .remove = imx258_remove, diff --git a/drivers/media/i2c/imx334.c b/drivers/media/i2c/imx334.c new file mode 100644 index 000000000000..ad530f0d338a --- /dev/null +++ b/drivers/media/i2c/imx334.c @@ -0,0 +1,1132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Sony imx334 sensor driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include <asm/unaligned.h> + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/pm_runtime.h> + +#include <media/v4l2-ctrls.h> +#include <media/v4l2-fwnode.h> +#include <media/v4l2-subdev.h> + +/* Streaming Mode */ +#define IMX334_REG_MODE_SELECT 0x3000 +#define IMX334_MODE_STANDBY 0x01 +#define IMX334_MODE_STREAMING 0x00 + +/* Lines per frame */ +#define IMX334_REG_LPFR 0x3030 + +/* Chip ID */ +#define IMX334_REG_ID 0x3044 +#define IMX334_ID 0x1e + +/* Exposure control */ +#define IMX334_REG_SHUTTER 0x3058 +#define IMX334_EXPOSURE_MIN 1 +#define IMX334_EXPOSURE_OFFSET 5 +#define IMX334_EXPOSURE_STEP 1 +#define IMX334_EXPOSURE_DEFAULT 0x0648 + +/* Analog gain control */ +#define IMX334_REG_AGAIN 0x30e8 +#define IMX334_AGAIN_MIN 0 +#define IMX334_AGAIN_MAX 240 +#define IMX334_AGAIN_STEP 1 +#define IMX334_AGAIN_DEFAULT 0 + +/* Group hold register */ +#define IMX334_REG_HOLD 0x3001 + +/* Input clock rate */ +#define IMX334_INCLK_RATE 24000000 + +/* CSI2 HW configuration */ +#define IMX334_LINK_FREQ 891000000 +#define IMX334_NUM_DATA_LANES 4 + +#define IMX334_REG_MIN 0x00 +#define IMX334_REG_MAX 0xfffff + +/** + * struct imx334_reg - imx334 sensor register + * @address: Register address + * @val: Register value + */ +struct imx334_reg { + u16 address; + u8 val; +}; + +/** + * struct imx334_reg_list - imx334 sensor register list + * @num_of_regs: Number of registers in the list + * @regs: Pointer to register list + */ +struct imx334_reg_list { + u32 num_of_regs; + const struct imx334_reg *regs; +}; + +/** + * struct imx334_mode - imx334 sensor mode structure + * @width: Frame width + * @height: Frame height + * @code: Format code + * @hblank: Horizontal blanking in lines + * @vblank: Vertical blanking in lines + * @vblank_min: Minimal vertical blanking in lines + * @vblank_max: Maximum vertical blanking in lines + * @pclk: Sensor pixel clock + * @link_freq_idx: Link frequency index + * @reg_list: Register list for sensor mode + */ +struct imx334_mode { + u32 width; + u32 height; + u32 code; + u32 hblank; + u32 vblank; + u32 vblank_min; + u32 vblank_max; + u64 pclk; + u32 link_freq_idx; + struct imx334_reg_list reg_list; +}; + +/** + * struct imx334 - imx334 sensor device structure + * @dev: Pointer to generic device + * @client: Pointer to i2c client + * @sd: V4L2 sub-device + * @pad: Media pad. Only one pad supported + * @reset_gpio: Sensor reset gpio + * @inclk: Sensor input clock + * @ctrl_handler: V4L2 control handler + * @link_freq_ctrl: Pointer to link frequency control + * @pclk_ctrl: Pointer to pixel clock control + * @hblank_ctrl: Pointer to horizontal blanking control + * @vblank_ctrl: Pointer to vertical blanking control + * @exp_ctrl: Pointer to exposure control + * @again_ctrl: Pointer to analog gain control + * @vblank: Vertical blanking in lines + * @cur_mode: Pointer to current selected sensor mode + * @mutex: Mutex for serializing sensor controls + * @streaming: Flag indicating streaming state + */ +struct imx334 { + struct device *dev; + struct i2c_client *client; + struct v4l2_subdev sd; + struct media_pad pad; + struct gpio_desc *reset_gpio; + struct clk *inclk; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *link_freq_ctrl; + struct v4l2_ctrl *pclk_ctrl; + struct v4l2_ctrl *hblank_ctrl; + struct v4l2_ctrl *vblank_ctrl; + struct { + struct v4l2_ctrl *exp_ctrl; + struct v4l2_ctrl *again_ctrl; + }; + u32 vblank; + const struct imx334_mode *cur_mode; + struct mutex mutex; + bool streaming; +}; + +static const s64 link_freq[] = { + IMX334_LINK_FREQ, +}; + +/* Sensor mode registers */ +static const struct imx334_reg mode_3840x2160_regs[] = { + {0x3000, 0x01}, + {0x3002, 0x00}, + {0x3018, 0x04}, + {0x37b0, 0x36}, + {0x304c, 0x00}, + {0x300c, 0x3b}, + {0x300d, 0x2a}, + {0x3034, 0x26}, + {0x3035, 0x02}, + {0x314c, 0x29}, + {0x314d, 0x01}, + {0x315a, 0x02}, + {0x3168, 0xa0}, + {0x316a, 0x7e}, + {0x3288, 0x21}, + {0x328a, 0x02}, + {0x302c, 0x3c}, + {0x302e, 0x00}, + {0x302f, 0x0f}, + {0x3076, 0x70}, + {0x3077, 0x08}, + {0x3090, 0x70}, + {0x3091, 0x08}, + {0x30d8, 0x20}, + {0x30d9, 0x12}, + {0x3308, 0x70}, + {0x3309, 0x08}, + {0x3414, 0x05}, + {0x3416, 0x18}, + {0x35ac, 0x0e}, + {0x3648, 0x01}, + {0x364a, 0x04}, + {0x364c, 0x04}, + {0x3678, 0x01}, + {0x367c, 0x31}, + {0x367e, 0x31}, + {0x3708, 0x02}, + {0x3714, 0x01}, + {0x3715, 0x02}, + {0x3716, 0x02}, + {0x3717, 0x02}, + {0x371c, 0x3d}, + {0x371d, 0x3f}, + {0x372c, 0x00}, + {0x372d, 0x00}, + {0x372e, 0x46}, + {0x372f, 0x00}, + {0x3730, 0x89}, + {0x3731, 0x00}, + {0x3732, 0x08}, + {0x3733, 0x01}, + {0x3734, 0xfe}, + {0x3735, 0x05}, + {0x375d, 0x00}, + {0x375e, 0x00}, + {0x375f, 0x61}, + {0x3760, 0x06}, + {0x3768, 0x1b}, + {0x3769, 0x1b}, + {0x376a, 0x1a}, + {0x376b, 0x19}, + {0x376c, 0x18}, + {0x376d, 0x14}, + {0x376e, 0x0f}, + {0x3776, 0x00}, + {0x3777, 0x00}, + {0x3778, 0x46}, + {0x3779, 0x00}, + {0x377a, 0x08}, + {0x377b, 0x01}, + {0x377c, 0x45}, + {0x377d, 0x01}, + {0x377e, 0x23}, + {0x377f, 0x02}, + {0x3780, 0xd9}, + {0x3781, 0x03}, + {0x3782, 0xf5}, + {0x3783, 0x06}, + {0x3784, 0xa5}, + {0x3788, 0x0f}, + {0x378a, 0xd9}, + {0x378b, 0x03}, + {0x378c, 0xeb}, + {0x378d, 0x05}, + {0x378e, 0x87}, + {0x378f, 0x06}, + {0x3790, 0xf5}, + {0x3792, 0x43}, + {0x3794, 0x7a}, + {0x3796, 0xa1}, + {0x3e04, 0x0e}, + {0x3a00, 0x01}, +}; + +/* Supported sensor mode configurations */ +static const struct imx334_mode supported_mode = { + .width = 3840, + .height = 2160, + .hblank = 560, + .vblank = 2340, + .vblank_min = 90, + .vblank_max = 132840, + .pclk = 594000000, + .link_freq_idx = 0, + .code = MEDIA_BUS_FMT_SRGGB12_1X12, + .reg_list = { + .num_of_regs = ARRAY_SIZE(mode_3840x2160_regs), + .regs = mode_3840x2160_regs, + }, +}; + +/** + * to_imx334() - imv334 V4L2 sub-device to imx334 device. + * @subdev: pointer to imx334 V4L2 sub-device + * + * Return: pointer to imx334 device + */ +static inline struct imx334 *to_imx334(struct v4l2_subdev *subdev) +{ + return container_of(subdev, struct imx334, sd); +} + +/** + * imx334_read_reg() - Read registers. + * @imx334: pointer to imx334 device + * @reg: register address + * @len: length of bytes to read. Max supported bytes is 4 + * @val: pointer to register value to be filled. + * + * Big endian register addresses with little endian values. + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_read_reg(struct imx334 *imx334, u16 reg, u32 len, u32 *val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd); + struct i2c_msg msgs[2] = {0}; + u8 addr_buf[2] = {0}; + u8 data_buf[4] = {0}; + int ret; + + if (WARN_ON(len > 4)) + return -EINVAL; + + put_unaligned_be16(reg, addr_buf); + + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = len; + msgs[1].buf = data_buf; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) + return -EIO; + + *val = get_unaligned_le32(data_buf); + + return 0; +} + +/** + * imx334_write_reg() - Write register + * @imx334: pointer to imx334 device + * @reg: register address + * @len: length of bytes. Max supported bytes is 4 + * @val: register value + * + * Big endian register addresses with little endian values. + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_write_reg(struct imx334 *imx334, u16 reg, u32 len, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&imx334->sd); + u8 buf[6] = {0}; + + if (WARN_ON(len > 4)) + return -EINVAL; + + put_unaligned_be16(reg, buf); + put_unaligned_le32(val, buf + 2); + if (i2c_master_send(client, buf, len + 2) != len + 2) + return -EIO; + + return 0; +} + +/** + * imx334_write_regs() - Write a list of registers + * @imx334: pointer to imx334 device + * @regs: list of registers to be written + * @len: length of registers array + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_write_regs(struct imx334 *imx334, + const struct imx334_reg *regs, u32 len) +{ + unsigned int i; + int ret; + + for (i = 0; i < len; i++) { + ret = imx334_write_reg(imx334, regs[i].address, 1, regs[i].val); + if (ret) + return ret; + } + + return 0; +} + +/** + * imx334_update_controls() - Update control ranges based on streaming mode + * @imx334: pointer to imx334 device + * @mode: pointer to imx334_mode sensor mode + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_update_controls(struct imx334 *imx334, + const struct imx334_mode *mode) +{ + int ret; + + ret = __v4l2_ctrl_s_ctrl(imx334->link_freq_ctrl, mode->link_freq_idx); + if (ret) + return ret; + + ret = __v4l2_ctrl_s_ctrl(imx334->hblank_ctrl, mode->hblank); + if (ret) + return ret; + + return __v4l2_ctrl_modify_range(imx334->vblank_ctrl, mode->vblank_min, + mode->vblank_max, 1, mode->vblank); +} + +/** + * imx334_update_exp_gain() - Set updated exposure and gain + * @imx334: pointer to imx334 device + * @exposure: updated exposure value + * @gain: updated analog gain value + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_update_exp_gain(struct imx334 *imx334, u32 exposure, u32 gain) +{ + u32 lpfr, shutter; + int ret; + + lpfr = imx334->vblank + imx334->cur_mode->height; + shutter = lpfr - exposure; + + dev_dbg(imx334->dev, "Set long exp %u analog gain %u sh0 %u lpfr %u", + exposure, gain, shutter, lpfr); + + ret = imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 1); + if (ret) + return ret; + + ret = imx334_write_reg(imx334, IMX334_REG_LPFR, 3, lpfr); + if (ret) + goto error_release_group_hold; + + ret = imx334_write_reg(imx334, IMX334_REG_SHUTTER, 3, shutter); + if (ret) + goto error_release_group_hold; + + ret = imx334_write_reg(imx334, IMX334_REG_AGAIN, 1, gain); + +error_release_group_hold: + imx334_write_reg(imx334, IMX334_REG_HOLD, 1, 0); + + return ret; +} + +/** + * imx334_set_ctrl() - Set subdevice control + * @ctrl: pointer to v4l2_ctrl structure + * + * Supported controls: + * - V4L2_CID_VBLANK + * - cluster controls: + * - V4L2_CID_ANALOGUE_GAIN + * - V4L2_CID_EXPOSURE + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx334 *imx334 = + container_of(ctrl->handler, struct imx334, ctrl_handler); + u32 analog_gain; + u32 exposure; + int ret; + + switch (ctrl->id) { + case V4L2_CID_VBLANK: + imx334->vblank = imx334->vblank_ctrl->val; + + dev_dbg(imx334->dev, "Received vblank %u, new lpfr %u", + imx334->vblank, + imx334->vblank + imx334->cur_mode->height); + + ret = __v4l2_ctrl_modify_range(imx334->exp_ctrl, + IMX334_EXPOSURE_MIN, + imx334->vblank + + imx334->cur_mode->height - + IMX334_EXPOSURE_OFFSET, + 1, IMX334_EXPOSURE_DEFAULT); + break; + case V4L2_CID_EXPOSURE: + + /* Set controls only if sensor is in power on state */ + if (!pm_runtime_get_if_in_use(imx334->dev)) + return 0; + + exposure = ctrl->val; + analog_gain = imx334->again_ctrl->val; + + dev_dbg(imx334->dev, "Received exp %u analog gain %u", + exposure, analog_gain); + + ret = imx334_update_exp_gain(imx334, exposure, analog_gain); + + pm_runtime_put(imx334->dev); + + break; + default: + dev_err(imx334->dev, "Invalid control %d", ctrl->id); + ret = -EINVAL; + } + + return ret; +} + +/* V4l2 subdevice control ops*/ +static const struct v4l2_ctrl_ops imx334_ctrl_ops = { + .s_ctrl = imx334_set_ctrl, +}; + +/** + * imx334_enum_mbus_code() - Enumerate V4L2 sub-device mbus codes + * @sd: pointer to imx334 V4L2 sub-device structure + * @cfg: V4L2 sub-device pad configuration + * @code: V4L2 sub-device code enumeration need to be filled + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index > 0) + return -EINVAL; + + code->code = supported_mode.code; + + return 0; +} + +/** + * imx334_enum_frame_size() - Enumerate V4L2 sub-device frame sizes + * @sd: pointer to imx334 V4L2 sub-device structure + * @cfg: V4L2 sub-device pad configuration + * @fsize: V4L2 sub-device size enumeration need to be filled + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fsize) +{ + if (fsize->index > 0) + return -EINVAL; + + if (fsize->code != supported_mode.code) + return -EINVAL; + + fsize->min_width = supported_mode.width; + fsize->max_width = fsize->min_width; + fsize->min_height = supported_mode.height; + fsize->max_height = fsize->min_height; + + return 0; +} + +/** + * imx334_fill_pad_format() - Fill subdevice pad format + * from selected sensor mode + * @imx334: pointer to imx334 device + * @mode: pointer to imx334_mode sensor mode + * @fmt: V4L2 sub-device format need to be filled + */ +static void imx334_fill_pad_format(struct imx334 *imx334, + const struct imx334_mode *mode, + struct v4l2_subdev_format *fmt) +{ + fmt->format.width = mode->width; + fmt->format.height = mode->height; + fmt->format.code = mode->code; + fmt->format.field = V4L2_FIELD_NONE; + fmt->format.colorspace = V4L2_COLORSPACE_RAW; + fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + fmt->format.quantization = V4L2_QUANTIZATION_DEFAULT; + fmt->format.xfer_func = V4L2_XFER_FUNC_NONE; +} + +/** + * imx334_get_pad_format() - Get subdevice pad format + * @sd: pointer to imx334 V4L2 sub-device structure + * @cfg: V4L2 sub-device pad configuration + * @fmt: V4L2 sub-device format need to be set + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_get_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct imx334 *imx334 = to_imx334(sd); + + mutex_lock(&imx334->mutex); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + struct v4l2_mbus_framefmt *framefmt; + + framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + fmt->format = *framefmt; + } else { + imx334_fill_pad_format(imx334, imx334->cur_mode, fmt); + } + + mutex_unlock(&imx334->mutex); + + return 0; +} + +/** + * imx334_set_pad_format() - Set subdevice pad format + * @sd: pointer to imx334 V4L2 sub-device structure + * @cfg: V4L2 sub-device pad configuration + * @fmt: V4L2 sub-device format need to be set + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct imx334 *imx334 = to_imx334(sd); + const struct imx334_mode *mode; + int ret = 0; + + mutex_lock(&imx334->mutex); + + mode = &supported_mode; + imx334_fill_pad_format(imx334, mode, fmt); + + if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { + struct v4l2_mbus_framefmt *framefmt; + + framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad); + *framefmt = fmt->format; + } else { + ret = imx334_update_controls(imx334, mode); + if (!ret) + imx334->cur_mode = mode; + } + + mutex_unlock(&imx334->mutex); + + return ret; +} + +/** + * imx334_init_pad_cfg() - Initialize sub-device pad configuration + * @sd: pointer to imx334 V4L2 sub-device structure + * @cfg: V4L2 sub-device pad configuration + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_init_pad_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct imx334 *imx334 = to_imx334(sd); + struct v4l2_subdev_format fmt = { 0 }; + + fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; + imx334_fill_pad_format(imx334, &supported_mode, &fmt); + + return imx334_set_pad_format(sd, cfg, &fmt); +} + +/** + * imx334_start_streaming() - Start sensor stream + * @imx334: pointer to imx334 device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_start_streaming(struct imx334 *imx334) +{ + const struct imx334_reg_list *reg_list; + int ret; + + /* Write sensor mode registers */ + reg_list = &imx334->cur_mode->reg_list; + ret = imx334_write_regs(imx334, reg_list->regs, + reg_list->num_of_regs); + if (ret) { + dev_err(imx334->dev, "fail to write initial registers"); + return ret; + } + + /* Setup handler will write actual exposure and gain */ + ret = __v4l2_ctrl_handler_setup(imx334->sd.ctrl_handler); + if (ret) { + dev_err(imx334->dev, "fail to setup handler"); + return ret; + } + + /* Start streaming */ + ret = imx334_write_reg(imx334, IMX334_REG_MODE_SELECT, + 1, IMX334_MODE_STREAMING); + if (ret) { + dev_err(imx334->dev, "fail to start streaming"); + return ret; + } + + return 0; +} + +/** + * imx334_stop_streaming() - Stop sensor stream + * @imx334: pointer to imx334 device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_stop_streaming(struct imx334 *imx334) +{ + return imx334_write_reg(imx334, IMX334_REG_MODE_SELECT, + 1, IMX334_MODE_STANDBY); +} + +/** + * imx334_set_stream() - Enable sensor streaming + * @sd: pointer to imx334 subdevice + * @enable: set to enable sensor streaming + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_set_stream(struct v4l2_subdev *sd, int enable) +{ + struct imx334 *imx334 = to_imx334(sd); + int ret; + + mutex_lock(&imx334->mutex); + + if (imx334->streaming == enable) { + mutex_unlock(&imx334->mutex); + return 0; + } + + if (enable) { + ret = pm_runtime_get_sync(imx334->dev); + if (ret) + goto error_power_off; + + ret = imx334_start_streaming(imx334); + if (ret) + goto error_power_off; + } else { + imx334_stop_streaming(imx334); + pm_runtime_put(imx334->dev); + } + + imx334->streaming = enable; + + mutex_unlock(&imx334->mutex); + + return 0; + +error_power_off: + pm_runtime_put(imx334->dev); + mutex_unlock(&imx334->mutex); + + return ret; +} + +/** + * imx334_detect() - Detect imx334 sensor + * @imx334: pointer to imx334 device + * + * Return: 0 if successful, -EIO if sensor id does not match + */ +static int imx334_detect(struct imx334 *imx334) +{ + int ret; + u32 val; + + ret = imx334_read_reg(imx334, IMX334_REG_ID, 2, &val); + if (ret) + return ret; + + if (val != IMX334_ID) { + dev_err(imx334->dev, "chip id mismatch: %x!=%x", + IMX334_ID, val); + return -ENXIO; + } + + return 0; +} + +/** + * imx334_parse_hw_config() - Parse HW configuration and check if supported + * @imx334: pointer to imx334 device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_parse_hw_config(struct imx334 *imx334) +{ + struct fwnode_handle *fwnode = dev_fwnode(imx334->dev); + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY + }; + struct fwnode_handle *ep; + unsigned long rate; + int ret; + int i; + + if (!fwnode) + return -ENXIO; + + /* Request optional reset pin */ + imx334->reset_gpio = devm_gpiod_get_optional(imx334->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(imx334->reset_gpio)) { + dev_err(imx334->dev, "failed to get reset gpio %ld", + PTR_ERR(imx334->reset_gpio)); + return PTR_ERR(imx334->reset_gpio); + } + + /* Get sensor input clock */ + imx334->inclk = devm_clk_get(imx334->dev, NULL); + if (IS_ERR(imx334->inclk)) { + dev_err(imx334->dev, "could not get inclk"); + return PTR_ERR(imx334->inclk); + } + + rate = clk_get_rate(imx334->inclk); + if (rate != IMX334_INCLK_RATE) { + dev_err(imx334->dev, "inclk frequency mismatch"); + return -EINVAL; + } + + ep = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (!ep) + return -ENXIO; + + ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX334_NUM_DATA_LANES) { + dev_err(imx334->dev, + "number of CSI2 data lanes %d is not supported", + bus_cfg.bus.mipi_csi2.num_data_lanes); + ret = -EINVAL; + goto done_endpoint_free; + } + + if (!bus_cfg.nr_of_link_frequencies) { + dev_err(imx334->dev, "no link frequencies defined"); + ret = -EINVAL; + goto done_endpoint_free; + } + + for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) + if (bus_cfg.link_frequencies[i] == IMX334_LINK_FREQ) + goto done_endpoint_free; + + ret = -EINVAL; + +done_endpoint_free: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +} + +/* V4l2 subdevice ops */ +static const struct v4l2_subdev_video_ops imx334_video_ops = { + .s_stream = imx334_set_stream, +}; + +static const struct v4l2_subdev_pad_ops imx334_pad_ops = { + .init_cfg = imx334_init_pad_cfg, + .enum_mbus_code = imx334_enum_mbus_code, + .enum_frame_size = imx334_enum_frame_size, + .get_fmt = imx334_get_pad_format, + .set_fmt = imx334_set_pad_format, +}; + +static const struct v4l2_subdev_ops imx334_subdev_ops = { + .video = &imx334_video_ops, + .pad = &imx334_pad_ops, +}; + +/** + * imx334_power_on() - Sensor power on sequence + * @dev: pointer to i2c device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_power_on(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx334 *imx334 = to_imx334(sd); + int ret; + + gpiod_set_value_cansleep(imx334->reset_gpio, 1); + + ret = clk_prepare_enable(imx334->inclk); + if (ret) { + dev_err(imx334->dev, "fail to enable inclk"); + goto error_reset; + } + + usleep_range(18000, 20000); + + return 0; + +error_reset: + gpiod_set_value_cansleep(imx334->reset_gpio, 0); + + return ret; +} + +/** + * imx334_power_off() - Sensor power off sequence + * @dev: pointer to i2c device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_power_off(struct device *dev) +{ + struct v4l2_subdev *sd = dev_get_drvdata(dev); + struct imx334 *imx334 = to_imx334(sd); + + gpiod_set_value_cansleep(imx334->reset_gpio, 0); + + clk_disable_unprepare(imx334->inclk); + + return 0; +} + +/** + * imx334_init_controls() - Initialize sensor subdevice controls + * @imx334: pointer to imx334 device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_init_controls(struct imx334 *imx334) +{ + struct v4l2_ctrl_handler *ctrl_hdlr = &imx334->ctrl_handler; + const struct imx334_mode *mode = imx334->cur_mode; + u32 lpfr; + int ret; + + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 6); + if (ret) + return ret; + + /* Serialize controls with sensor device */ + ctrl_hdlr->lock = &imx334->mutex; + + /* Initialize exposure and gain */ + lpfr = mode->vblank + mode->height; + imx334->exp_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_EXPOSURE, + IMX334_EXPOSURE_MIN, + lpfr - IMX334_EXPOSURE_OFFSET, + IMX334_EXPOSURE_STEP, + IMX334_EXPOSURE_DEFAULT); + + imx334->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, + IMX334_AGAIN_MIN, + IMX334_AGAIN_MAX, + IMX334_AGAIN_STEP, + IMX334_AGAIN_DEFAULT); + + v4l2_ctrl_cluster(2, &imx334->exp_ctrl); + + imx334->vblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_VBLANK, + mode->vblank_min, + mode->vblank_max, + 1, mode->vblank); + + /* Read only controls */ + imx334->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_PIXEL_RATE, + mode->pclk, mode->pclk, + 1, mode->pclk); + + imx334->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq) - + 1, + mode->link_freq_idx, + link_freq); + if (imx334->link_freq_ctrl) + imx334->link_freq_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + imx334->hblank_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, + &imx334_ctrl_ops, + V4L2_CID_HBLANK, + IMX334_REG_MIN, + IMX334_REG_MAX, + 1, mode->hblank); + if (imx334->hblank_ctrl) + imx334->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + if (ctrl_hdlr->error) { + dev_err(imx334->dev, "control init failed: %d", + ctrl_hdlr->error); + v4l2_ctrl_handler_free(ctrl_hdlr); + return ctrl_hdlr->error; + } + + imx334->sd.ctrl_handler = ctrl_hdlr; + + return 0; +} + +/** + * imx334_probe() - I2C client device binding + * @client: pointer to i2c client device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_probe(struct i2c_client *client) +{ + struct imx334 *imx334; + int ret; + + imx334 = devm_kzalloc(&client->dev, sizeof(*imx334), GFP_KERNEL); + if (!imx334) + return -ENOMEM; + + imx334->dev = &client->dev; + + /* Initialize subdev */ + v4l2_i2c_subdev_init(&imx334->sd, client, &imx334_subdev_ops); + + ret = imx334_parse_hw_config(imx334); + if (ret) { + dev_err(imx334->dev, "HW configuration is not supported"); + return ret; + } + + mutex_init(&imx334->mutex); + + ret = imx334_power_on(imx334->dev); + if (ret) { + dev_err(imx334->dev, "failed to power-on the sensor"); + goto error_mutex_destroy; + } + + /* Check module identity */ + ret = imx334_detect(imx334); + if (ret) { + dev_err(imx334->dev, "failed to find sensor: %d", ret); + goto error_power_off; + } + + /* Set default mode to max resolution */ + imx334->cur_mode = &supported_mode; + imx334->vblank = imx334->cur_mode->vblank; + + ret = imx334_init_controls(imx334); + if (ret) { + dev_err(imx334->dev, "failed to init controls: %d", ret); + goto error_power_off; + } + + /* Initialize subdev */ + imx334->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + imx334->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + /* Initialize source pad */ + imx334->pad.flags = MEDIA_PAD_FL_SOURCE; + ret = media_entity_pads_init(&imx334->sd.entity, 1, &imx334->pad); + if (ret) { + dev_err(imx334->dev, "failed to init entity pads: %d", ret); + goto error_handler_free; + } + + ret = v4l2_async_register_subdev_sensor_common(&imx334->sd); + if (ret < 0) { + dev_err(imx334->dev, + "failed to register async subdev: %d", ret); + goto error_media_entity; + } + + pm_runtime_set_active(imx334->dev); + pm_runtime_enable(imx334->dev); + pm_runtime_idle(imx334->dev); + + return 0; + +error_media_entity: + media_entity_cleanup(&imx334->sd.entity); +error_handler_free: + v4l2_ctrl_handler_free(imx334->sd.ctrl_handler); +error_power_off: + imx334_power_off(imx334->dev); +error_mutex_destroy: + mutex_destroy(&imx334->mutex); + + return ret; +} + +/** + * imx334_remove() - I2C client device unbinding + * @client: pointer to I2C client device + * + * Return: 0 if successful, error code otherwise. + */ +static int imx334_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx334 *imx334 = to_imx334(sd); + + v4l2_async_unregister_subdev(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(sd->ctrl_handler); + + pm_runtime_disable(&client->dev); + pm_runtime_suspended(&client->dev); + + mutex_destroy(&imx334->mutex); + + return 0; +} + +static const struct dev_pm_ops imx334_pm_ops = { + SET_RUNTIME_PM_OPS(imx334_power_off, imx334_power_on, NULL) +}; + +static const struct of_device_id imx334_of_match[] = { + { .compatible = "sony,imx334" }, + { } +}; + +MODULE_DEVICE_TABLE(of, imx334_of_match); + +static struct i2c_driver imx334_driver = { + .probe_new = imx334_probe, + .remove = imx334_remove, + .driver = { + .name = "imx334", + .pm = &imx334_pm_ops, + .of_match_table = imx334_of_match, + }, +}; + +module_i2c_driver(imx334_driver); + +MODULE_DESCRIPTION("Sony imx334 sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/max9271.c b/drivers/media/i2c/max9271.c index c247db569bab..c495582dcff6 100644 --- a/drivers/media/i2c/max9271.c +++ b/drivers/media/i2c/max9271.c @@ -18,6 +18,7 @@ #include <linux/delay.h> #include <linux/i2c.h> +#include <linux/module.h> #include "max9271.h" @@ -339,3 +340,7 @@ int max9271_set_translation(struct max9271_device *dev, u8 source, u8 dest) return 0; } EXPORT_SYMBOL_GPL(max9271_set_translation); + +MODULE_DESCRIPTION("Maxim MAX9271 GMSL Serializer"); +MODULE_AUTHOR("Jacopo Mondi"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c index c82c1493e099..6fd4d59fcc72 100644 --- a/drivers/media/i2c/max9286.c +++ b/drivers/media/i2c/max9286.c @@ -163,6 +163,8 @@ struct max9286_priv { unsigned int mux_channel; bool mux_open; + u32 reverse_channel_mv; + struct v4l2_ctrl_handler ctrls; struct v4l2_ctrl *pixelrate; @@ -336,6 +338,31 @@ static void max9286_configure_i2c(struct max9286_priv *priv, bool localack) usleep_range(3000, 5000); } +static void max9286_reverse_channel_setup(struct max9286_priv *priv, + unsigned int chan_amplitude) +{ + /* Reverse channel transmission time: default to 1. */ + u8 chan_config = MAX9286_REV_TRF(1); + + /* + * Reverse channel setup. + * + * - Enable custom reverse channel configuration (through register 0x3f) + * and set the first pulse length to 35 clock cycles. + * - Adjust reverse channel amplitude: values > 130 are programmed + * using the additional +100mV REV_AMP_X boost flag + */ + max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35)); + + if (chan_amplitude > 100) { + /* It is not possible to express values (100 < x < 130) */ + chan_amplitude = max(30U, chan_amplitude - 100); + chan_config |= MAX9286_REV_AMP_X; + } + max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude)); + usleep_range(2000, 2500); +} + /* * max9286_check_video_links() - Make sure video links are detected and locked * @@ -531,10 +558,14 @@ static int max9286_notify_bound(struct v4l2_async_notifier *notifier, * All enabled sources have probed and enabled their reverse control * channels: * + * - Increase the reverse channel amplitude to compensate for the + * remote ends high threshold, if not done already * - Verify all configuration links are properly detected * - Disable auto-ack as communication on the control channel are now * stable. */ + if (priv->reverse_channel_mv < 170) + max9286_reverse_channel_setup(priv, 170); max9286_check_config_link(priv, priv->source_mask); /* @@ -576,19 +607,19 @@ static int max9286_v4l2_notifier_register(struct max9286_priv *priv) for_each_source(priv, source) { unsigned int i = to_index(priv, source); - struct v4l2_async_subdev *asd; + struct max9286_asd *mas; - asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, + mas = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, source->fwnode, - sizeof(*asd)); - if (IS_ERR(asd)) { + struct max9286_asd); + if (IS_ERR(mas)) { dev_err(dev, "Failed to add subdev for source %u: %ld", - i, PTR_ERR(asd)); + i, PTR_ERR(mas)); v4l2_async_notifier_cleanup(&priv->notifier); - return PTR_ERR(asd); + return PTR_ERR(mas); } - to_max9286_asd(asd)->source = source; + mas->source = source; } priv->notifier.ops = &max9286_notify_ops; @@ -941,19 +972,7 @@ static int max9286_setup(struct max9286_priv *priv) * only. This should be disabled after the mux is initialised. */ max9286_configure_i2c(priv, true); - - /* - * Reverse channel setup. - * - * - Enable custom reverse channel configuration (through register 0x3f) - * and set the first pulse length to 35 clock cycles. - * - Increase the reverse channel amplitude to 170mV to accommodate the - * high threshold enabled by the serializer driver. - */ - max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35)); - max9286_write(priv, 0x3b, MAX9286_REV_TRF(1) | MAX9286_REV_AMP(70) | - MAX9286_REV_AMP_X); - usleep_range(2000, 2500); + max9286_reverse_channel_setup(priv, priv->reverse_channel_mv); /* * Enable GMSL links, mask unused ones and autodetect link @@ -1117,6 +1136,7 @@ static int max9286_parse_dt(struct max9286_priv *priv) struct device_node *i2c_mux; struct device_node *node = NULL; unsigned int i2c_mux_mask = 0; + u32 reverse_channel_microvolt; /* Balance the of_node_put() performed by of_find_node_by_name(). */ of_node_get(dev->of_node); @@ -1207,6 +1227,20 @@ static int max9286_parse_dt(struct max9286_priv *priv) } of_node_put(node); + /* + * Parse the initial value of the reverse channel amplitude from + * the firmware interface and convert it to millivolts. + * + * Default it to 170mV for backward compatibility with DTBs that do not + * provide the property. + */ + if (of_property_read_u32(dev->of_node, + "maxim,reverse-channel-microvolt", + &reverse_channel_microvolt)) + priv->reverse_channel_mv = 170; + else + priv->reverse_channel_mv = reverse_channel_microvolt / 1000U; + priv->route_mask = priv->source_mask; return 0; diff --git a/drivers/media/i2c/mt9m111.c b/drivers/media/i2c/mt9m111.c index 69697386ffcd..0e11734f75aa 100644 --- a/drivers/media/i2c/mt9m111.c +++ b/drivers/media/i2c/mt9m111.c @@ -4,6 +4,7 @@ * * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> */ +#include <linux/clk.h> #include <linux/videodev2.h> #include <linux/slab.h> #include <linux/i2c.h> @@ -16,7 +17,6 @@ #include <linux/property.h> #include <media/v4l2-async.h> -#include <media/v4l2-clk.h> #include <media/v4l2-common.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> @@ -232,7 +232,7 @@ struct mt9m111 { struct v4l2_ctrl *gain; struct mt9m111_context *ctx; struct v4l2_rect rect; /* cropping rectangle */ - struct v4l2_clk *clk; + struct clk *clk; unsigned int width; /* output */ unsigned int height; /* sizes */ struct v4l2_fract frame_interval; @@ -977,7 +977,7 @@ static int mt9m111_power_on(struct mt9m111 *mt9m111) struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev); int ret; - ret = v4l2_clk_enable(mt9m111->clk); + ret = clk_prepare_enable(mt9m111->clk); if (ret < 0) return ret; @@ -995,7 +995,7 @@ out_regulator_disable: regulator_disable(mt9m111->regulator); out_clk_disable: - v4l2_clk_disable(mt9m111->clk); + clk_disable_unprepare(mt9m111->clk); dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret); @@ -1006,7 +1006,7 @@ static void mt9m111_power_off(struct mt9m111 *mt9m111) { mt9m111_suspend(mt9m111); regulator_disable(mt9m111->regulator); - v4l2_clk_disable(mt9m111->clk); + clk_disable_unprepare(mt9m111->clk); } static int mt9m111_s_power(struct v4l2_subdev *sd, int on) @@ -1266,7 +1266,7 @@ static int mt9m111_probe(struct i2c_client *client) return ret; } - mt9m111->clk = v4l2_clk_get(&client->dev, "mclk"); + mt9m111->clk = devm_clk_get(&client->dev, "mclk"); if (IS_ERR(mt9m111->clk)) return PTR_ERR(mt9m111->clk); @@ -1311,7 +1311,7 @@ static int mt9m111_probe(struct i2c_client *client) mt9m111->subdev.ctrl_handler = &mt9m111->hdl; if (mt9m111->hdl.error) { ret = mt9m111->hdl.error; - goto out_clkput; + return ret; } #ifdef CONFIG_MEDIA_CONTROLLER @@ -1354,8 +1354,6 @@ out_entityclean: out_hdlfree: #endif v4l2_ctrl_handler_free(&mt9m111->hdl); -out_clkput: - v4l2_clk_put(mt9m111->clk); return ret; } @@ -1366,7 +1364,6 @@ static int mt9m111_remove(struct i2c_client *client) v4l2_async_unregister_subdev(&mt9m111->subdev); media_entity_cleanup(&mt9m111->subdev.entity); - v4l2_clk_put(mt9m111->clk); v4l2_ctrl_handler_free(&mt9m111->hdl); return 0; diff --git a/drivers/media/i2c/mt9v111.c b/drivers/media/i2c/mt9v111.c index 61ae6a0d5679..97c7527b74ed 100644 --- a/drivers/media/i2c/mt9v111.c +++ b/drivers/media/i2c/mt9v111.c @@ -1253,12 +1253,6 @@ static int mt9v111_remove(struct i2c_client *client) mutex_destroy(&mt9v111->pwr_mutex); mutex_destroy(&mt9v111->stream_mutex); - devm_gpiod_put(mt9v111->dev, mt9v111->oe); - devm_gpiod_put(mt9v111->dev, mt9v111->standby); - devm_gpiod_put(mt9v111->dev, mt9v111->reset); - - devm_clk_put(mt9v111->dev, mt9v111->clk); - return 0; } diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c index 8683ffd3287a..60b4bc645334 100644 --- a/drivers/media/i2c/ov02a10.c +++ b/drivers/media/i2c/ov02a10.c @@ -388,7 +388,7 @@ static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10) if (ret < 0) return ret; - chip_id = le16_to_cpu(ret); + chip_id = le16_to_cpu((__force __le16)ret); if ((chip_id & OV02A10_ID_MASK) != OV02A10_ID) { dev_err(&client->dev, "unexpected sensor id(0x%04x)\n", chip_id); diff --git a/drivers/media/i2c/ov5647.c b/drivers/media/i2c/ov5647.c index e7d2e5b4ad4b..1cefa15729ce 100644 --- a/drivers/media/i2c/ov5647.c +++ b/drivers/media/i2c/ov5647.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * A V4L2 driver for OmniVision OV5647 cameras. * @@ -8,119 +9,316 @@ * Copyright (C) 2006-7 Jonathan Corbet <corbet@lwn.net> * * Copyright (C) 2016, Synopsys, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed .as is. WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/clk.h> #include <linux/delay.h> +#include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of_graph.h> +#include <linux/pm_runtime.h> #include <linux/slab.h> #include <linux/videodev2.h> +#include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> +#include <media/v4l2-event.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-image-sizes.h> #include <media/v4l2-mediabus.h> -#define SENSOR_NAME "ov5647" +/* + * From the datasheet, "20ms after PWDN goes low or 20ms after RESETB goes + * high if reset is inserted after PWDN goes high, host can access sensor's + * SCCB to initialize sensor." + */ +#define PWDN_ACTIVE_DELAY_MS 20 #define MIPI_CTRL00_CLOCK_LANE_GATE BIT(5) +#define MIPI_CTRL00_LINE_SYNC_ENABLE BIT(4) #define MIPI_CTRL00_BUS_IDLE BIT(2) #define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0) #define OV5647_SW_STANDBY 0x0100 #define OV5647_SW_RESET 0x0103 -#define OV5647_REG_CHIPID_H 0x300A -#define OV5647_REG_CHIPID_L 0x300B -#define OV5640_REG_PAD_OUT 0x300D +#define OV5647_REG_CHIPID_H 0x300a +#define OV5647_REG_CHIPID_L 0x300b +#define OV5640_REG_PAD_OUT 0x300d +#define OV5647_REG_EXP_HI 0x3500 +#define OV5647_REG_EXP_MID 0x3501 +#define OV5647_REG_EXP_LO 0x3502 +#define OV5647_REG_AEC_AGC 0x3503 +#define OV5647_REG_GAIN_HI 0x350a +#define OV5647_REG_GAIN_LO 0x350b +#define OV5647_REG_VTS_HI 0x380e +#define OV5647_REG_VTS_LO 0x380f #define OV5647_REG_FRAME_OFF_NUMBER 0x4202 #define OV5647_REG_MIPI_CTRL00 0x4800 #define OV5647_REG_MIPI_CTRL14 0x4814 +#define OV5647_REG_AWB 0x5001 #define REG_TERM 0xfffe #define VAL_TERM 0xfe #define REG_DLY 0xffff -#define OV5647_ROW_START 0x01 -#define OV5647_ROW_START_MIN 0 -#define OV5647_ROW_START_MAX 2004 -#define OV5647_ROW_START_DEF 54 +/* OV5647 native and active pixel array size */ +#define OV5647_NATIVE_WIDTH 2624U +#define OV5647_NATIVE_HEIGHT 1956U -#define OV5647_COLUMN_START 0x02 -#define OV5647_COLUMN_START_MIN 0 -#define OV5647_COLUMN_START_MAX 2750 -#define OV5647_COLUMN_START_DEF 16 +#define OV5647_PIXEL_ARRAY_LEFT 16U +#define OV5647_PIXEL_ARRAY_TOP 16U +#define OV5647_PIXEL_ARRAY_WIDTH 2592U +#define OV5647_PIXEL_ARRAY_HEIGHT 1944U -#define OV5647_WINDOW_HEIGHT 0x03 -#define OV5647_WINDOW_HEIGHT_MIN 2 -#define OV5647_WINDOW_HEIGHT_MAX 2006 -#define OV5647_WINDOW_HEIGHT_DEF 1944 +#define OV5647_VBLANK_MIN 4 +#define OV5647_VTS_MAX 32767 -#define OV5647_WINDOW_WIDTH 0x04 -#define OV5647_WINDOW_WIDTH_MIN 2 -#define OV5647_WINDOW_WIDTH_MAX 2752 -#define OV5647_WINDOW_WIDTH_DEF 2592 +#define OV5647_EXPOSURE_MIN 4 +#define OV5647_EXPOSURE_STEP 1 +#define OV5647_EXPOSURE_DEFAULT 1000 +#define OV5647_EXPOSURE_MAX 65535 struct regval_list { u16 addr; u8 data; }; +struct ov5647_mode { + struct v4l2_mbus_framefmt format; + struct v4l2_rect crop; + u64 pixel_rate; + int hts; + int vts; + const struct regval_list *reg_list; + unsigned int num_regs; +}; + struct ov5647 { struct v4l2_subdev sd; struct media_pad pad; struct mutex lock; - struct v4l2_mbus_framefmt format; - unsigned int width; - unsigned int height; - int power_count; struct clk *xclk; + struct gpio_desc *pwdn; + bool clock_ncont; + struct v4l2_ctrl_handler ctrls; + const struct ov5647_mode *mode; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *exposure; + bool streaming; }; -static inline struct ov5647 *to_state(struct v4l2_subdev *sd) +static inline struct ov5647 *to_sensor(struct v4l2_subdev *sd) { return container_of(sd, struct ov5647, sd); } -static struct regval_list sensor_oe_disable_regs[] = { +static const struct regval_list sensor_oe_disable_regs[] = { {0x3000, 0x00}, {0x3001, 0x00}, {0x3002, 0x00}, }; -static struct regval_list sensor_oe_enable_regs[] = { +static const struct regval_list sensor_oe_enable_regs[] = { {0x3000, 0x0f}, {0x3001, 0xff}, {0x3002, 0xe4}, }; -static struct regval_list ov5647_640x480[] = { +static struct regval_list ov5647_2592x1944_10bpp[] = { {0x0100, 0x00}, {0x0103, 0x01}, - {0x3034, 0x08}, + {0x3034, 0x1a}, {0x3035, 0x21}, - {0x3036, 0x46}, + {0x3036, 0x69}, + {0x303c, 0x11}, + {0x3106, 0xf5}, + {0x3821, 0x06}, + {0x3820, 0x00}, + {0x3827, 0xec}, + {0x370c, 0x03}, + {0x3612, 0x5b}, + {0x3618, 0x04}, + {0x5000, 0x06}, + {0x5002, 0x41}, + {0x5003, 0x08}, + {0x5a00, 0x08}, + {0x3000, 0x00}, + {0x3001, 0x00}, + {0x3002, 0x00}, + {0x3016, 0x08}, + {0x3017, 0xe0}, + {0x3018, 0x44}, + {0x301c, 0xf8}, + {0x301d, 0xf0}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3c01, 0x80}, + {0x3b07, 0x0c}, + {0x380c, 0x0b}, + {0x380d, 0x1c}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x3708, 0x64}, + {0x3709, 0x12}, + {0x3808, 0x0a}, + {0x3809, 0x20}, + {0x380a, 0x07}, + {0x380b, 0x98}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3811, 0x10}, + {0x3813, 0x06}, + {0x3630, 0x2e}, + {0x3632, 0xe2}, + {0x3633, 0x23}, + {0x3634, 0x44}, + {0x3636, 0x06}, + {0x3620, 0x64}, + {0x3621, 0xe0}, + {0x3600, 0x37}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x3731, 0x02}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3f05, 0x02}, + {0x3f06, 0x10}, + {0x3f01, 0x0a}, + {0x3a08, 0x01}, + {0x3a09, 0x28}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0d, 0x08}, + {0x3a0e, 0x06}, + {0x3a0f, 0x58}, + {0x3a10, 0x50}, + {0x3a1b, 0x58}, + {0x3a1e, 0x50}, + {0x3a11, 0x60}, + {0x3a1f, 0x28}, + {0x4001, 0x02}, + {0x4004, 0x04}, + {0x4000, 0x09}, + {0x4837, 0x19}, + {0x4800, 0x24}, + {0x3503, 0x03}, + {0x0100, 0x01}, +}; + +static struct regval_list ov5647_1080p30_10bpp[] = { + {0x0100, 0x00}, + {0x0103, 0x01}, + {0x3034, 0x1a}, + {0x3035, 0x21}, + {0x3036, 0x62}, + {0x303c, 0x11}, + {0x3106, 0xf5}, + {0x3821, 0x06}, + {0x3820, 0x00}, + {0x3827, 0xec}, + {0x370c, 0x03}, + {0x3612, 0x5b}, + {0x3618, 0x04}, + {0x5000, 0x06}, + {0x5002, 0x41}, + {0x5003, 0x08}, + {0x5a00, 0x08}, + {0x3000, 0x00}, + {0x3001, 0x00}, + {0x3002, 0x00}, + {0x3016, 0x08}, + {0x3017, 0xe0}, + {0x3018, 0x44}, + {0x301c, 0xf8}, + {0x301d, 0xf0}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3c01, 0x80}, + {0x3b07, 0x0c}, + {0x380c, 0x09}, + {0x380d, 0x70}, + {0x3814, 0x11}, + {0x3815, 0x11}, + {0x3708, 0x64}, + {0x3709, 0x12}, + {0x3808, 0x07}, + {0x3809, 0x80}, + {0x380a, 0x04}, + {0x380b, 0x38}, + {0x3800, 0x01}, + {0x3801, 0x5c}, + {0x3802, 0x01}, + {0x3803, 0xb2}, + {0x3804, 0x08}, + {0x3805, 0xe3}, + {0x3806, 0x05}, + {0x3807, 0xf1}, + {0x3811, 0x04}, + {0x3813, 0x02}, + {0x3630, 0x2e}, + {0x3632, 0xe2}, + {0x3633, 0x23}, + {0x3634, 0x44}, + {0x3636, 0x06}, + {0x3620, 0x64}, + {0x3621, 0xe0}, + {0x3600, 0x37}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x3731, 0x02}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3f05, 0x02}, + {0x3f06, 0x10}, + {0x3f01, 0x0a}, + {0x3a08, 0x01}, + {0x3a09, 0x4b}, + {0x3a0a, 0x01}, + {0x3a0b, 0x13}, + {0x3a0d, 0x04}, + {0x3a0e, 0x03}, + {0x3a0f, 0x58}, + {0x3a10, 0x50}, + {0x3a1b, 0x58}, + {0x3a1e, 0x50}, + {0x3a11, 0x60}, + {0x3a1f, 0x28}, + {0x4001, 0x02}, + {0x4004, 0x04}, + {0x4000, 0x09}, + {0x4837, 0x19}, + {0x4800, 0x34}, + {0x3503, 0x03}, + {0x0100, 0x01}, +}; + +static struct regval_list ov5647_2x2binned_10bpp[] = { + {0x0100, 0x00}, + {0x0103, 0x01}, + {0x3034, 0x1a}, + {0x3035, 0x21}, + {0x3036, 0x62}, {0x303c, 0x11}, {0x3106, 0xf5}, - {0x3821, 0x07}, - {0x3820, 0x41}, {0x3827, 0xec}, - {0x370c, 0x0f}, + {0x370c, 0x03}, {0x3612, 0x59}, {0x3618, 0x00}, {0x5000, 0x06}, - {0x5001, 0x01}, {0x5002, 0x41}, {0x5003, 0x08}, {0x5a00, 0x08}, @@ -136,32 +334,115 @@ static struct regval_list ov5647_640x480[] = { {0x3a19, 0xf8}, {0x3c01, 0x80}, {0x3b07, 0x0c}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x00}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0xa3}, + {0x3808, 0x05}, + {0x3809, 0x10}, + {0x380a, 0x03}, + {0x380b, 0xcc}, {0x380c, 0x07}, {0x380d, 0x68}, - {0x380e, 0x03}, - {0x380f, 0xd8}, + {0x3811, 0x0c}, + {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, + {0x3630, 0x2e}, + {0x3632, 0xe2}, + {0x3633, 0x23}, + {0x3634, 0x44}, + {0x3636, 0x06}, + {0x3620, 0x64}, + {0x3621, 0xe0}, + {0x3600, 0x37}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x3731, 0x02}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3f05, 0x02}, + {0x3f06, 0x10}, + {0x3f01, 0x0a}, + {0x3a08, 0x01}, + {0x3a09, 0x28}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0d, 0x08}, + {0x3a0e, 0x06}, + {0x3a0f, 0x58}, + {0x3a10, 0x50}, + {0x3a1b, 0x58}, + {0x3a1e, 0x50}, + {0x3a11, 0x60}, + {0x3a1f, 0x28}, + {0x4001, 0x02}, + {0x4004, 0x04}, + {0x4000, 0x09}, + {0x4837, 0x16}, + {0x4800, 0x24}, + {0x3503, 0x03}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x350a, 0x00}, + {0x350b, 0x10}, + {0x3500, 0x00}, + {0x3501, 0x1a}, + {0x3502, 0xf0}, + {0x3212, 0xa0}, + {0x0100, 0x01}, +}; + +static struct regval_list ov5647_640x480_10bpp[] = { + {0x0100, 0x00}, + {0x0103, 0x01}, + {0x3035, 0x11}, + {0x3036, 0x46}, + {0x303c, 0x11}, + {0x3821, 0x07}, + {0x3820, 0x41}, + {0x370c, 0x03}, + {0x3612, 0x59}, + {0x3618, 0x00}, + {0x5000, 0x06}, + {0x5003, 0x08}, + {0x5a00, 0x08}, + {0x3000, 0xff}, + {0x3001, 0xff}, + {0x3002, 0xff}, + {0x301d, 0xf0}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3c01, 0x80}, + {0x3b07, 0x0c}, + {0x380c, 0x07}, + {0x380d, 0x3c}, + {0x3814, 0x35}, + {0x3815, 0x35}, {0x3708, 0x64}, {0x3709, 0x52}, {0x3808, 0x02}, {0x3809, 0x80}, {0x380a, 0x01}, - {0x380b, 0xE0}, - {0x3801, 0x00}, + {0x380b, 0xe0}, + {0x3800, 0x00}, + {0x3801, 0x10}, {0x3802, 0x00}, {0x3803, 0x00}, {0x3804, 0x0a}, - {0x3805, 0x3f}, + {0x3805, 0x2f}, {0x3806, 0x07}, - {0x3807, 0xa1}, - {0x3811, 0x08}, - {0x3813, 0x02}, + {0x3807, 0x9f}, {0x3630, 0x2e}, {0x3632, 0xe2}, {0x3633, 0x23}, {0x3634, 0x44}, - {0x3636, 0x06}, {0x3620, 0x64}, {0x3621, 0xe0}, {0x3600, 0x37}, @@ -176,11 +457,11 @@ static struct regval_list ov5647_640x480[] = { {0x3f06, 0x10}, {0x3f01, 0x0a}, {0x3a08, 0x01}, - {0x3a09, 0x27}, + {0x3a09, 0x2e}, {0x3a0a, 0x00}, - {0x3a0b, 0xf6}, - {0x3a0d, 0x04}, - {0x3a0e, 0x03}, + {0x3a0b, 0xfb}, + {0x3a0d, 0x02}, + {0x3a0e, 0x01}, {0x3a0f, 0x58}, {0x3a10, 0x50}, {0x3a1b, 0x58}, @@ -190,31 +471,152 @@ static struct regval_list ov5647_640x480[] = { {0x4001, 0x02}, {0x4004, 0x02}, {0x4000, 0x09}, - {0x4837, 0x24}, - {0x4050, 0x6e}, - {0x4051, 0x8f}, + {0x3000, 0x00}, + {0x3001, 0x00}, + {0x3002, 0x00}, + {0x3017, 0xe0}, + {0x301c, 0xfc}, + {0x3636, 0x06}, + {0x3016, 0x08}, + {0x3827, 0xec}, + {0x3018, 0x44}, + {0x3035, 0x21}, + {0x3106, 0xf5}, + {0x3034, 0x1a}, + {0x301c, 0xf8}, + {0x4800, 0x34}, + {0x3503, 0x03}, {0x0100, 0x01}, }; -static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val) +static const struct ov5647_mode ov5647_modes[] = { + /* 2592x1944 full resolution full FOV 10-bit mode. */ + { + .format = { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .colorspace = V4L2_COLORSPACE_SRGB, + .field = V4L2_FIELD_NONE, + .width = 2592, + .height = 1944 + }, + .crop = { + .left = OV5647_PIXEL_ARRAY_LEFT, + .top = OV5647_PIXEL_ARRAY_TOP, + .width = 2592, + .height = 1944 + }, + .pixel_rate = 87500000, + .hts = 2844, + .vts = 0x7b0, + .reg_list = ov5647_2592x1944_10bpp, + .num_regs = ARRAY_SIZE(ov5647_2592x1944_10bpp) + }, + /* 1080p30 10-bit mode. Full resolution centre-cropped down to 1080p. */ + { + .format = { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .colorspace = V4L2_COLORSPACE_SRGB, + .field = V4L2_FIELD_NONE, + .width = 1920, + .height = 1080 + }, + .crop = { + .left = 348 + OV5647_PIXEL_ARRAY_LEFT, + .top = 434 + OV5647_PIXEL_ARRAY_TOP, + .width = 1928, + .height = 1080, + }, + .pixel_rate = 81666700, + .hts = 2416, + .vts = 0x450, + .reg_list = ov5647_1080p30_10bpp, + .num_regs = ARRAY_SIZE(ov5647_1080p30_10bpp) + }, + /* 2x2 binned full FOV 10-bit mode. */ + { + .format = { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .colorspace = V4L2_COLORSPACE_SRGB, + .field = V4L2_FIELD_NONE, + .width = 1296, + .height = 972 + }, + .crop = { + .left = OV5647_PIXEL_ARRAY_LEFT, + .top = OV5647_PIXEL_ARRAY_TOP, + .width = 2592, + .height = 1944, + }, + .pixel_rate = 81666700, + .hts = 1896, + .vts = 0x59b, + .reg_list = ov5647_2x2binned_10bpp, + .num_regs = ARRAY_SIZE(ov5647_2x2binned_10bpp) + }, + /* 10-bit VGA full FOV 60fps. 2x2 binned and subsampled down to VGA. */ + { + .format = { + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .colorspace = V4L2_COLORSPACE_SRGB, + .field = V4L2_FIELD_NONE, + .width = 640, + .height = 480 + }, + .crop = { + .left = 16 + OV5647_PIXEL_ARRAY_LEFT, + .top = OV5647_PIXEL_ARRAY_TOP, + .width = 2560, + .height = 1920, + }, + .pixel_rate = 55000000, + .hts = 1852, + .vts = 0x1f8, + .reg_list = ov5647_640x480_10bpp, + .num_regs = ARRAY_SIZE(ov5647_640x480_10bpp) + }, +}; + +/* Default sensor mode is 2x2 binned 640x480 SBGGR10_1X10. */ +#define OV5647_DEFAULT_MODE (&ov5647_modes[3]) +#define OV5647_DEFAULT_FORMAT (ov5647_modes[3].format) + +static int ov5647_write16(struct v4l2_subdev *sd, u16 reg, u16 val) { + unsigned char data[4] = { reg >> 8, reg & 0xff, val >> 8, val & 0xff}; + struct i2c_client *client = v4l2_get_subdevdata(sd); int ret; + + ret = i2c_master_send(client, data, 4); + if (ret < 0) { + dev_dbg(&client->dev, "%s: i2c write error, reg: %x\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val) +{ unsigned char data[3] = { reg >> 8, reg & 0xff, val}; struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; ret = i2c_master_send(client, data, 3); - if (ret < 0) + if (ret < 0) { dev_dbg(&client->dev, "%s: i2c write error, reg: %x\n", __func__, reg); + return ret; + } - return ret; + return 0; } static int ov5647_read(struct v4l2_subdev *sd, u16 reg, u8 *val) { - int ret; unsigned char data_w[2] = { reg >> 8, reg & 0xff }; struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; ret = i2c_master_send(client, data_w, 2); if (ret < 0) { @@ -224,15 +626,17 @@ static int ov5647_read(struct v4l2_subdev *sd, u16 reg, u8 *val) } ret = i2c_master_recv(client, val, 1); - if (ret < 0) + if (ret < 0) { dev_dbg(&client->dev, "%s: i2c read error, reg: %x\n", __func__, reg); + return ret; + } - return ret; + return 0; } static int ov5647_write_array(struct v4l2_subdev *sd, - struct regval_list *regs, int array_size) + const struct regval_list *regs, int array_size) { int i, ret; @@ -255,161 +659,174 @@ static int ov5647_set_virtual_channel(struct v4l2_subdev *sd, int channel) return ret; channel_id &= ~(3 << 6); - return ov5647_write(sd, OV5647_REG_MIPI_CTRL14, channel_id | (channel << 6)); + + return ov5647_write(sd, OV5647_REG_MIPI_CTRL14, + channel_id | (channel << 6)); } -static int ov5647_stream_on(struct v4l2_subdev *sd) +static int ov5647_set_mode(struct v4l2_subdev *sd) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5647 *sensor = to_sensor(sd); + u8 resetval, rdval; int ret; - ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, MIPI_CTRL00_BUS_IDLE); + ret = ov5647_read(sd, OV5647_SW_STANDBY, &rdval); + if (ret < 0) + return ret; + + ret = ov5647_write_array(sd, sensor->mode->reg_list, + sensor->mode->num_regs); + if (ret < 0) { + dev_err(&client->dev, "write sensor default regs error\n"); + return ret; + } + + ret = ov5647_set_virtual_channel(sd, 0); if (ret < 0) return ret; - ret = ov5647_write(sd, OV5647_REG_FRAME_OFF_NUMBER, 0x00); + ret = ov5647_read(sd, OV5647_SW_STANDBY, &resetval); if (ret < 0) return ret; - return ov5647_write(sd, OV5640_REG_PAD_OUT, 0x00); + if (!(resetval & 0x01)) { + dev_err(&client->dev, "Device was in SW standby"); + ret = ov5647_write(sd, OV5647_SW_STANDBY, 0x01); + if (ret < 0) + return ret; + } + + return 0; } -static int ov5647_stream_off(struct v4l2_subdev *sd) +static int ov5647_stream_on(struct v4l2_subdev *sd) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5647 *sensor = to_sensor(sd); + u8 val = MIPI_CTRL00_BUS_IDLE; int ret; - ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, MIPI_CTRL00_CLOCK_LANE_GATE - | MIPI_CTRL00_BUS_IDLE | MIPI_CTRL00_CLOCK_LANE_DISABLE); - if (ret < 0) + ret = ov5647_set_mode(sd); + if (ret) { + dev_err(&client->dev, "Failed to program sensor mode: %d\n", ret); return ret; + } - ret = ov5647_write(sd, OV5647_REG_FRAME_OFF_NUMBER, 0x0f); - if (ret < 0) + /* Apply customized values from user when stream starts. */ + ret = __v4l2_ctrl_handler_setup(sd->ctrl_handler); + if (ret) return ret; - return ov5647_write(sd, OV5640_REG_PAD_OUT, 0x01); -} - -static int set_sw_standby(struct v4l2_subdev *sd, bool standby) -{ - int ret; - u8 rdval; + if (sensor->clock_ncont) + val |= MIPI_CTRL00_CLOCK_LANE_GATE | + MIPI_CTRL00_LINE_SYNC_ENABLE; - ret = ov5647_read(sd, OV5647_SW_STANDBY, &rdval); + ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, val); if (ret < 0) return ret; - if (standby) - rdval &= ~0x01; - else - rdval |= 0x01; + ret = ov5647_write(sd, OV5647_REG_FRAME_OFF_NUMBER, 0x00); + if (ret < 0) + return ret; - return ov5647_write(sd, OV5647_SW_STANDBY, rdval); + return ov5647_write(sd, OV5640_REG_PAD_OUT, 0x00); } -static int __sensor_init(struct v4l2_subdev *sd) +static int ov5647_stream_off(struct v4l2_subdev *sd) { int ret; - u8 resetval, rdval; - struct i2c_client *client = v4l2_get_subdevdata(sd); - ret = ov5647_read(sd, OV5647_SW_STANDBY, &rdval); + ret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, + MIPI_CTRL00_CLOCK_LANE_GATE | MIPI_CTRL00_BUS_IDLE | + MIPI_CTRL00_CLOCK_LANE_DISABLE); if (ret < 0) return ret; - ret = ov5647_write_array(sd, ov5647_640x480, - ARRAY_SIZE(ov5647_640x480)); - if (ret < 0) { - dev_err(&client->dev, "write sensor default regs error\n"); - return ret; - } - - ret = ov5647_set_virtual_channel(sd, 0); - if (ret < 0) - return ret; - - ret = ov5647_read(sd, OV5647_SW_STANDBY, &resetval); + ret = ov5647_write(sd, OV5647_REG_FRAME_OFF_NUMBER, 0x0f); if (ret < 0) return ret; - if (!(resetval & 0x01)) { - dev_err(&client->dev, "Device was in SW standby"); - ret = ov5647_write(sd, OV5647_SW_STANDBY, 0x01); - if (ret < 0) - return ret; - } - - /* - * stream off to make the clock lane into LP-11 state. - */ - return ov5647_stream_off(sd); + return ov5647_write(sd, OV5640_REG_PAD_OUT, 0x01); } -static int ov5647_sensor_power(struct v4l2_subdev *sd, int on) +static int ov5647_power_on(struct device *dev) { - int ret = 0; - struct ov5647 *ov5647 = to_state(sd); - struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5647 *sensor = dev_get_drvdata(dev); + int ret; - mutex_lock(&ov5647->lock); + dev_dbg(dev, "OV5647 power on\n"); - if (on && !ov5647->power_count) { - dev_dbg(&client->dev, "OV5647 power on\n"); + if (sensor->pwdn) { + gpiod_set_value_cansleep(sensor->pwdn, 0); + msleep(PWDN_ACTIVE_DELAY_MS); + } - ret = clk_prepare_enable(ov5647->xclk); - if (ret < 0) { - dev_err(&client->dev, "clk prepare enable failed\n"); - goto out; - } + ret = clk_prepare_enable(sensor->xclk); + if (ret < 0) { + dev_err(dev, "clk prepare enable failed\n"); + goto error_pwdn; + } - ret = ov5647_write_array(sd, sensor_oe_enable_regs, - ARRAY_SIZE(sensor_oe_enable_regs)); - if (ret < 0) { - clk_disable_unprepare(ov5647->xclk); - dev_err(&client->dev, - "write sensor_oe_enable_regs error\n"); - goto out; - } + ret = ov5647_write_array(&sensor->sd, sensor_oe_enable_regs, + ARRAY_SIZE(sensor_oe_enable_regs)); + if (ret < 0) { + dev_err(dev, "write sensor_oe_enable_regs error\n"); + goto error_clk_disable; + } - ret = __sensor_init(sd); - if (ret < 0) { - clk_disable_unprepare(ov5647->xclk); - dev_err(&client->dev, - "Camera not available, check Power\n"); - goto out; - } - } else if (!on && ov5647->power_count == 1) { - dev_dbg(&client->dev, "OV5647 power off\n"); + /* Stream off to coax lanes into LP-11 state. */ + ret = ov5647_stream_off(&sensor->sd); + if (ret < 0) { + dev_err(dev, "camera not available, check power\n"); + goto error_clk_disable; + } - ret = ov5647_write_array(sd, sensor_oe_disable_regs, - ARRAY_SIZE(sensor_oe_disable_regs)); + return 0; - if (ret < 0) - dev_dbg(&client->dev, "disable oe failed\n"); +error_clk_disable: + clk_disable_unprepare(sensor->xclk); +error_pwdn: + gpiod_set_value_cansleep(sensor->pwdn, 1); - ret = set_sw_standby(sd, true); + return ret; +} - if (ret < 0) - dev_dbg(&client->dev, "soft stby failed\n"); +static int ov5647_power_off(struct device *dev) +{ + struct ov5647 *sensor = dev_get_drvdata(dev); + u8 rdval; + int ret; - clk_disable_unprepare(ov5647->xclk); - } + dev_dbg(dev, "OV5647 power off\n"); - /* Update the power count. */ - ov5647->power_count += on ? 1 : -1; - WARN_ON(ov5647->power_count < 0); + ret = ov5647_write_array(&sensor->sd, sensor_oe_disable_regs, + ARRAY_SIZE(sensor_oe_disable_regs)); + if (ret < 0) + dev_dbg(dev, "disable oe failed\n"); -out: - mutex_unlock(&ov5647->lock); + /* Enter software standby */ + ret = ov5647_read(&sensor->sd, OV5647_SW_STANDBY, &rdval); + if (ret < 0) + dev_dbg(dev, "software standby failed\n"); - return ret; + rdval &= ~0x01; + ret = ov5647_write(&sensor->sd, OV5647_SW_STANDBY, rdval); + if (ret < 0) + dev_dbg(dev, "software standby failed\n"); + + clk_disable_unprepare(sensor->xclk); + gpiod_set_value_cansleep(sensor->pwdn, 1); + + return 0; } #ifdef CONFIG_VIDEO_ADV_DEBUG static int ov5647_sensor_get_register(struct v4l2_subdev *sd, - struct v4l2_dbg_register *reg) + struct v4l2_dbg_register *reg) { - u8 val; int ret; + u8 val; ret = ov5647_read(sd, reg->reg & 0xff, &val); if (ret < 0) @@ -422,29 +839,77 @@ static int ov5647_sensor_get_register(struct v4l2_subdev *sd, } static int ov5647_sensor_set_register(struct v4l2_subdev *sd, - const struct v4l2_dbg_register *reg) + const struct v4l2_dbg_register *reg) { return ov5647_write(sd, reg->reg & 0xff, reg->val & 0xff); } #endif -/* - * Subdev core operations registration - */ +/* Subdev core operations registration */ static const struct v4l2_subdev_core_ops ov5647_subdev_core_ops = { - .s_power = ov5647_sensor_power, + .subscribe_event = v4l2_ctrl_subdev_subscribe_event, + .unsubscribe_event = v4l2_event_subdev_unsubscribe, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = ov5647_sensor_get_register, .s_register = ov5647_sensor_set_register, #endif }; +static const struct v4l2_rect * +__ov5647_get_pad_crop(struct ov5647 *ov5647, struct v4l2_subdev_pad_config *cfg, + unsigned int pad, enum v4l2_subdev_format_whence which) +{ + switch (which) { + case V4L2_SUBDEV_FORMAT_TRY: + return v4l2_subdev_get_try_crop(&ov5647->sd, cfg, pad); + case V4L2_SUBDEV_FORMAT_ACTIVE: + return &ov5647->mode->crop; + } + + return NULL; +} + static int ov5647_s_stream(struct v4l2_subdev *sd, int enable) { - if (enable) - return ov5647_stream_on(sd); - else - return ov5647_stream_off(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5647 *sensor = to_sensor(sd); + int ret; + + mutex_lock(&sensor->lock); + if (sensor->streaming == enable) { + mutex_unlock(&sensor->lock); + return 0; + } + + if (enable) { + ret = pm_runtime_get_sync(&client->dev); + if (ret < 0) + goto error_unlock; + + ret = ov5647_stream_on(sd); + if (ret < 0) { + dev_err(&client->dev, "stream start failed: %d\n", ret); + goto error_unlock; + } + } else { + ret = ov5647_stream_off(sd); + if (ret < 0) { + dev_err(&client->dev, "stream stop failed: %d\n", ret); + goto error_unlock; + } + pm_runtime_put(&client->dev); + } + + sensor->streaming = enable; + mutex_unlock(&sensor->lock); + + return 0; + +error_unlock: + pm_runtime_put(&client->dev); + mutex_unlock(&sensor->lock); + + return ret; } static const struct v4l2_subdev_video_ops ov5647_subdev_video_ops = { @@ -452,19 +917,150 @@ static const struct v4l2_subdev_video_ops ov5647_subdev_video_ops = { }; static int ov5647_enum_mbus_code(struct v4l2_subdev *sd, - struct v4l2_subdev_pad_config *cfg, - struct v4l2_subdev_mbus_code_enum *code) + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) { if (code->index > 0) return -EINVAL; - code->code = MEDIA_BUS_FMT_SBGGR8_1X8; + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov5647_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + const struct v4l2_mbus_framefmt *fmt; + + if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10 || + fse->index >= ARRAY_SIZE(ov5647_modes)) + return -EINVAL; + + fmt = &ov5647_modes[fse->index].format; + fse->min_width = fmt->width; + fse->max_width = fmt->width; + fse->min_height = fmt->height; + fse->max_height = fmt->height; + + return 0; +} + +static int ov5647_get_pad_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + const struct v4l2_mbus_framefmt *sensor_format; + struct ov5647 *sensor = to_sensor(sd); + + mutex_lock(&sensor->lock); + switch (format->which) { + case V4L2_SUBDEV_FORMAT_TRY: + sensor_format = v4l2_subdev_get_try_format(sd, cfg, format->pad); + break; + default: + sensor_format = &sensor->mode->format; + break; + } + + *fmt = *sensor_format; + mutex_unlock(&sensor->lock); return 0; } +static int ov5647_set_pad_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5647 *sensor = to_sensor(sd); + const struct ov5647_mode *mode; + + mode = v4l2_find_nearest_size(ov5647_modes, ARRAY_SIZE(ov5647_modes), + format.width, format.height, + fmt->width, fmt->height); + + /* Update the sensor mode and apply at it at streamon time. */ + mutex_lock(&sensor->lock); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + *v4l2_subdev_get_try_format(sd, cfg, format->pad) = mode->format; + } else { + int exposure_max, exposure_def; + int hblank, vblank; + + sensor->mode = mode; + __v4l2_ctrl_modify_range(sensor->pixel_rate, mode->pixel_rate, + mode->pixel_rate, 1, mode->pixel_rate); + + hblank = mode->hts - mode->format.width; + __v4l2_ctrl_modify_range(sensor->hblank, hblank, hblank, 1, + hblank); + + vblank = mode->vts - mode->format.height; + __v4l2_ctrl_modify_range(sensor->vblank, OV5647_VBLANK_MIN, + OV5647_VTS_MAX - mode->format.height, + 1, vblank); + __v4l2_ctrl_s_ctrl(sensor->vblank, vblank); + + exposure_max = mode->vts - 4; + exposure_def = min(exposure_max, OV5647_EXPOSURE_DEFAULT); + __v4l2_ctrl_modify_range(sensor->exposure, + sensor->exposure->minimum, + exposure_max, sensor->exposure->step, + exposure_def); + } + *fmt = mode->format; + mutex_unlock(&sensor->lock); + + return 0; +} + +static int ov5647_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + switch (sel->target) { + case V4L2_SEL_TGT_CROP: { + struct ov5647 *sensor = to_sensor(sd); + + mutex_lock(&sensor->lock); + sel->r = *__ov5647_get_pad_crop(sensor, cfg, sel->pad, + sel->which); + mutex_unlock(&sensor->lock); + + return 0; + } + + case V4L2_SEL_TGT_NATIVE_SIZE: + sel->r.top = 0; + sel->r.left = 0; + sel->r.width = OV5647_NATIVE_WIDTH; + sel->r.height = OV5647_NATIVE_HEIGHT; + + return 0; + + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.top = OV5647_PIXEL_ARRAY_TOP; + sel->r.left = OV5647_PIXEL_ARRAY_LEFT; + sel->r.width = OV5647_PIXEL_ARRAY_WIDTH; + sel->r.height = OV5647_PIXEL_ARRAY_HEIGHT; + + return 0; + } + + return -EINVAL; +} + static const struct v4l2_subdev_pad_ops ov5647_subdev_pad_ops = { - .enum_mbus_code = ov5647_enum_mbus_code, + .enum_mbus_code = ov5647_enum_mbus_code, + .enum_frame_size = ov5647_enum_frame_size, + .set_fmt = ov5647_set_pad_fmt, + .get_fmt = ov5647_get_pad_fmt, + .get_selection = ov5647_get_selection, }; static const struct v4l2_subdev_ops ov5647_subdev_ops = { @@ -475,9 +1071,9 @@ static const struct v4l2_subdev_ops ov5647_subdev_ops = { static int ov5647_detect(struct v4l2_subdev *sd) { + struct i2c_client *client = v4l2_get_subdevdata(sd); u8 read; int ret; - struct i2c_client *client = v4l2_get_subdevdata(sd); ret = ov5647_write(sd, OV5647_SW_RESET, 0x01); if (ret < 0) @@ -508,20 +1104,14 @@ static int ov5647_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(sd, fh->pad, 0); - struct v4l2_rect *crop = - v4l2_subdev_get_try_crop(sd, fh->pad, 0); + struct v4l2_rect *crop = v4l2_subdev_get_try_crop(sd, fh->pad, 0); - crop->left = OV5647_COLUMN_START_DEF; - crop->top = OV5647_ROW_START_DEF; - crop->width = OV5647_WINDOW_WIDTH_DEF; - crop->height = OV5647_WINDOW_HEIGHT_DEF; + crop->left = OV5647_PIXEL_ARRAY_LEFT; + crop->top = OV5647_PIXEL_ARRAY_TOP; + crop->width = OV5647_PIXEL_ARRAY_WIDTH; + crop->height = OV5647_PIXEL_ARRAY_HEIGHT; - format->code = MEDIA_BUS_FMT_SBGGR8_1X8; - - format->width = OV5647_WINDOW_WIDTH_DEF; - format->height = OV5647_WINDOW_HEIGHT_DEF; - format->field = V4L2_FIELD_NONE; - format->colorspace = V4L2_COLORSPACE_SRGB; + *format = OV5647_DEFAULT_FORMAT; return 0; } @@ -530,11 +1120,220 @@ static const struct v4l2_subdev_internal_ops ov5647_subdev_internal_ops = { .open = ov5647_open, }; -static int ov5647_parse_dt(struct device_node *np) +static int ov5647_s_auto_white_balance(struct v4l2_subdev *sd, u32 val) { - struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 }; - struct device_node *ep; + return ov5647_write(sd, OV5647_REG_AWB, val ? 1 : 0); +} +static int ov5647_s_autogain(struct v4l2_subdev *sd, u32 val) +{ + int ret; + u8 reg; + + /* Non-zero turns on AGC by clearing bit 1.*/ + ret = ov5647_read(sd, OV5647_REG_AEC_AGC, ®); + if (ret) + return ret; + + return ov5647_write(sd, OV5647_REG_AEC_AGC, val ? reg & ~BIT(1) + : reg | BIT(1)); +} + +static int ov5647_s_exposure_auto(struct v4l2_subdev *sd, u32 val) +{ + int ret; + u8 reg; + + /* + * Everything except V4L2_EXPOSURE_MANUAL turns on AEC by + * clearing bit 0. + */ + ret = ov5647_read(sd, OV5647_REG_AEC_AGC, ®); + if (ret) + return ret; + + return ov5647_write(sd, OV5647_REG_AEC_AGC, + val == V4L2_EXPOSURE_MANUAL ? reg | BIT(0) + : reg & ~BIT(0)); +} + +static int ov5647_s_analogue_gain(struct v4l2_subdev *sd, u32 val) +{ + int ret; + + /* 10 bits of gain, 2 in the high register. */ + ret = ov5647_write(sd, OV5647_REG_GAIN_HI, (val >> 8) & 3); + if (ret) + return ret; + + return ov5647_write(sd, OV5647_REG_GAIN_LO, val & 0xff); +} + +static int ov5647_s_exposure(struct v4l2_subdev *sd, u32 val) +{ + int ret; + + /* + * Sensor has 20 bits, but the bottom 4 bits are fractions of a line + * which we leave as zero (and don't receive in "val"). + */ + ret = ov5647_write(sd, OV5647_REG_EXP_HI, (val >> 12) & 0xf); + if (ret) + return ret; + + ret = ov5647_write(sd, OV5647_REG_EXP_MID, (val >> 4) & 0xff); + if (ret) + return ret; + + return ov5647_write(sd, OV5647_REG_EXP_LO, (val & 0xf) << 4); +} + +static int ov5647_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5647 *sensor = container_of(ctrl->handler, + struct ov5647, ctrls); + struct v4l2_subdev *sd = &sensor->sd; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + + /* v4l2_ctrl_lock() locks our own mutex */ + + if (ctrl->id == V4L2_CID_VBLANK) { + int exposure_max, exposure_def; + + /* Update max exposure while meeting expected vblanking */ + exposure_max = sensor->mode->format.height + ctrl->val - 4; + exposure_def = min(exposure_max, OV5647_EXPOSURE_DEFAULT); + __v4l2_ctrl_modify_range(sensor->exposure, + sensor->exposure->minimum, + exposure_max, sensor->exposure->step, + exposure_def); + } + + /* + * If the device is not powered up do not apply any controls + * to H/W at this time. Instead the controls will be restored + * at s_stream(1) time. + */ + if (pm_runtime_get_if_in_use(&client->dev) == 0) + return 0; + + switch (ctrl->id) { + case V4L2_CID_AUTO_WHITE_BALANCE: + ret = ov5647_s_auto_white_balance(sd, ctrl->val); + break; + case V4L2_CID_AUTOGAIN: + ret = ov5647_s_autogain(sd, ctrl->val); + break; + case V4L2_CID_EXPOSURE_AUTO: + ret = ov5647_s_exposure_auto(sd, ctrl->val); + break; + case V4L2_CID_ANALOGUE_GAIN: + ret = ov5647_s_analogue_gain(sd, ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = ov5647_s_exposure(sd, ctrl->val); + break; + case V4L2_CID_VBLANK: + ret = ov5647_write16(sd, OV5647_REG_VTS_HI, + sensor->mode->format.height + ctrl->val); + break; + + /* Read-only, but we adjust it based on mode. */ + case V4L2_CID_PIXEL_RATE: + case V4L2_CID_HBLANK: + /* Read-only, but we adjust it based on mode. */ + break; + + default: + dev_info(&client->dev, + "Control (id:0x%x, val:0x%x) not supported\n", + ctrl->id, ctrl->val); + return -EINVAL; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ov5647_ctrl_ops = { + .s_ctrl = ov5647_s_ctrl, +}; + +static int ov5647_init_controls(struct ov5647 *sensor) +{ + struct i2c_client *client = v4l2_get_subdevdata(&sensor->sd); + int hblank, exposure_max, exposure_def; + + v4l2_ctrl_handler_init(&sensor->ctrls, 8); + + v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_AUTOGAIN, 0, 1, 1, 0); + + v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 0); + + v4l2_ctrl_new_std_menu(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, + 0, V4L2_EXPOSURE_MANUAL); + + exposure_max = sensor->mode->vts - 4; + exposure_def = min(exposure_max, OV5647_EXPOSURE_DEFAULT); + sensor->exposure = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_EXPOSURE, + OV5647_EXPOSURE_MIN, + exposure_max, OV5647_EXPOSURE_STEP, + exposure_def); + + /* min: 16 = 1.0x; max (10 bits); default: 32 = 2.0x. */ + v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, 16, 1023, 1, 32); + + /* By default, PIXEL_RATE is read only, but it does change per mode */ + sensor->pixel_rate = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_PIXEL_RATE, + sensor->mode->pixel_rate, + sensor->mode->pixel_rate, 1, + sensor->mode->pixel_rate); + + /* By default, HBLANK is read only, but it does change per mode. */ + hblank = sensor->mode->hts - sensor->mode->format.width; + sensor->hblank = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_HBLANK, hblank, hblank, 1, + hblank); + + sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops, + V4L2_CID_VBLANK, OV5647_VBLANK_MIN, + OV5647_VTS_MAX - + sensor->mode->format.height, 1, + sensor->mode->vts - + sensor->mode->format.height); + + if (sensor->ctrls.error) + goto handler_free; + + sensor->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; + sensor->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; + sensor->sd.ctrl_handler = &sensor->ctrls; + + return 0; + +handler_free: + dev_err(&client->dev, "%s Controls initialization failed (%d)\n", + __func__, sensor->ctrls.error); + v4l2_ctrl_handler_free(&sensor->ctrls); + + return sensor->ctrls.error; +} + +static int ov5647_parse_dt(struct ov5647 *sensor, struct device_node *np) +{ + struct v4l2_fwnode_endpoint bus_cfg = { + .bus_type = V4L2_MBUS_CSI2_DPHY, + }; + struct device_node *ep; int ret; ep = of_graph_get_next_endpoint(np, NULL); @@ -542,33 +1341,39 @@ static int ov5647_parse_dt(struct device_node *np) return -EINVAL; ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg); + if (ret) + goto out; + sensor->clock_ncont = bus_cfg.bus.mipi_csi2.flags & + V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; + +out: of_node_put(ep); + return ret; } static int ov5647_probe(struct i2c_client *client) { + struct device_node *np = client->dev.of_node; struct device *dev = &client->dev; struct ov5647 *sensor; - int ret; struct v4l2_subdev *sd; - struct device_node *np = client->dev.of_node; u32 xclk_freq; + int ret; sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); if (!sensor) return -ENOMEM; if (IS_ENABLED(CONFIG_OF) && np) { - ret = ov5647_parse_dt(np); + ret = ov5647_parse_dt(sensor, np); if (ret) { dev_err(dev, "DT parsing error: %d\n", ret); return ret; } } - /* get system clock (xclk) */ sensor->xclk = devm_clk_get(dev, NULL); if (IS_ERR(sensor->xclk)) { dev_err(dev, "could not get xclk"); @@ -581,52 +1386,87 @@ static int ov5647_probe(struct i2c_client *client) return -EINVAL; } + /* Request the power down GPIO asserted. */ + sensor->pwdn = devm_gpiod_get_optional(dev, "pwdn", GPIOD_OUT_HIGH); + if (IS_ERR(sensor->pwdn)) { + dev_err(dev, "Failed to get 'pwdn' gpio\n"); + return -EINVAL; + } + mutex_init(&sensor->lock); + sensor->mode = OV5647_DEFAULT_MODE; + + ret = ov5647_init_controls(sensor); + if (ret) + goto mutex_destroy; + sd = &sensor->sd; v4l2_i2c_subdev_init(sd, client, &ov5647_subdev_ops); - sensor->sd.internal_ops = &ov5647_subdev_internal_ops; - sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->internal_ops = &ov5647_subdev_internal_ops; + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; sensor->pad.flags = MEDIA_PAD_FL_SOURCE; sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; ret = media_entity_pads_init(&sd->entity, 1, &sensor->pad); if (ret < 0) - goto mutex_remove; + goto ctrl_handler_free; + + ret = ov5647_power_on(dev); + if (ret) + goto entity_cleanup; ret = ov5647_detect(sd); if (ret < 0) - goto error; + goto power_off; ret = v4l2_async_register_subdev(sd); if (ret < 0) - goto error; + goto power_off; + + /* Enable runtime PM and turn off the device */ + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_idle(dev); dev_dbg(dev, "OmniVision OV5647 camera driver probed\n"); + return 0; -error: + +power_off: + ov5647_power_off(dev); +entity_cleanup: media_entity_cleanup(&sd->entity); -mutex_remove: +ctrl_handler_free: + v4l2_ctrl_handler_free(&sensor->ctrls); +mutex_destroy: mutex_destroy(&sensor->lock); + return ret; } static int ov5647_remove(struct i2c_client *client) { struct v4l2_subdev *sd = i2c_get_clientdata(client); - struct ov5647 *ov5647 = to_state(sd); + struct ov5647 *sensor = to_sensor(sd); - v4l2_async_unregister_subdev(&ov5647->sd); - media_entity_cleanup(&ov5647->sd.entity); + v4l2_async_unregister_subdev(&sensor->sd); + media_entity_cleanup(&sensor->sd.entity); + v4l2_ctrl_handler_free(&sensor->ctrls); v4l2_device_unregister_subdev(sd); - mutex_destroy(&ov5647->lock); + pm_runtime_disable(&client->dev); + mutex_destroy(&sensor->lock); return 0; } +static const struct dev_pm_ops ov5647_pm_ops = { + SET_RUNTIME_PM_OPS(ov5647_power_off, ov5647_power_on, NULL) +}; + static const struct i2c_device_id ov5647_id[] = { { "ov5647", 0 }, - { } + { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, ov5647_id); @@ -641,7 +1481,8 @@ MODULE_DEVICE_TABLE(of, ov5647_of_match); static struct i2c_driver ov5647_driver = { .driver = { .of_match_table = of_match_ptr(ov5647_of_match), - .name = SENSOR_NAME, + .name = "ov5647", + .pm = &ov5647_pm_ops, }, .probe_new = ov5647_probe, .remove = ov5647_remove, diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c new file mode 100644 index 000000000000..dfe38ab8224d --- /dev/null +++ b/drivers/media/i2c/ov5648.c @@ -0,0 +1,2624 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2020 Bootlin + * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> +#include <linux/videodev2.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> +#include <media/v4l2-image-sizes.h> +#include <media/v4l2-mediabus.h> + +/* Clock rate */ + +#define OV5648_XVCLK_RATE 24000000 + +/* Register definitions */ + +/* System */ + +#define OV5648_SW_STANDBY_REG 0x100 +#define OV5648_SW_STANDBY_STREAM_ON BIT(0) + +#define OV5648_SW_RESET_REG 0x103 +#define OV5648_SW_RESET_RESET BIT(0) + +#define OV5648_PAD_OEN0_REG 0x3000 +#define OV5648_PAD_OEN1_REG 0x3001 +#define OV5648_PAD_OEN2_REG 0x3002 +#define OV5648_PAD_OUT0_REG 0x3008 +#define OV5648_PAD_OUT1_REG 0x3009 + +#define OV5648_CHIP_ID_H_REG 0x300a +#define OV5648_CHIP_ID_H_VALUE 0x56 +#define OV5648_CHIP_ID_L_REG 0x300b +#define OV5648_CHIP_ID_L_VALUE 0x48 + +#define OV5648_PAD_OUT2_REG 0x300d +#define OV5648_PAD_SEL0_REG 0x300e +#define OV5648_PAD_SEL1_REG 0x300f +#define OV5648_PAD_SEL2_REG 0x3010 +#define OV5648_PAD_PK_REG 0x3011 +#define OV5648_PAD_PK_PD_DATO_EN BIT(7) +#define OV5648_PAD_PK_DRIVE_STRENGTH_1X (0 << 5) +#define OV5648_PAD_PK_DRIVE_STRENGTH_2X (2 << 5) +#define OV5648_PAD_PK_FREX_N BIT(1) + +#define OV5648_A_PWC_PK_O0_REG 0x3013 +#define OV5648_A_PWC_PK_O0_BP_REGULATOR_N BIT(3) +#define OV5648_A_PWC_PK_O1_REG 0x3014 + +#define OV5648_MIPI_PHY0_REG 0x3016 +#define OV5648_MIPI_PHY1_REG 0x3017 +#define OV5648_MIPI_SC_CTRL0_REG 0x3018 +#define OV5648_MIPI_SC_CTRL0_MIPI_LANES(v) (((v) << 5) & GENMASK(7, 5)) +#define OV5648_MIPI_SC_CTRL0_PHY_HS_TX_PD BIT(4) +#define OV5648_MIPI_SC_CTRL0_PHY_LP_RX_PD BIT(3) +#define OV5648_MIPI_SC_CTRL0_MIPI_EN BIT(2) +#define OV5648_MIPI_SC_CTRL0_MIPI_SUSP BIT(1) +#define OV5648_MIPI_SC_CTRL0_LANE_DIS_OP BIT(0) +#define OV5648_MIPI_SC_CTRL1_REG 0x3019 +#define OV5648_MISC_CTRL0_REG 0x3021 +#define OV5648_MIPI_SC_CTRL2_REG 0x3022 +#define OV5648_SUB_ID_REG 0x302a + +#define OV5648_PLL_CTRL0_REG 0x3034 +#define OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4)) +#define OV5648_PLL_CTRL0_BITS(v) ((v) & GENMASK(3, 0)) +#define OV5648_PLL_CTRL1_REG 0x3035 +#define OV5648_PLL_CTRL1_SYS_DIV(v) (((v) << 4) & GENMASK(7, 4)) +#define OV5648_PLL_CTRL1_MIPI_DIV(v) ((v) & GENMASK(3, 0)) +#define OV5648_PLL_MUL_REG 0x3036 +#define OV5648_PLL_MUL(v) ((v) & GENMASK(7, 0)) +#define OV5648_PLL_DIV_REG 0x3037 +#define OV5648_PLL_DIV_ROOT_DIV(v) ((((v) - 1) << 4) & BIT(4)) +#define OV5648_PLL_DIV_PLL_PRE_DIV(v) ((v) & GENMASK(3, 0)) +#define OV5648_PLL_DEBUG_REG 0x3038 +#define OV5648_PLL_BYPASS_REG 0x3039 + +#define OV5648_PLLS_BYPASS_REG 0x303a +#define OV5648_PLLS_MUL_REG 0x303b +#define OV5648_PLLS_MUL(v) ((v) & GENMASK(4, 0)) +#define OV5648_PLLS_CTRL_REG 0x303c +#define OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(v) (((v) << 4) & GENMASK(6, 4)) +#define OV5648_PLLS_CTRL_SYS_DIV(v) ((v) & GENMASK(3, 0)) +#define OV5648_PLLS_DIV_REG 0x303d +#define OV5648_PLLS_DIV_PLLS_PRE_DIV(v) (((v) << 4) & GENMASK(5, 4)) +#define OV5648_PLLS_DIV_PLLS_DIV_R(v) ((((v) - 1) << 2) & BIT(2)) +#define OV5648_PLLS_DIV_PLLS_SEL_DIV(v) ((v) & GENMASK(1, 0)) + +#define OV5648_SRB_CTRL_REG 0x3106 +#define OV5648_SRB_CTRL_SCLK_DIV(v) (((v) << 2) & GENMASK(3, 2)) +#define OV5648_SRB_CTRL_RESET_ARBITER_EN BIT(1) +#define OV5648_SRB_CTRL_SCLK_ARBITER_EN BIT(0) + +/* Group Hold */ + +#define OV5648_GROUP_ADR0_REG 0x3200 +#define OV5648_GROUP_ADR1_REG 0x3201 +#define OV5648_GROUP_ADR2_REG 0x3202 +#define OV5648_GROUP_ADR3_REG 0x3203 +#define OV5648_GROUP_LEN0_REG 0x3204 +#define OV5648_GROUP_LEN1_REG 0x3205 +#define OV5648_GROUP_LEN2_REG 0x3206 +#define OV5648_GROUP_LEN3_REG 0x3207 +#define OV5648_GROUP_ACCESS_REG 0x3208 + +/* Exposure/gain/banding */ + +#define OV5648_EXPOSURE_CTRL_HH_REG 0x3500 +#define OV5648_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16) +#define OV5648_EXPOSURE_CTRL_HH_VALUE(v) (((v) << 16) & GENMASK(19, 16)) +#define OV5648_EXPOSURE_CTRL_H_REG 0x3501 +#define OV5648_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV5648_EXPOSURE_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(15, 8)) +#define OV5648_EXPOSURE_CTRL_L_REG 0x3502 +#define OV5648_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_EXPOSURE_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0)) +#define OV5648_MANUAL_CTRL_REG 0x3503 +#define OV5648_MANUAL_CTRL_FRAME_DELAY(v) (((v) << 4) & GENMASK(5, 4)) +#define OV5648_MANUAL_CTRL_AGC_MANUAL_EN BIT(1) +#define OV5648_MANUAL_CTRL_AEC_MANUAL_EN BIT(0) +#define OV5648_GAIN_CTRL_H_REG 0x350a +#define OV5648_GAIN_CTRL_H(v) (((v) & GENMASK(9, 8)) >> 8) +#define OV5648_GAIN_CTRL_H_VALUE(v) (((v) << 8) & GENMASK(9, 8)) +#define OV5648_GAIN_CTRL_L_REG 0x350b +#define OV5648_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_GAIN_CTRL_L_VALUE(v) ((v) & GENMASK(7, 0)) + +#define OV5648_ANALOG_CTRL0_REG_BASE 0x3600 +#define OV5648_ANALOG_CTRL1_REG_BASE 0x3700 + +#define OV5648_AEC_CTRL0_REG 0x3a00 +#define OV5648_AEC_CTRL0_DEBUG BIT(6) +#define OV5648_AEC_CTRL0_DEBAND_EN BIT(5) +#define OV5648_AEC_CTRL0_DEBAND_LOW_LIMIT_EN BIT(4) +#define OV5648_AEC_CTRL0_START_SEL_EN BIT(3) +#define OV5648_AEC_CTRL0_NIGHT_MODE_EN BIT(2) +#define OV5648_AEC_CTRL0_FREEZE_EN BIT(0) +#define OV5648_EXPOSURE_MIN_REG 0x3a01 +#define OV5648_EXPOSURE_MAX_60_H_REG 0x3a02 +#define OV5648_EXPOSURE_MAX_60_L_REG 0x3a03 +#define OV5648_AEC_CTRL5_REG 0x3a05 +#define OV5648_AEC_CTRL6_REG 0x3a06 +#define OV5648_AEC_CTRL7_REG 0x3a07 +#define OV5648_BANDING_STEP_50_H_REG 0x3a08 +#define OV5648_BANDING_STEP_50_L_REG 0x3a09 +#define OV5648_BANDING_STEP_60_H_REG 0x3a0a +#define OV5648_BANDING_STEP_60_L_REG 0x3a0b +#define OV5648_AEC_CTRLC_REG 0x3a0c +#define OV5648_BANDING_MAX_60_REG 0x3a0d +#define OV5648_BANDING_MAX_50_REG 0x3a0e +#define OV5648_WPT_REG 0x3a0f +#define OV5648_BPT_REG 0x3a10 +#define OV5648_VPT_HIGH_REG 0x3a11 +#define OV5648_AVG_MANUAL_REG 0x3a12 +#define OV5648_PRE_GAIN_REG 0x3a13 +#define OV5648_EXPOSURE_MAX_50_H_REG 0x3a14 +#define OV5648_EXPOSURE_MAX_50_L_REG 0x3a15 +#define OV5648_GAIN_BASE_NIGHT_REG 0x3a17 +#define OV5648_AEC_GAIN_CEILING_H_REG 0x3a18 +#define OV5648_AEC_GAIN_CEILING_L_REG 0x3a19 +#define OV5648_DIFF_MAX_REG 0x3a1a +#define OV5648_WPT2_REG 0x3a1b +#define OV5648_LED_ADD_ROW_H_REG 0x3a1c +#define OV5648_LED_ADD_ROW_L_REG 0x3a1d +#define OV5648_BPT2_REG 0x3a1e +#define OV5648_VPT_LOW_REG 0x3a1f +#define OV5648_AEC_CTRL20_REG 0x3a20 +#define OV5648_AEC_CTRL21_REG 0x3a21 + +#define OV5648_AVG_START_X_H_REG 0x5680 +#define OV5648_AVG_START_X_L_REG 0x5681 +#define OV5648_AVG_START_Y_H_REG 0x5682 +#define OV5648_AVG_START_Y_L_REG 0x5683 +#define OV5648_AVG_WINDOW_X_H_REG 0x5684 +#define OV5648_AVG_WINDOW_X_L_REG 0x5685 +#define OV5648_AVG_WINDOW_Y_H_REG 0x5686 +#define OV5648_AVG_WINDOW_Y_L_REG 0x5687 +#define OV5648_AVG_WEIGHT00_REG 0x5688 +#define OV5648_AVG_WEIGHT01_REG 0x5689 +#define OV5648_AVG_WEIGHT02_REG 0x568a +#define OV5648_AVG_WEIGHT03_REG 0x568b +#define OV5648_AVG_WEIGHT04_REG 0x568c +#define OV5648_AVG_WEIGHT05_REG 0x568d +#define OV5648_AVG_WEIGHT06_REG 0x568e +#define OV5648_AVG_WEIGHT07_REG 0x568f +#define OV5648_AVG_CTRL10_REG 0x5690 +#define OV5648_AVG_WEIGHT_SUM_REG 0x5691 +#define OV5648_AVG_READOUT_REG 0x5693 + +#define OV5648_DIG_CTRL0_REG 0x5a00 +#define OV5648_DIG_COMP_MAN_H_REG 0x5a02 +#define OV5648_DIG_COMP_MAN_L_REG 0x5a03 + +#define OV5648_GAINC_MAN_H_REG 0x5a20 +#define OV5648_GAINC_MAN_L_REG 0x5a21 +#define OV5648_GAINC_DGC_MAN_H_REG 0x5a22 +#define OV5648_GAINC_DGC_MAN_L_REG 0x5a23 +#define OV5648_GAINC_CTRL0_REG 0x5a24 + +#define OV5648_GAINF_ANA_NUM_REG 0x5a40 +#define OV5648_GAINF_DIG_GAIN_REG 0x5a41 + +/* Timing */ + +#define OV5648_CROP_START_X_H_REG 0x3800 +#define OV5648_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_CROP_START_X_L_REG 0x3801 +#define OV5648_CROP_START_X_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_CROP_START_Y_H_REG 0x3802 +#define OV5648_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_CROP_START_Y_L_REG 0x3803 +#define OV5648_CROP_START_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_CROP_END_X_H_REG 0x3804 +#define OV5648_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_CROP_END_X_L_REG 0x3805 +#define OV5648_CROP_END_X_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_CROP_END_Y_H_REG 0x3806 +#define OV5648_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_CROP_END_Y_L_REG 0x3807 +#define OV5648_CROP_END_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_OUTPUT_SIZE_X_H_REG 0x3808 +#define OV5648_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_OUTPUT_SIZE_X_L_REG 0x3809 +#define OV5648_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_OUTPUT_SIZE_Y_H_REG 0x380a +#define OV5648_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_OUTPUT_SIZE_Y_L_REG 0x380b +#define OV5648_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_HTS_H_REG 0x380c +#define OV5648_HTS_H(v) (((v) & GENMASK(12, 8)) >> 8) +#define OV5648_HTS_L_REG 0x380d +#define OV5648_HTS_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_VTS_H_REG 0x380e +#define OV5648_VTS_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV5648_VTS_L_REG 0x380f +#define OV5648_VTS_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_OFFSET_X_H_REG 0x3810 +#define OV5648_OFFSET_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_OFFSET_X_L_REG 0x3811 +#define OV5648_OFFSET_X_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_OFFSET_Y_H_REG 0x3812 +#define OV5648_OFFSET_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_OFFSET_Y_L_REG 0x3813 +#define OV5648_OFFSET_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_SUB_INC_X_REG 0x3814 +#define OV5648_SUB_INC_X_ODD(v) (((v) << 4) & GENMASK(7, 4)) +#define OV5648_SUB_INC_X_EVEN(v) ((v) & GENMASK(3, 0)) +#define OV5648_SUB_INC_Y_REG 0x3815 +#define OV5648_SUB_INC_Y_ODD(v) (((v) << 4) & GENMASK(7, 4)) +#define OV5648_SUB_INC_Y_EVEN(v) ((v) & GENMASK(3, 0)) +#define OV5648_HSYNCST_H_REG 0x3816 +#define OV5648_HSYNCST_H(v) (((v) >> 8) & 0xf) +#define OV5648_HSYNCST_L_REG 0x3817 +#define OV5648_HSYNCST_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_HSYNCW_H_REG 0x3818 +#define OV5648_HSYNCW_H(v) (((v) >> 8) & 0xf) +#define OV5648_HSYNCW_L_REG 0x3819 +#define OV5648_HSYNCW_L(v) ((v) & GENMASK(7, 0)) + +#define OV5648_TC20_REG 0x3820 +#define OV5648_TC20_DEBUG BIT(6) +#define OV5648_TC20_FLIP_VERT_ISP_EN BIT(2) +#define OV5648_TC20_FLIP_VERT_SENSOR_EN BIT(1) +#define OV5648_TC20_BINNING_VERT_EN BIT(0) +#define OV5648_TC21_REG 0x3821 +#define OV5648_TC21_FLIP_HORZ_ISP_EN BIT(2) +#define OV5648_TC21_FLIP_HORZ_SENSOR_EN BIT(1) +#define OV5648_TC21_BINNING_HORZ_EN BIT(0) + +/* Strobe/exposure */ + +#define OV5648_STROBE_REG 0x3b00 +#define OV5648_FREX_EXP_HH_REG 0x3b01 +#define OV5648_SHUTTER_DLY_H_REG 0x3b02 +#define OV5648_SHUTTER_DLY_L_REG 0x3b03 +#define OV5648_FREX_EXP_H_REG 0x3b04 +#define OV5648_FREX_EXP_L_REG 0x3b05 +#define OV5648_FREX_CTRL_REG 0x3b06 +#define OV5648_FREX_MODE_SEL_REG 0x3b07 +#define OV5648_FREX_MODE_SEL_FREX_SA1 BIT(4) +#define OV5648_FREX_MODE_SEL_FX1_FM_EN BIT(3) +#define OV5648_FREX_MODE_SEL_FREX_INV BIT(2) +#define OV5648_FREX_MODE_SEL_MODE1 0x0 +#define OV5648_FREX_MODE_SEL_MODE2 0x1 +#define OV5648_FREX_MODE_SEL_ROLLING 0x2 +#define OV5648_FREX_EXP_REQ_REG 0x3b08 +#define OV5648_FREX_SHUTTER_DLY_REG 0x3b09 +#define OV5648_FREX_RST_LEN_REG 0x3b0a +#define OV5648_STROBE_WIDTH_HH_REG 0x3b0b +#define OV5648_STROBE_WIDTH_H_REG 0x3b0c + +/* OTP */ + +#define OV5648_OTP_DATA_REG_BASE 0x3d00 +#define OV5648_OTP_PROGRAM_CTRL_REG 0x3d80 +#define OV5648_OTP_LOAD_CTRL_REG 0x3d81 + +/* PSRAM */ + +#define OV5648_PSRAM_CTRL1_REG 0x3f01 +#define OV5648_PSRAM_CTRLF_REG 0x3f0f + +/* Black Level */ + +#define OV5648_BLC_CTRL0_REG 0x4000 +#define OV5648_BLC_CTRL1_REG 0x4001 +#define OV5648_BLC_CTRL1_START_LINE(v) ((v) & GENMASK(5, 0)) +#define OV5648_BLC_CTRL2_REG 0x4002 +#define OV5648_BLC_CTRL2_AUTO_EN BIT(6) +#define OV5648_BLC_CTRL2_RESET_FRAME_NUM(v) ((v) & GENMASK(5, 0)) +#define OV5648_BLC_CTRL3_REG 0x4003 +#define OV5648_BLC_LINE_NUM_REG 0x4004 +#define OV5648_BLC_LINE_NUM(v) ((v) & GENMASK(7, 0)) +#define OV5648_BLC_CTRL5_REG 0x4005 +#define OV5648_BLC_CTRL5_UPDATE_EN BIT(1) +#define OV5648_BLC_LEVEL_REG 0x4009 + +/* Frame */ + +#define OV5648_FRAME_CTRL_REG 0x4200 +#define OV5648_FRAME_ON_NUM_REG 0x4201 +#define OV5648_FRAME_OFF_NUM_REG 0x4202 + +/* MIPI CSI-2 */ + +#define OV5648_MIPI_CTRL0_REG 0x4800 +#define OV5648_MIPI_CTRL0_CLK_LANE_AUTOGATE BIT(5) +#define OV5648_MIPI_CTRL0_LANE_SYNC_EN BIT(4) +#define OV5648_MIPI_CTRL0_LANE_SELECT_LANE1 0 +#define OV5648_MIPI_CTRL0_LANE_SELECT_LANE2 BIT(3) +#define OV5648_MIPI_CTRL0_IDLE_LP00 0 +#define OV5648_MIPI_CTRL0_IDLE_LP11 BIT(2) + +#define OV5648_MIPI_CTRL1_REG 0x4801 +#define OV5648_MIPI_CTRL2_REG 0x4802 +#define OV5648_MIPI_CTRL3_REG 0x4803 +#define OV5648_MIPI_CTRL4_REG 0x4804 +#define OV5648_MIPI_CTRL5_REG 0x4805 +#define OV5648_MIPI_MAX_FRAME_COUNT_H_REG 0x4810 +#define OV5648_MIPI_MAX_FRAME_COUNT_L_REG 0x4811 +#define OV5648_MIPI_CTRL14_REG 0x4814 +#define OV5648_MIPI_DT_SPKT_REG 0x4815 +#define OV5648_MIPI_HS_ZERO_MIN_H_REG 0x4818 +#define OV5648_MIPI_HS_ZERO_MIN_L_REG 0x4819 +#define OV5648_MIPI_HS_TRAIN_MIN_H_REG 0x481a +#define OV5648_MIPI_HS_TRAIN_MIN_L_REG 0x481b +#define OV5648_MIPI_CLK_ZERO_MIN_H_REG 0x481c +#define OV5648_MIPI_CLK_ZERO_MIN_L_REG 0x481d +#define OV5648_MIPI_CLK_PREPARE_MIN_H_REG 0x481e +#define OV5648_MIPI_CLK_PREPARE_MIN_L_REG 0x481f +#define OV5648_MIPI_CLK_POST_MIN_H_REG 0x4820 +#define OV5648_MIPI_CLK_POST_MIN_L_REG 0x4821 +#define OV5648_MIPI_CLK_TRAIL_MIN_H_REG 0x4822 +#define OV5648_MIPI_CLK_TRAIL_MIN_L_REG 0x4823 +#define OV5648_MIPI_LPX_P_MIN_H_REG 0x4824 +#define OV5648_MIPI_LPX_P_MIN_L_REG 0x4825 +#define OV5648_MIPI_HS_PREPARE_MIN_H_REG 0x4826 +#define OV5648_MIPI_HS_PREPARE_MIN_L_REG 0x4827 +#define OV5648_MIPI_HS_EXIT_MIN_H_REG 0x4828 +#define OV5648_MIPI_HS_EXIT_MIN_L_REG 0x4829 +#define OV5648_MIPI_HS_ZERO_MIN_UI_REG 0x482a +#define OV5648_MIPI_HS_TRAIL_MIN_UI_REG 0x482b +#define OV5648_MIPI_CLK_ZERO_MIN_UI_REG 0x482c +#define OV5648_MIPI_CLK_PREPARE_MIN_UI_REG 0x482d +#define OV5648_MIPI_CLK_POST_MIN_UI_REG 0x482e +#define OV5648_MIPI_CLK_TRAIL_MIN_UI_REG 0x482f +#define OV5648_MIPI_LPX_P_MIN_UI_REG 0x4830 +#define OV5648_MIPI_HS_PREPARE_MIN_UI_REG 0x4831 +#define OV5648_MIPI_HS_EXIT_MIN_UI_REG 0x4832 +#define OV5648_MIPI_REG_MIN_H_REG 0x4833 +#define OV5648_MIPI_REG_MIN_L_REG 0x4834 +#define OV5648_MIPI_REG_MAX_H_REG 0x4835 +#define OV5648_MIPI_REG_MAX_L_REG 0x4836 +#define OV5648_MIPI_PCLK_PERIOD_REG 0x4837 +#define OV5648_MIPI_WKUP_DLY_REG 0x4838 +#define OV5648_MIPI_LP_GPIO_REG 0x483b +#define OV5648_MIPI_SNR_PCLK_DIV_REG 0x4843 + +/* ISP */ + +#define OV5648_ISP_CTRL0_REG 0x5000 +#define OV5648_ISP_CTRL0_BLACK_CORRECT_EN BIT(2) +#define OV5648_ISP_CTRL0_WHITE_CORRECT_EN BIT(1) +#define OV5648_ISP_CTRL1_REG 0x5001 +#define OV5648_ISP_CTRL1_AWB_EN BIT(0) +#define OV5648_ISP_CTRL2_REG 0x5002 +#define OV5648_ISP_CTRL2_WIN_EN BIT(6) +#define OV5648_ISP_CTRL2_OTP_EN BIT(1) +#define OV5648_ISP_CTRL2_AWB_GAIN_EN BIT(0) +#define OV5648_ISP_CTRL3_REG 0x5003 +#define OV5648_ISP_CTRL3_BUF_EN BIT(3) +#define OV5648_ISP_CTRL3_BIN_MAN_SET BIT(2) +#define OV5648_ISP_CTRL3_BIN_AUTO_EN BIT(1) +#define OV5648_ISP_CTRL4_REG 0x5004 +#define OV5648_ISP_CTRL5_REG 0x5005 +#define OV5648_ISP_CTRL6_REG 0x5006 +#define OV5648_ISP_CTRL7_REG 0x5007 +#define OV5648_ISP_MAN_OFFSET_X_H_REG 0x5008 +#define OV5648_ISP_MAN_OFFSET_X_L_REG 0x5009 +#define OV5648_ISP_MAN_OFFSET_Y_H_REG 0x500a +#define OV5648_ISP_MAN_OFFSET_Y_L_REG 0x500b +#define OV5648_ISP_MAN_WIN_OFFSET_X_H_REG 0x500c +#define OV5648_ISP_MAN_WIN_OFFSET_X_L_REG 0x500d +#define OV5648_ISP_MAN_WIN_OFFSET_Y_H_REG 0x500e +#define OV5648_ISP_MAN_WIN_OFFSET_Y_L_REG 0x500f +#define OV5648_ISP_MAN_WIN_OUTPUT_X_H_REG 0x5010 +#define OV5648_ISP_MAN_WIN_OUTPUT_X_L_REG 0x5011 +#define OV5648_ISP_MAN_WIN_OUTPUT_Y_H_REG 0x5012 +#define OV5648_ISP_MAN_WIN_OUTPUT_Y_L_REG 0x5013 +#define OV5648_ISP_MAN_INPUT_X_H_REG 0x5014 +#define OV5648_ISP_MAN_INPUT_X_L_REG 0x5015 +#define OV5648_ISP_MAN_INPUT_Y_H_REG 0x5016 +#define OV5648_ISP_MAN_INPUT_Y_L_REG 0x5017 +#define OV5648_ISP_CTRL18_REG 0x5018 +#define OV5648_ISP_CTRL19_REG 0x5019 +#define OV5648_ISP_CTRL1A_REG 0x501a +#define OV5648_ISP_CTRL1D_REG 0x501d +#define OV5648_ISP_CTRL1F_REG 0x501f +#define OV5648_ISP_CTRL1F_OUTPUT_EN 3 +#define OV5648_ISP_CTRL25_REG 0x5025 + +#define OV5648_ISP_CTRL3D_REG 0x503d +#define OV5648_ISP_CTRL3D_PATTERN_EN BIT(7) +#define OV5648_ISP_CTRL3D_ROLLING_BAR_EN BIT(6) +#define OV5648_ISP_CTRL3D_TRANSPARENT_MODE BIT(5) +#define OV5648_ISP_CTRL3D_SQUARES_BW_MODE BIT(4) +#define OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS 0 +#define OV5648_ISP_CTRL3D_PATTERN_RANDOM_DATA 1 +#define OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES 2 +#define OV5648_ISP_CTRL3D_PATTERN_INPUT 3 + +#define OV5648_ISP_CTRL3E_REG 0x503e +#define OV5648_ISP_CTRL4B_REG 0x504b +#define OV5648_ISP_CTRL4B_POST_BIN_H_EN BIT(5) +#define OV5648_ISP_CTRL4B_POST_BIN_V_EN BIT(4) +#define OV5648_ISP_CTRL4C_REG 0x504c +#define OV5648_ISP_CTRL57_REG 0x5057 +#define OV5648_ISP_CTRL58_REG 0x5058 +#define OV5648_ISP_CTRL59_REG 0x5059 + +#define OV5648_ISP_WINDOW_START_X_H_REG 0x5980 +#define OV5648_ISP_WINDOW_START_X_L_REG 0x5981 +#define OV5648_ISP_WINDOW_START_Y_H_REG 0x5982 +#define OV5648_ISP_WINDOW_START_Y_L_REG 0x5983 +#define OV5648_ISP_WINDOW_WIN_X_H_REG 0x5984 +#define OV5648_ISP_WINDOW_WIN_X_L_REG 0x5985 +#define OV5648_ISP_WINDOW_WIN_Y_H_REG 0x5986 +#define OV5648_ISP_WINDOW_WIN_Y_L_REG 0x5987 +#define OV5648_ISP_WINDOW_MAN_REG 0x5988 + +/* White Balance */ + +#define OV5648_AWB_CTRL_REG 0x5180 +#define OV5648_AWB_CTRL_FAST_AWB BIT(6) +#define OV5648_AWB_CTRL_GAIN_FREEZE_EN BIT(5) +#define OV5648_AWB_CTRL_SUM_FREEZE_EN BIT(4) +#define OV5648_AWB_CTRL_GAIN_MANUAL_EN BIT(3) + +#define OV5648_AWB_DELTA_REG 0x5181 +#define OV5648_AWB_STABLE_RANGE_REG 0x5182 +#define OV5648_AWB_STABLE_RANGE_WIDE_REG 0x5183 +#define OV5648_HSIZE_MAN_REG 0x5185 + +#define OV5648_GAIN_RED_MAN_H_REG 0x5186 +#define OV5648_GAIN_RED_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_GAIN_RED_MAN_L_REG 0x5187 +#define OV5648_GAIN_RED_MAN_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_GAIN_GREEN_MAN_H_REG 0x5188 +#define OV5648_GAIN_GREEN_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_GAIN_GREEN_MAN_L_REG 0x5189 +#define OV5648_GAIN_GREEN_MAN_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_GAIN_BLUE_MAN_H_REG 0x518a +#define OV5648_GAIN_BLUE_MAN_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV5648_GAIN_BLUE_MAN_L_REG 0x518b +#define OV5648_GAIN_BLUE_MAN_L(v) ((v) & GENMASK(7, 0)) +#define OV5648_GAIN_RED_LIMIT_REG 0x518c +#define OV5648_GAIN_GREEN_LIMIT_REG 0x518d +#define OV5648_GAIN_BLUE_LIMIT_REG 0x518e +#define OV5648_AWB_FRAME_COUNT_REG 0x518f +#define OV5648_AWB_BASE_MAN_REG 0x51df + +/* Macros */ + +#define ov5648_subdev_sensor(s) \ + container_of(s, struct ov5648_sensor, subdev) + +#define ov5648_ctrl_subdev(c) \ + (&container_of((c)->handler, struct ov5648_sensor, \ + ctrls.handler)->subdev) + +/* Data structures */ + +struct ov5648_register_value { + u16 address; + u8 value; + unsigned int delay_ms; +}; + +/* + * PLL1 Clock Tree: + * + * +-< XVCLK + * | + * +-+ pll_pre_div (0x3037 [3:0], special values: 5: 1.5, 7: 2.5) + * | + * +-+ pll_mul (0x3036 [7:0]) + * | + * +-+ sys_div (0x3035 [7:4]) + * | + * +-+ mipi_div (0x3035 [3:0]) + * | | + * | +-> MIPI_SCLK + * | | + * | +-+ mipi_phy_div (2) + * | | + * | +-> MIPI_CLK + * | + * +-+ root_div (0x3037 [4]) + * | + * +-+ bit_div (0x3034 [3:0], 8 bits: 2, 10 bits: 2.5, other: 1) + * | + * +-+ sclk_div (0x3106 [3:2]) + * | + * +-> SCLK + * | + * +-+ mipi_div (0x3035, 1: PCLK = SCLK) + * | + * +-> PCLK + */ + +struct ov5648_pll1_config { + unsigned int pll_pre_div; + unsigned int pll_mul; + unsigned int sys_div; + unsigned int root_div; + unsigned int sclk_div; + unsigned int mipi_div; +}; + +/* + * PLL2 Clock Tree: + * + * +-< XVCLK + * | + * +-+ plls_pre_div (0x303d [5:4], special values: 0: 1, 1: 1.5) + * | + * +-+ plls_div_r (0x303d [2]) + * | + * +-+ plls_mul (0x303b [4:0]) + * | + * +-+ sys_div (0x303c [3:0]) + * | + * +-+ sel_div (0x303d [1:0], special values: 0: 1, 3: 2.5) + * | + * +-> ADCLK + */ + +struct ov5648_pll2_config { + unsigned int plls_pre_div; + unsigned int plls_div_r; + unsigned int plls_mul; + unsigned int sys_div; + unsigned int sel_div; +}; + +/* + * General formulas for (array-centered) mode calculation: + * - photo_array_width = 2624 + * - crop_start_x = (photo_array_width - output_size_x) / 2 + * - crop_end_x = crop_start_x + offset_x + output_size_x - 1 + * + * - photo_array_height = 1956 + * - crop_start_y = (photo_array_height - output_size_y) / 2 + * - crop_end_y = crop_start_y + offset_y + output_size_y - 1 + */ + +struct ov5648_mode { + unsigned int crop_start_x; + unsigned int offset_x; + unsigned int output_size_x; + unsigned int crop_end_x; + unsigned int hts; + + unsigned int crop_start_y; + unsigned int offset_y; + unsigned int output_size_y; + unsigned int crop_end_y; + unsigned int vts; + + bool binning_x; + bool binning_y; + + unsigned int inc_x_odd; + unsigned int inc_x_even; + unsigned int inc_y_odd; + unsigned int inc_y_even; + + /* 8-bit frame interval followed by 10-bit frame interval. */ + struct v4l2_fract frame_interval[2]; + + /* 8-bit config followed by 10-bit config. */ + const struct ov5648_pll1_config *pll1_config[2]; + const struct ov5648_pll2_config *pll2_config; + + const struct ov5648_register_value *register_values; + unsigned int register_values_count; +}; + +struct ov5648_state { + const struct ov5648_mode *mode; + u32 mbus_code; + + bool streaming; +}; + +struct ov5648_ctrls { + struct v4l2_ctrl *exposure_auto; + struct v4l2_ctrl *exposure; + + struct v4l2_ctrl *gain_auto; + struct v4l2_ctrl *gain; + + struct v4l2_ctrl *white_balance_auto; + struct v4l2_ctrl *red_balance; + struct v4l2_ctrl *blue_balance; + + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + + struct v4l2_ctrl_handler handler; +} __packed; + +struct ov5648_sensor { + struct device *dev; + struct i2c_client *i2c_client; + struct gpio_desc *reset; + struct gpio_desc *powerdown; + struct regulator *avdd; + struct regulator *dvdd; + struct regulator *dovdd; + struct clk *xvclk; + + struct v4l2_fwnode_endpoint endpoint; + struct v4l2_subdev subdev; + struct media_pad pad; + + struct mutex mutex; + + struct ov5648_state state; + struct ov5648_ctrls ctrls; +}; + +/* Static definitions */ + +/* + * XVCLK = 24 MHz + * SCLK = 84 MHz + * PCLK = 84 MHz + */ +static const struct ov5648_pll1_config ov5648_pll1_config_native_8_bits = { + .pll_pre_div = 3, + .pll_mul = 84, + .sys_div = 2, + .root_div = 1, + .sclk_div = 1, + .mipi_div = 1, +}; + +/* + * XVCLK = 24 MHz + * SCLK = 84 MHz + * PCLK = 84 MHz + */ +static const struct ov5648_pll1_config ov5648_pll1_config_native_10_bits = { + .pll_pre_div = 3, + .pll_mul = 105, + .sys_div = 2, + .root_div = 1, + .sclk_div = 1, + .mipi_div = 1, +}; + +/* + * XVCLK = 24 MHz + * ADCLK = 200 MHz + */ +static const struct ov5648_pll2_config ov5648_pll2_config_native = { + .plls_pre_div = 3, + .plls_div_r = 1, + .plls_mul = 25, + .sys_div = 1, + .sel_div = 1, +}; + +static const struct ov5648_mode ov5648_modes[] = { + /* 2592x1944 */ + { + /* Horizontal */ + .crop_start_x = 16, + .offset_x = 0, + .output_size_x = 2592, + .crop_end_x = 2607, + .hts = 2816, + + /* Vertical */ + .crop_start_y = 6, + .offset_y = 0, + .output_size_y = 1944, + .crop_end_y = 1949, + .vts = 1984, + + /* Subsample increase */ + .inc_x_odd = 1, + .inc_x_even = 1, + .inc_y_odd = 1, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 15 }, + { 1, 15 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, + /* 1600x1200 (UXGA) */ + { + /* Horizontal */ + .crop_start_x = 512, + .offset_x = 0, + .output_size_x = 1600, + .crop_end_x = 2111, + .hts = 2816, + + /* Vertical */ + .crop_start_y = 378, + .offset_y = 0, + .output_size_y = 1200, + .crop_end_y = 1577, + .vts = 1984, + + /* Subsample increase */ + .inc_x_odd = 1, + .inc_x_even = 1, + .inc_y_odd = 1, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 15 }, + { 1, 15 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, + /* 1920x1080 (Full HD) */ + { + /* Horizontal */ + .crop_start_x = 352, + .offset_x = 0, + .output_size_x = 1920, + .crop_end_x = 2271, + .hts = 2816, + + /* Vertical */ + .crop_start_y = 438, + .offset_y = 0, + .output_size_y = 1080, + .crop_end_y = 1517, + .vts = 1984, + + /* Subsample increase */ + .inc_x_odd = 1, + .inc_x_even = 1, + .inc_y_odd = 1, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 15 }, + { 1, 15 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, + /* 1280x960 */ + { + /* Horizontal */ + .crop_start_x = 16, + .offset_x = 8, + .output_size_x = 1280, + .crop_end_x = 2607, + .hts = 1912, + + /* Vertical */ + .crop_start_y = 6, + .offset_y = 6, + .output_size_y = 960, + .crop_end_y = 1949, + .vts = 1496, + + /* Binning */ + .binning_x = true, + + /* Subsample increase */ + .inc_x_odd = 3, + .inc_x_even = 1, + .inc_y_odd = 3, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 30 }, + { 1, 30 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, + /* 1280x720 (HD) */ + { + /* Horizontal */ + .crop_start_x = 16, + .offset_x = 8, + .output_size_x = 1280, + .crop_end_x = 2607, + .hts = 1912, + + /* Vertical */ + .crop_start_y = 254, + .offset_y = 2, + .output_size_y = 720, + .crop_end_y = 1701, + .vts = 1496, + + /* Binning */ + .binning_x = true, + + /* Subsample increase */ + .inc_x_odd = 3, + .inc_x_even = 1, + .inc_y_odd = 3, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 30 }, + { 1, 30 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, + /* 640x480 (VGA) */ + { + /* Horizontal */ + .crop_start_x = 0, + .offset_x = 8, + .output_size_x = 640, + .crop_end_x = 2623, + .hts = 1896, + + /* Vertical */ + .crop_start_y = 0, + .offset_y = 2, + .output_size_y = 480, + .crop_end_y = 1953, + .vts = 984, + + /* Binning */ + .binning_x = true, + + /* Subsample increase */ + .inc_x_odd = 7, + .inc_x_even = 1, + .inc_y_odd = 7, + .inc_y_even = 1, + + /* Frame Interval */ + .frame_interval = { + { 1, 30 }, + { 1, 30 }, + }, + + /* PLL */ + .pll1_config = { + &ov5648_pll1_config_native_8_bits, + &ov5648_pll1_config_native_10_bits, + }, + .pll2_config = &ov5648_pll2_config_native, + }, +}; + +static const u32 ov5648_mbus_codes[] = { + MEDIA_BUS_FMT_SBGGR8_1X8, + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + +static const struct ov5648_register_value ov5648_init_sequence[] = { + /* PSRAM */ + { OV5648_PSRAM_CTRL1_REG, 0x0d }, + { OV5648_PSRAM_CTRLF_REG, 0xf5 }, +}; + +static const s64 ov5648_link_freq_menu[] = { + 210000000, + 168000000, +}; + +static const char *const ov5648_test_pattern_menu[] = { + "Disabled", + "Random data", + "Color bars", + "Color bars with rolling bar", + "Color squares", + "Color squares with rolling bar" +}; + +static const u8 ov5648_test_pattern_bits[] = { + 0, + OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_RANDOM_DATA, + OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS, + OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_ROLLING_BAR_EN | + OV5648_ISP_CTRL3D_PATTERN_COLOR_BARS, + OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES, + OV5648_ISP_CTRL3D_PATTERN_EN | OV5648_ISP_CTRL3D_ROLLING_BAR_EN | + OV5648_ISP_CTRL3D_PATTERN_COLOR_SQUARES, +}; + +/* Input/Output */ + +static int ov5648_read(struct ov5648_sensor *sensor, u16 address, u8 *value) +{ + unsigned char data[2] = { address >> 8, address & 0xff }; + struct i2c_client *client = sensor->i2c_client; + int ret; + + ret = i2c_master_send(client, data, sizeof(data)); + if (ret < 0) { + dev_dbg(&client->dev, "i2c send error at address %#04x\n", + address); + return ret; + } + + ret = i2c_master_recv(client, value, 1); + if (ret < 0) { + dev_dbg(&client->dev, "i2c recv error at address %#04x\n", + address); + return ret; + } + + return 0; +} + +static int ov5648_write(struct ov5648_sensor *sensor, u16 address, u8 value) +{ + unsigned char data[3] = { address >> 8, address & 0xff, value }; + struct i2c_client *client = sensor->i2c_client; + int ret; + + ret = i2c_master_send(client, data, sizeof(data)); + if (ret < 0) { + dev_dbg(&client->dev, "i2c send error at address %#04x\n", + address); + return ret; + } + + return 0; +} + +static int ov5648_write_sequence(struct ov5648_sensor *sensor, + const struct ov5648_register_value *sequence, + unsigned int sequence_count) +{ + unsigned int i; + int ret = 0; + + for (i = 0; i < sequence_count; i++) { + ret = ov5648_write(sensor, sequence[i].address, + sequence[i].value); + if (ret) + break; + + if (sequence[i].delay_ms) + msleep(sequence[i].delay_ms); + } + + return ret; +} + +static int ov5648_update_bits(struct ov5648_sensor *sensor, u16 address, + u8 mask, u8 bits) +{ + u8 value = 0; + int ret; + + ret = ov5648_read(sensor, address, &value); + if (ret) + return ret; + + value &= ~mask; + value |= bits; + + ret = ov5648_write(sensor, address, value); + if (ret) + return ret; + + return 0; +} + +/* Sensor */ + +static int ov5648_sw_reset(struct ov5648_sensor *sensor) +{ + return ov5648_write(sensor, OV5648_SW_RESET_REG, OV5648_SW_RESET_RESET); +} + +static int ov5648_sw_standby(struct ov5648_sensor *sensor, int standby) +{ + u8 value = 0; + + if (!standby) + value = OV5648_SW_STANDBY_STREAM_ON; + + return ov5648_write(sensor, OV5648_SW_STANDBY_REG, value); +} + +static int ov5648_chip_id_check(struct ov5648_sensor *sensor) +{ + u16 regs[] = { OV5648_CHIP_ID_H_REG, OV5648_CHIP_ID_L_REG }; + u8 values[] = { OV5648_CHIP_ID_H_VALUE, OV5648_CHIP_ID_L_VALUE }; + unsigned int i; + u8 value; + int ret; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + ret = ov5648_read(sensor, regs[i], &value); + if (ret < 0) + return ret; + + if (value != values[i]) { + dev_err(sensor->dev, + "chip id value mismatch: %#x instead of %#x\n", + value, values[i]); + return -EINVAL; + } + } + + return 0; +} + +static int ov5648_avdd_internal_power(struct ov5648_sensor *sensor, int on) +{ + return ov5648_write(sensor, OV5648_A_PWC_PK_O0_REG, + on ? 0 : OV5648_A_PWC_PK_O0_BP_REGULATOR_N); +} + +static int ov5648_pad_configure(struct ov5648_sensor *sensor) +{ + int ret; + + /* Configure pads as input. */ + + ret = ov5648_write(sensor, OV5648_PAD_OEN1_REG, 0); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_PAD_OEN2_REG, 0); + if (ret) + return ret; + + /* Disable FREX pin. */ + + return ov5648_write(sensor, OV5648_PAD_PK_REG, + OV5648_PAD_PK_DRIVE_STRENGTH_1X | + OV5648_PAD_PK_FREX_N); +} + +static int ov5648_mipi_configure(struct ov5648_sensor *sensor) +{ + struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + &sensor->endpoint.bus.mipi_csi2; + unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; + int ret; + + ret = ov5648_write(sensor, OV5648_MIPI_CTRL0_REG, + OV5648_MIPI_CTRL0_CLK_LANE_AUTOGATE | + OV5648_MIPI_CTRL0_LANE_SELECT_LANE1 | + OV5648_MIPI_CTRL0_IDLE_LP11); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_MIPI_SC_CTRL0_REG, + OV5648_MIPI_SC_CTRL0_MIPI_LANES(lanes_count) | + OV5648_MIPI_SC_CTRL0_PHY_LP_RX_PD | + OV5648_MIPI_SC_CTRL0_MIPI_EN); +} + +static int ov5648_black_level_configure(struct ov5648_sensor *sensor) +{ + int ret; + + /* Up to 6 lines are available for black level calibration. */ + + ret = ov5648_write(sensor, OV5648_BLC_CTRL1_REG, + OV5648_BLC_CTRL1_START_LINE(2)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_BLC_CTRL2_REG, + OV5648_BLC_CTRL2_AUTO_EN | + OV5648_BLC_CTRL2_RESET_FRAME_NUM(5)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_BLC_LINE_NUM_REG, + OV5648_BLC_LINE_NUM(4)); + if (ret) + return ret; + + return ov5648_update_bits(sensor, OV5648_BLC_CTRL5_REG, + OV5648_BLC_CTRL5_UPDATE_EN, + OV5648_BLC_CTRL5_UPDATE_EN); +} + +static int ov5648_isp_configure(struct ov5648_sensor *sensor) +{ + u8 bits; + int ret; + + /* Enable black and white level correction. */ + bits = OV5648_ISP_CTRL0_BLACK_CORRECT_EN | + OV5648_ISP_CTRL0_WHITE_CORRECT_EN; + + ret = ov5648_update_bits(sensor, OV5648_ISP_CTRL0_REG, bits, bits); + if (ret) + return ret; + + /* Enable AWB. */ + ret = ov5648_write(sensor, OV5648_ISP_CTRL1_REG, + OV5648_ISP_CTRL1_AWB_EN); + if (ret) + return ret; + + /* Enable AWB gain and windowing. */ + ret = ov5648_write(sensor, OV5648_ISP_CTRL2_REG, + OV5648_ISP_CTRL2_WIN_EN | + OV5648_ISP_CTRL2_AWB_GAIN_EN); + if (ret) + return ret; + + /* Enable buffering and auto-binning. */ + ret = ov5648_write(sensor, OV5648_ISP_CTRL3_REG, + OV5648_ISP_CTRL3_BUF_EN | + OV5648_ISP_CTRL3_BIN_AUTO_EN); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_ISP_CTRL4_REG, 0); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_ISP_CTRL1F_REG, + OV5648_ISP_CTRL1F_OUTPUT_EN); + if (ret) + return ret; + + /* Enable post-binning filters. */ + ret = ov5648_write(sensor, OV5648_ISP_CTRL4B_REG, + OV5648_ISP_CTRL4B_POST_BIN_H_EN | + OV5648_ISP_CTRL4B_POST_BIN_V_EN); + if (ret) + return ret; + + /* Disable debanding and night mode. Debug bit seems necessary. */ + ret = ov5648_write(sensor, OV5648_AEC_CTRL0_REG, + OV5648_AEC_CTRL0_DEBUG | + OV5648_AEC_CTRL0_START_SEL_EN); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_MANUAL_CTRL_REG, + OV5648_MANUAL_CTRL_FRAME_DELAY(1)); +} + +static unsigned long ov5648_mode_pll1_rate(struct ov5648_sensor *sensor, + const struct ov5648_pll1_config *config) +{ + unsigned long xvclk_rate; + unsigned long pll1_rate; + + xvclk_rate = clk_get_rate(sensor->xvclk); + pll1_rate = xvclk_rate * config->pll_mul; + + switch (config->pll_pre_div) { + case 5: + pll1_rate *= 3; + pll1_rate /= 2; + break; + case 7: + pll1_rate *= 5; + pll1_rate /= 2; + break; + default: + pll1_rate /= config->pll_pre_div; + break; + } + + return pll1_rate; +} + +static int ov5648_mode_pll1_configure(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode, + u32 mbus_code) +{ + const struct ov5648_pll1_config *config; + u8 value; + int ret; + + value = OV5648_PLL_CTRL0_PLL_CHARGE_PUMP(1); + + switch (mbus_code) { + case MEDIA_BUS_FMT_SBGGR8_1X8: + config = mode->pll1_config[0]; + value |= OV5648_PLL_CTRL0_BITS(8); + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + config = mode->pll1_config[1]; + value |= OV5648_PLL_CTRL0_BITS(10); + break; + default: + return -EINVAL; + } + + ret = ov5648_write(sensor, OV5648_PLL_CTRL0_REG, value); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_PLL_DIV_REG, + OV5648_PLL_DIV_ROOT_DIV(config->root_div) | + OV5648_PLL_DIV_PLL_PRE_DIV(config->pll_pre_div)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_PLL_MUL_REG, + OV5648_PLL_MUL(config->pll_mul)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_PLL_CTRL1_REG, + OV5648_PLL_CTRL1_SYS_DIV(config->sys_div) | + OV5648_PLL_CTRL1_MIPI_DIV(config->mipi_div)); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_SRB_CTRL_REG, + OV5648_SRB_CTRL_SCLK_DIV(config->sclk_div) | + OV5648_SRB_CTRL_SCLK_ARBITER_EN); +} + +static int ov5648_mode_pll2_configure(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode) +{ + const struct ov5648_pll2_config *config = mode->pll2_config; + int ret; + + ret = ov5648_write(sensor, OV5648_PLLS_DIV_REG, + OV5648_PLLS_DIV_PLLS_PRE_DIV(config->plls_pre_div) | + OV5648_PLLS_DIV_PLLS_DIV_R(config->plls_div_r) | + OV5648_PLLS_DIV_PLLS_SEL_DIV(config->sel_div)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_PLLS_MUL_REG, + OV5648_PLLS_MUL(config->plls_mul)); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_PLLS_CTRL_REG, + OV5648_PLLS_CTRL_PLL_CHARGE_PUMP(1) | + OV5648_PLLS_CTRL_SYS_DIV(config->sys_div)); +} + +static int ov5648_mode_configure(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode, u32 mbus_code) +{ + int ret; + + /* Crop Start X */ + + ret = ov5648_write(sensor, OV5648_CROP_START_X_H_REG, + OV5648_CROP_START_X_H(mode->crop_start_x)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_CROP_START_X_L_REG, + OV5648_CROP_START_X_L(mode->crop_start_x)); + if (ret) + return ret; + + /* Offset X */ + + ret = ov5648_write(sensor, OV5648_OFFSET_X_H_REG, + OV5648_OFFSET_X_H(mode->offset_x)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_OFFSET_X_L_REG, + OV5648_OFFSET_X_L(mode->offset_x)); + if (ret) + return ret; + + /* Output Size X */ + + ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_X_H_REG, + OV5648_OUTPUT_SIZE_X_H(mode->output_size_x)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_X_L_REG, + OV5648_OUTPUT_SIZE_X_L(mode->output_size_x)); + if (ret) + return ret; + + /* Crop End X */ + + ret = ov5648_write(sensor, OV5648_CROP_END_X_H_REG, + OV5648_CROP_END_X_H(mode->crop_end_x)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_CROP_END_X_L_REG, + OV5648_CROP_END_X_L(mode->crop_end_x)); + if (ret) + return ret; + + /* Horizontal Total Size */ + + ret = ov5648_write(sensor, OV5648_HTS_H_REG, OV5648_HTS_H(mode->hts)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_HTS_L_REG, OV5648_HTS_L(mode->hts)); + if (ret) + return ret; + + /* Crop Start Y */ + + ret = ov5648_write(sensor, OV5648_CROP_START_Y_H_REG, + OV5648_CROP_START_Y_H(mode->crop_start_y)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_CROP_START_Y_L_REG, + OV5648_CROP_START_Y_L(mode->crop_start_y)); + if (ret) + return ret; + + /* Offset Y */ + + ret = ov5648_write(sensor, OV5648_OFFSET_Y_H_REG, + OV5648_OFFSET_Y_H(mode->offset_y)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_OFFSET_Y_L_REG, + OV5648_OFFSET_Y_L(mode->offset_y)); + if (ret) + return ret; + + /* Output Size Y */ + + ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_Y_H_REG, + OV5648_OUTPUT_SIZE_Y_H(mode->output_size_y)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_OUTPUT_SIZE_Y_L_REG, + OV5648_OUTPUT_SIZE_Y_L(mode->output_size_y)); + if (ret) + return ret; + + /* Crop End Y */ + + ret = ov5648_write(sensor, OV5648_CROP_END_Y_H_REG, + OV5648_CROP_END_Y_H(mode->crop_end_y)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_CROP_END_Y_L_REG, + OV5648_CROP_END_Y_L(mode->crop_end_y)); + if (ret) + return ret; + + /* Vertical Total Size */ + + ret = ov5648_write(sensor, OV5648_VTS_H_REG, OV5648_VTS_H(mode->vts)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_VTS_L_REG, OV5648_VTS_L(mode->vts)); + if (ret) + return ret; + + /* Flip/Mirror/Binning */ + + /* + * A debug bit is enabled by default and needs to be cleared for + * subsampling to work. + */ + ret = ov5648_update_bits(sensor, OV5648_TC20_REG, + OV5648_TC20_DEBUG | + OV5648_TC20_BINNING_VERT_EN, + mode->binning_y ? OV5648_TC20_BINNING_VERT_EN : + 0); + if (ret) + return ret; + + ret = ov5648_update_bits(sensor, OV5648_TC21_REG, + OV5648_TC21_BINNING_HORZ_EN, + mode->binning_x ? OV5648_TC21_BINNING_HORZ_EN : + 0); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_SUB_INC_X_REG, + OV5648_SUB_INC_X_ODD(mode->inc_x_odd) | + OV5648_SUB_INC_X_EVEN(mode->inc_x_even)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_SUB_INC_Y_REG, + OV5648_SUB_INC_Y_ODD(mode->inc_y_odd) | + OV5648_SUB_INC_Y_EVEN(mode->inc_y_even)); + if (ret) + return ret; + + /* PLLs */ + + ret = ov5648_mode_pll1_configure(sensor, mode, mbus_code); + if (ret) + return ret; + + ret = ov5648_mode_pll2_configure(sensor, mode); + if (ret) + return ret; + + /* Extra registers */ + + if (mode->register_values) { + ret = ov5648_write_sequence(sensor, mode->register_values, + mode->register_values_count); + if (ret) + return ret; + } + + return 0; +} + +static unsigned long ov5648_mode_mipi_clk_rate(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode, + u32 mbus_code) +{ + const struct ov5648_pll1_config *config; + unsigned long pll1_rate; + + switch (mbus_code) { + case MEDIA_BUS_FMT_SBGGR8_1X8: + config = mode->pll1_config[0]; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + config = mode->pll1_config[1]; + break; + default: + return 0; + } + + pll1_rate = ov5648_mode_pll1_rate(sensor, config); + + return pll1_rate / config->sys_div / config->mipi_div / 2; +} + +/* Exposure */ + +static int ov5648_exposure_auto_configure(struct ov5648_sensor *sensor, + bool enable) +{ + return ov5648_update_bits(sensor, OV5648_MANUAL_CTRL_REG, + OV5648_MANUAL_CTRL_AEC_MANUAL_EN, + enable ? 0 : OV5648_MANUAL_CTRL_AEC_MANUAL_EN); +} + +static int ov5648_exposure_configure(struct ov5648_sensor *sensor, u32 exposure) +{ + struct ov5648_ctrls *ctrls = &sensor->ctrls; + int ret; + + if (ctrls->exposure_auto->val != V4L2_EXPOSURE_MANUAL) + return -EINVAL; + + ret = ov5648_write(sensor, OV5648_EXPOSURE_CTRL_HH_REG, + OV5648_EXPOSURE_CTRL_HH(exposure)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_EXPOSURE_CTRL_H_REG, + OV5648_EXPOSURE_CTRL_H(exposure)); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_EXPOSURE_CTRL_L_REG, + OV5648_EXPOSURE_CTRL_L(exposure)); +} + +static int ov5648_exposure_value(struct ov5648_sensor *sensor, + u32 *exposure) +{ + u8 exposure_hh = 0, exposure_h = 0, exposure_l = 0; + int ret; + + ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_HH_REG, &exposure_hh); + if (ret) + return ret; + + ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_H_REG, &exposure_h); + if (ret) + return ret; + + ret = ov5648_read(sensor, OV5648_EXPOSURE_CTRL_L_REG, &exposure_l); + if (ret) + return ret; + + *exposure = OV5648_EXPOSURE_CTRL_HH_VALUE((u32)exposure_hh) | + OV5648_EXPOSURE_CTRL_H_VALUE((u32)exposure_h) | + OV5648_EXPOSURE_CTRL_L_VALUE((u32)exposure_l); + + return 0; +} + +/* Gain */ + +static int ov5648_gain_auto_configure(struct ov5648_sensor *sensor, bool enable) +{ + return ov5648_update_bits(sensor, OV5648_MANUAL_CTRL_REG, + OV5648_MANUAL_CTRL_AGC_MANUAL_EN, + enable ? 0 : OV5648_MANUAL_CTRL_AGC_MANUAL_EN); +} + +static int ov5648_gain_configure(struct ov5648_sensor *sensor, u32 gain) +{ + struct ov5648_ctrls *ctrls = &sensor->ctrls; + int ret; + + if (ctrls->gain_auto->val) + return -EINVAL; + + ret = ov5648_write(sensor, OV5648_GAIN_CTRL_H_REG, + OV5648_GAIN_CTRL_H(gain)); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_GAIN_CTRL_L_REG, + OV5648_GAIN_CTRL_L(gain)); +} + +static int ov5648_gain_value(struct ov5648_sensor *sensor, u32 *gain) +{ + u8 gain_h = 0, gain_l = 0; + int ret; + + ret = ov5648_read(sensor, OV5648_GAIN_CTRL_H_REG, &gain_h); + if (ret) + return ret; + + ret = ov5648_read(sensor, OV5648_GAIN_CTRL_L_REG, &gain_l); + if (ret) + return ret; + + *gain = OV5648_GAIN_CTRL_H_VALUE((u32)gain_h) | + OV5648_GAIN_CTRL_L_VALUE((u32)gain_l); + + return 0; +} + +/* White Balance */ + +static int ov5648_white_balance_auto_configure(struct ov5648_sensor *sensor, + bool enable) +{ + return ov5648_write(sensor, OV5648_AWB_CTRL_REG, + enable ? 0 : OV5648_AWB_CTRL_GAIN_MANUAL_EN); +} + +static int ov5648_white_balance_configure(struct ov5648_sensor *sensor, + u32 red_balance, u32 blue_balance) +{ + struct ov5648_ctrls *ctrls = &sensor->ctrls; + int ret; + + if (ctrls->white_balance_auto->val) + return -EINVAL; + + ret = ov5648_write(sensor, OV5648_GAIN_RED_MAN_H_REG, + OV5648_GAIN_RED_MAN_H(red_balance)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_GAIN_RED_MAN_L_REG, + OV5648_GAIN_RED_MAN_L(red_balance)); + if (ret) + return ret; + + ret = ov5648_write(sensor, OV5648_GAIN_BLUE_MAN_H_REG, + OV5648_GAIN_BLUE_MAN_H(blue_balance)); + if (ret) + return ret; + + return ov5648_write(sensor, OV5648_GAIN_BLUE_MAN_L_REG, + OV5648_GAIN_BLUE_MAN_L(blue_balance)); +} + +/* Flip */ + +static int ov5648_flip_vert_configure(struct ov5648_sensor *sensor, bool enable) +{ + u8 bits = OV5648_TC20_FLIP_VERT_ISP_EN | + OV5648_TC20_FLIP_VERT_SENSOR_EN; + + return ov5648_update_bits(sensor, OV5648_TC20_REG, bits, + enable ? bits : 0); +} + +static int ov5648_flip_horz_configure(struct ov5648_sensor *sensor, bool enable) +{ + u8 bits = OV5648_TC21_FLIP_HORZ_ISP_EN | + OV5648_TC21_FLIP_HORZ_SENSOR_EN; + + return ov5648_update_bits(sensor, OV5648_TC21_REG, bits, + enable ? bits : 0); +} + +/* Test Pattern */ + +static int ov5648_test_pattern_configure(struct ov5648_sensor *sensor, + unsigned int index) +{ + if (index >= ARRAY_SIZE(ov5648_test_pattern_bits)) + return -EINVAL; + + return ov5648_write(sensor, OV5648_ISP_CTRL3D_REG, + ov5648_test_pattern_bits[index]); +} + +/* State */ + +static int ov5648_state_mipi_configure(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode, + u32 mbus_code) +{ + struct ov5648_ctrls *ctrls = &sensor->ctrls; + struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + &sensor->endpoint.bus.mipi_csi2; + unsigned long mipi_clk_rate; + unsigned int bits_per_sample; + unsigned int lanes_count; + unsigned int i, j; + s64 mipi_pixel_rate; + + mipi_clk_rate = ov5648_mode_mipi_clk_rate(sensor, mode, mbus_code); + if (!mipi_clk_rate) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(ov5648_link_freq_menu); i++) { + s64 freq = ov5648_link_freq_menu[i]; + + if (freq == mipi_clk_rate) + break; + } + + for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) { + u64 freq = sensor->endpoint.link_frequencies[j]; + + if (freq == mipi_clk_rate) + break; + } + + if (i == ARRAY_SIZE(ov5648_link_freq_menu)) { + dev_err(sensor->dev, + "failed to find %lu clk rate in link freq\n", + mipi_clk_rate); + } else if (j == sensor->endpoint.nr_of_link_frequencies) { + dev_err(sensor->dev, + "failed to find %lu clk rate in endpoint link-frequencies\n", + mipi_clk_rate); + } else { + __v4l2_ctrl_s_ctrl(ctrls->link_freq, i); + } + + switch (mbus_code) { + case MEDIA_BUS_FMT_SBGGR8_1X8: + bits_per_sample = 8; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + bits_per_sample = 10; + break; + default: + return -EINVAL; + } + + lanes_count = bus_mipi_csi2->num_data_lanes; + mipi_pixel_rate = mipi_clk_rate * 2 * lanes_count / bits_per_sample; + + __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mipi_pixel_rate); + + return 0; +} + +static int ov5648_state_configure(struct ov5648_sensor *sensor, + const struct ov5648_mode *mode, + u32 mbus_code) +{ + int ret; + + if (sensor->state.streaming) + return -EBUSY; + + /* State will be configured at first power on otherwise. */ + if (pm_runtime_enabled(sensor->dev) && + !pm_runtime_suspended(sensor->dev)) { + ret = ov5648_mode_configure(sensor, mode, mbus_code); + if (ret) + return ret; + } + + ret = ov5648_state_mipi_configure(sensor, mode, mbus_code); + if (ret) + return ret; + + sensor->state.mode = mode; + sensor->state.mbus_code = mbus_code; + + return 0; +} + +static int ov5648_state_init(struct ov5648_sensor *sensor) +{ + return ov5648_state_configure(sensor, &ov5648_modes[0], + ov5648_mbus_codes[0]); +} + +/* Sensor Base */ + +static int ov5648_sensor_init(struct ov5648_sensor *sensor) +{ + int ret; + + ret = ov5648_sw_reset(sensor); + if (ret) { + dev_err(sensor->dev, "failed to perform sw reset\n"); + return ret; + } + + ret = ov5648_sw_standby(sensor, 1); + if (ret) { + dev_err(sensor->dev, "failed to set sensor standby\n"); + return ret; + } + + ret = ov5648_chip_id_check(sensor); + if (ret) { + dev_err(sensor->dev, "failed to check sensor chip id\n"); + return ret; + } + + ret = ov5648_avdd_internal_power(sensor, !sensor->avdd); + if (ret) { + dev_err(sensor->dev, "failed to set internal avdd power\n"); + return ret; + } + + ret = ov5648_write_sequence(sensor, ov5648_init_sequence, + ARRAY_SIZE(ov5648_init_sequence)); + if (ret) { + dev_err(sensor->dev, "failed to write init sequence\n"); + return ret; + } + + ret = ov5648_pad_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure pad\n"); + return ret; + } + + ret = ov5648_mipi_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure MIPI\n"); + return ret; + } + + ret = ov5648_isp_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure ISP\n"); + return ret; + } + + ret = ov5648_black_level_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure black level\n"); + return ret; + } + + /* Configure current mode. */ + ret = ov5648_state_configure(sensor, sensor->state.mode, + sensor->state.mbus_code); + if (ret) { + dev_err(sensor->dev, "failed to configure state\n"); + return ret; + } + + return 0; +} + +static int ov5648_sensor_power(struct ov5648_sensor *sensor, bool on) +{ + /* Keep initialized to zero for disable label. */ + int ret = 0; + + /* + * General notes about the power sequence: + * - power-down GPIO must be active (low) during power-on; + * - reset GPIO state does not matter during power-on; + * - XVCLK must be provided 1 ms before register access; + * - 10 ms are needed between power-down deassert and register access. + */ + + /* Note that regulator-and-GPIO-based power is untested. */ + if (on) { + gpiod_set_value_cansleep(sensor->reset, 1); + gpiod_set_value_cansleep(sensor->powerdown, 1); + + ret = regulator_enable(sensor->dovdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable DOVDD regulator\n"); + goto disable; + } + + if (sensor->avdd) { + ret = regulator_enable(sensor->avdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable AVDD regulator\n"); + goto disable; + } + } + + ret = regulator_enable(sensor->dvdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable DVDD regulator\n"); + goto disable; + } + + /* According to OV5648 power up diagram. */ + usleep_range(5000, 10000); + + ret = clk_prepare_enable(sensor->xvclk); + if (ret) { + dev_err(sensor->dev, "failed to enable XVCLK clock\n"); + goto disable; + } + + gpiod_set_value_cansleep(sensor->reset, 0); + gpiod_set_value_cansleep(sensor->powerdown, 0); + + usleep_range(20000, 25000); + } else { +disable: + gpiod_set_value_cansleep(sensor->powerdown, 1); + gpiod_set_value_cansleep(sensor->reset, 1); + + clk_disable_unprepare(sensor->xvclk); + + regulator_disable(sensor->dvdd); + + if (sensor->avdd) + regulator_disable(sensor->avdd); + + regulator_disable(sensor->dovdd); + } + + return ret; +} + +/* Controls */ + +static int ov5648_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *subdev = ov5648_ctrl_subdev(ctrl); + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct ov5648_ctrls *ctrls = &sensor->ctrls; + int ret; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_AUTO: + ret = ov5648_exposure_value(sensor, &ctrls->exposure->val); + if (ret) + return ret; + break; + case V4L2_CID_AUTOGAIN: + ret = ov5648_gain_value(sensor, &ctrls->gain->val); + if (ret) + return ret; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ov5648_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *subdev = ov5648_ctrl_subdev(ctrl); + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct ov5648_ctrls *ctrls = &sensor->ctrls; + unsigned int index; + bool enable; + int ret; + + /* Wait for the sensor to be on before setting controls. */ + if (pm_runtime_suspended(sensor->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_AUTO: + enable = ctrl->val == V4L2_EXPOSURE_AUTO; + + ret = ov5648_exposure_auto_configure(sensor, enable); + if (ret) + return ret; + + if (!enable && ctrls->exposure->is_new) { + ret = ov5648_exposure_configure(sensor, + ctrls->exposure->val); + if (ret) + return ret; + } + break; + case V4L2_CID_AUTOGAIN: + enable = !!ctrl->val; + + ret = ov5648_gain_auto_configure(sensor, enable); + if (ret) + return ret; + + if (!enable) { + ret = ov5648_gain_configure(sensor, ctrls->gain->val); + if (ret) + return ret; + } + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + enable = !!ctrl->val; + + ret = ov5648_white_balance_auto_configure(sensor, enable); + if (ret) + return ret; + + if (!enable) { + ret = ov5648_white_balance_configure(sensor, + ctrls->red_balance->val, + ctrls->blue_balance->val); + if (ret) + return ret; + } + break; + case V4L2_CID_HFLIP: + enable = !!ctrl->val; + return ov5648_flip_horz_configure(sensor, enable); + case V4L2_CID_VFLIP: + enable = !!ctrl->val; + return ov5648_flip_vert_configure(sensor, enable); + case V4L2_CID_TEST_PATTERN: + index = (unsigned int)ctrl->val; + return ov5648_test_pattern_configure(sensor, index); + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops ov5648_ctrl_ops = { + .g_volatile_ctrl = ov5648_g_volatile_ctrl, + .s_ctrl = ov5648_s_ctrl, +}; + +static int ov5648_ctrls_init(struct ov5648_sensor *sensor) +{ + struct ov5648_ctrls *ctrls = &sensor->ctrls; + struct v4l2_ctrl_handler *handler = &ctrls->handler; + const struct v4l2_ctrl_ops *ops = &ov5648_ctrl_ops; + int ret; + + v4l2_ctrl_handler_init(handler, 32); + + /* Use our mutex for ctrl locking. */ + handler->lock = &sensor->mutex; + + /* Exposure */ + + ctrls->exposure_auto = v4l2_ctrl_new_std_menu(handler, ops, + V4L2_CID_EXPOSURE_AUTO, + V4L2_EXPOSURE_MANUAL, 0, + V4L2_EXPOSURE_AUTO); + + ctrls->exposure = v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, + 16, 1048575, 16, 512); + + v4l2_ctrl_auto_cluster(2, &ctrls->exposure_auto, 1, true); + + /* Gain */ + + ctrls->gain_auto = + v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTOGAIN, 0, 1, 1, 1); + + ctrls->gain = v4l2_ctrl_new_std(handler, ops, V4L2_CID_GAIN, 16, 1023, + 16, 16); + + v4l2_ctrl_auto_cluster(2, &ctrls->gain_auto, 0, true); + + /* White Balance */ + + ctrls->white_balance_auto = + v4l2_ctrl_new_std(handler, ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, + 1, 1, 1); + + ctrls->red_balance = v4l2_ctrl_new_std(handler, ops, + V4L2_CID_RED_BALANCE, 0, 4095, + 1, 1024); + + ctrls->blue_balance = v4l2_ctrl_new_std(handler, ops, + V4L2_CID_BLUE_BALANCE, 0, 4095, + 1, 1024); + + v4l2_ctrl_auto_cluster(3, &ctrls->white_balance_auto, 0, false); + + /* Flip */ + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); + + /* Test Pattern */ + + v4l2_ctrl_new_std_menu_items(handler, ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov5648_test_pattern_menu) - 1, + 0, 0, ov5648_test_pattern_menu); + + /* MIPI CSI-2 */ + + ctrls->link_freq = + v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + ARRAY_SIZE(ov5648_link_freq_menu) - 1, + 0, ov5648_link_freq_menu); + + ctrls->pixel_rate = + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1, + INT_MAX, 1, 1); + + if (handler->error) { + ret = handler->error; + goto error_ctrls; + } + + ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; + ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; + + ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + sensor->subdev.ctrl_handler = handler; + + return 0; + +error_ctrls: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +/* Subdev Video Operations */ + +static int ov5648_s_stream(struct v4l2_subdev *subdev, int enable) +{ + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct ov5648_state *state = &sensor->state; + int ret; + + if (enable) { + ret = pm_runtime_get_sync(sensor->dev); + if (ret < 0) { + pm_runtime_put_noidle(sensor->dev); + return ret; + } + } + + mutex_lock(&sensor->mutex); + ret = ov5648_sw_standby(sensor, !enable); + mutex_unlock(&sensor->mutex); + + if (ret) + return ret; + + state->streaming = !!enable; + + if (!enable) + pm_runtime_put(sensor->dev); + + return 0; +} + +static int ov5648_g_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + const struct ov5648_mode *mode; + int ret = 0; + + mutex_lock(&sensor->mutex); + + mode = sensor->state.mode; + + switch (sensor->state.mbus_code) { + case MEDIA_BUS_FMT_SBGGR8_1X8: + interval->interval = mode->frame_interval[0]; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + interval->interval = mode->frame_interval[1]; + break; + default: + ret = -EINVAL; + } + + mutex_unlock(&sensor->mutex); + + return ret; +} + +static const struct v4l2_subdev_video_ops ov5648_subdev_video_ops = { + .s_stream = ov5648_s_stream, + .g_frame_interval = ov5648_g_frame_interval, + .s_frame_interval = ov5648_g_frame_interval, +}; + +/* Subdev Pad Operations */ + +static int ov5648_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_mbus_code_enum *code_enum) +{ + if (code_enum->index >= ARRAY_SIZE(ov5648_mbus_codes)) + return -EINVAL; + + code_enum->code = ov5648_mbus_codes[code_enum->index]; + + return 0; +} + +static void ov5648_mbus_format_fill(struct v4l2_mbus_framefmt *mbus_format, + u32 mbus_code, + const struct ov5648_mode *mode) +{ + mbus_format->width = mode->output_size_x; + mbus_format->height = mode->output_size_y; + mbus_format->code = mbus_code; + + mbus_format->field = V4L2_FIELD_NONE; + mbus_format->colorspace = V4L2_COLORSPACE_RAW; + mbus_format->ycbcr_enc = + V4L2_MAP_YCBCR_ENC_DEFAULT(mbus_format->colorspace); + mbus_format->quantization = V4L2_QUANTIZATION_FULL_RANGE; + mbus_format->xfer_func = + V4L2_MAP_XFER_FUNC_DEFAULT(mbus_format->colorspace); +} + +static int ov5648_get_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_format *format) +{ + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct v4l2_mbus_framefmt *mbus_format = &format->format; + + mutex_lock(&sensor->mutex); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + *mbus_format = *v4l2_subdev_get_try_format(subdev, config, + format->pad); + else + ov5648_mbus_format_fill(mbus_format, sensor->state.mbus_code, + sensor->state.mode); + + mutex_unlock(&sensor->mutex); + + return 0; +} + +static int ov5648_set_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_format *format) +{ + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct v4l2_mbus_framefmt *mbus_format = &format->format; + const struct ov5648_mode *mode; + u32 mbus_code = 0; + unsigned int index; + int ret = 0; + + mutex_lock(&sensor->mutex); + + if (sensor->state.streaming) { + ret = -EBUSY; + goto complete; + } + + /* Try to find requested mbus code. */ + for (index = 0; index < ARRAY_SIZE(ov5648_mbus_codes); index++) { + if (ov5648_mbus_codes[index] == mbus_format->code) { + mbus_code = mbus_format->code; + break; + } + } + + /* Fallback to default. */ + if (!mbus_code) + mbus_code = ov5648_mbus_codes[0]; + + /* Find the mode with nearest dimensions. */ + mode = v4l2_find_nearest_size(ov5648_modes, ARRAY_SIZE(ov5648_modes), + output_size_x, output_size_y, + mbus_format->width, mbus_format->height); + if (!mode) { + ret = -EINVAL; + goto complete; + } + + ov5648_mbus_format_fill(mbus_format, mbus_code, mode); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + *v4l2_subdev_get_try_format(subdev, config, format->pad) = + *mbus_format; + else if (sensor->state.mode != mode || + sensor->state.mbus_code != mbus_code) + ret = ov5648_state_configure(sensor, mode, mbus_code); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov5648_enum_frame_size(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_frame_size_enum *size_enum) +{ + const struct ov5648_mode *mode; + + if (size_enum->index >= ARRAY_SIZE(ov5648_modes)) + return -EINVAL; + + mode = &ov5648_modes[size_enum->index]; + + size_enum->min_width = size_enum->max_width = mode->output_size_x; + size_enum->min_height = size_enum->max_height = mode->output_size_y; + + return 0; +} + +static int ov5648_enum_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_frame_interval_enum *interval_enum) +{ + const struct ov5648_mode *mode = NULL; + unsigned int mode_index; + unsigned int interval_index; + + if (interval_enum->index > 0) + return -EINVAL; + + /* + * Multiple modes with the same dimensions may have different frame + * intervals, so look up each relevant mode. + */ + for (mode_index = 0, interval_index = 0; + mode_index < ARRAY_SIZE(ov5648_modes); mode_index++) { + mode = &ov5648_modes[mode_index]; + + if (mode->output_size_x == interval_enum->width && + mode->output_size_y == interval_enum->height) { + if (interval_index == interval_enum->index) + break; + + interval_index++; + } + } + + if (mode_index == ARRAY_SIZE(ov5648_modes)) + return -EINVAL; + + switch (interval_enum->code) { + case MEDIA_BUS_FMT_SBGGR8_1X8: + interval_enum->interval = mode->frame_interval[0]; + break; + case MEDIA_BUS_FMT_SBGGR10_1X10: + interval_enum->interval = mode->frame_interval[1]; + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_subdev_pad_ops ov5648_subdev_pad_ops = { + .enum_mbus_code = ov5648_enum_mbus_code, + .get_fmt = ov5648_get_fmt, + .set_fmt = ov5648_set_fmt, + .enum_frame_size = ov5648_enum_frame_size, + .enum_frame_interval = ov5648_enum_frame_interval, +}; + +static const struct v4l2_subdev_ops ov5648_subdev_ops = { + .video = &ov5648_subdev_video_ops, + .pad = &ov5648_subdev_pad_ops, +}; + +static int ov5648_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct ov5648_state *state = &sensor->state; + int ret = 0; + + mutex_lock(&sensor->mutex); + + if (state->streaming) { + ret = ov5648_sw_standby(sensor, true); + if (ret) + goto complete; + } + + ret = ov5648_sensor_power(sensor, false); + if (ret) + ov5648_sw_standby(sensor, false); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov5648_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + struct ov5648_state *state = &sensor->state; + int ret = 0; + + mutex_lock(&sensor->mutex); + + ret = ov5648_sensor_power(sensor, true); + if (ret) + goto complete; + + ret = ov5648_sensor_init(sensor); + if (ret) + goto error_power; + + ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); + if (ret) + goto error_power; + + if (state->streaming) { + ret = ov5648_sw_standby(sensor, false); + if (ret) + goto error_power; + } + + goto complete; + +error_power: + ov5648_sensor_power(sensor, false); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov5648_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct fwnode_handle *handle; + struct ov5648_sensor *sensor; + struct v4l2_subdev *subdev; + struct media_pad *pad; + unsigned long rate; + int ret; + + sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->dev = dev; + sensor->i2c_client = client; + + /* Graph Endpoint */ + + handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); + if (!handle) { + dev_err(dev, "unable to find endpoint node\n"); + return -EINVAL; + } + + sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY; + + ret = v4l2_fwnode_endpoint_alloc_parse(handle, &sensor->endpoint); + fwnode_handle_put(handle); + if (ret) { + dev_err(dev, "failed to parse endpoint node\n"); + return ret; + } + + /* GPIOs */ + + sensor->powerdown = devm_gpiod_get_optional(dev, "powerdown", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->powerdown)) { + ret = PTR_ERR(sensor->powerdown); + goto error_endpoint; + } + + sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(sensor->reset)) { + ret = PTR_ERR(sensor->reset); + goto error_endpoint; + } + + /* Regulators */ + + /* DVDD: digital core */ + sensor->dvdd = devm_regulator_get(dev, "dvdd"); + if (IS_ERR(sensor->dvdd)) { + dev_err(dev, "cannot get DVDD (digital core) regulator\n"); + ret = PTR_ERR(sensor->dvdd); + goto error_endpoint; + } + + /* DOVDD: digital I/O */ + sensor->dovdd = devm_regulator_get(dev, "dovdd"); + if (IS_ERR(sensor->dvdd)) { + dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n"); + ret = PTR_ERR(sensor->dvdd); + goto error_endpoint; + } + + /* AVDD: analog */ + sensor->avdd = devm_regulator_get_optional(dev, "avdd"); + if (IS_ERR(sensor->avdd)) { + dev_info(dev, "no AVDD regulator provided, using internal\n"); + sensor->avdd = NULL; + } + + /* External Clock */ + + sensor->xvclk = devm_clk_get(dev, NULL); + if (IS_ERR(sensor->xvclk)) { + dev_err(dev, "failed to get external clock\n"); + ret = PTR_ERR(sensor->xvclk); + goto error_endpoint; + } + + rate = clk_get_rate(sensor->xvclk); + if (rate != OV5648_XVCLK_RATE) { + dev_err(dev, "clock rate %lu Hz is unsupported\n", rate); + ret = -EINVAL; + goto error_endpoint; + } + + /* Subdev, entity and pad */ + + subdev = &sensor->subdev; + v4l2_i2c_subdev_init(subdev, client, &ov5648_subdev_ops); + + subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + subdev->entity.function = MEDIA_ENT_F_CAM_SENSOR; + + pad = &sensor->pad; + pad->flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&subdev->entity, 1, pad); + if (ret) + goto error_entity; + + /* Mutex */ + + mutex_init(&sensor->mutex); + + /* Sensor */ + + ret = ov5648_ctrls_init(sensor); + if (ret) + goto error_mutex; + + ret = ov5648_state_init(sensor); + if (ret) + goto error_ctrls; + + /* Runtime PM */ + + pm_runtime_enable(sensor->dev); + pm_runtime_set_suspended(sensor->dev); + + /* V4L2 subdev register */ + + ret = v4l2_async_register_subdev_sensor_common(subdev); + if (ret) + goto error_pm; + + return 0; + +error_pm: + pm_runtime_disable(sensor->dev); + +error_ctrls: + v4l2_ctrl_handler_free(&sensor->ctrls.handler); + +error_mutex: + mutex_destroy(&sensor->mutex); + +error_entity: + media_entity_cleanup(&sensor->subdev.entity); + +error_endpoint: + v4l2_fwnode_endpoint_free(&sensor->endpoint); + + return ret; +} + +static int ov5648_remove(struct i2c_client *client) +{ + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov5648_sensor *sensor = ov5648_subdev_sensor(subdev); + + v4l2_async_unregister_subdev(subdev); + pm_runtime_disable(sensor->dev); + v4l2_ctrl_handler_free(&sensor->ctrls.handler); + mutex_destroy(&sensor->mutex); + media_entity_cleanup(&subdev->entity); + + return 0; +} + +static const struct dev_pm_ops ov5648_pm_ops = { + SET_RUNTIME_PM_OPS(ov5648_suspend, ov5648_resume, NULL) +}; + +static const struct of_device_id ov5648_of_match[] = { + { .compatible = "ovti,ov5648" }, + { } +}; +MODULE_DEVICE_TABLE(of, ov5648_of_match); + +static struct i2c_driver ov5648_driver = { + .driver = { + .name = "ov5648", + .of_match_table = ov5648_of_match, + .pm = &ov5648_pm_ops, + }, + .probe_new = ov5648_probe, + .remove = ov5648_remove, +}; + +module_i2c_driver(ov5648_driver); + +MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>"); +MODULE_DESCRIPTION("V4L2 driver for the OmniVision OV5648 image sensor"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/ov5670.c b/drivers/media/i2c/ov5670.c index 148fd4e05029..866c8c2e8f59 100644 --- a/drivers/media/i2c/ov5670.c +++ b/drivers/media/i2c/ov5670.c @@ -2084,7 +2084,8 @@ static int ov5670_init_controls(struct ov5670 *ov5670) /* By default, V4L2_CID_PIXEL_RATE is read only */ ov5670->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5670_ctrl_ops, - V4L2_CID_PIXEL_RATE, 0, + V4L2_CID_PIXEL_RATE, + link_freq_configs[0].pixel_rate, link_freq_configs[0].pixel_rate, 1, link_freq_configs[0].pixel_rate); diff --git a/drivers/media/i2c/ov5675.c b/drivers/media/i2c/ov5675.c index 5e35808037ad..ae00d717e599 100644 --- a/drivers/media/i2c/ov5675.c +++ b/drivers/media/i2c/ov5675.c @@ -624,7 +624,7 @@ static int ov5675_set_ctrl_hflip(struct ov5675 *ov5675, u32 ctrl_val) return ov5675_write_reg(ov5675, OV5675_REG_FORMAT1, OV5675_REG_VALUE_08BIT, - ctrl_val ? val & ~BIT(3) : val); + ctrl_val ? val & ~BIT(3) : val | BIT(3)); } static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val) @@ -639,7 +639,7 @@ static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val) ret = ov5675_write_reg(ov5675, OV5675_REG_FORMAT1, OV5675_REG_VALUE_08BIT, - ctrl_val ? val | BIT(4) | BIT(5) : val); + ctrl_val ? val | BIT(4) | BIT(5) : val & ~BIT(4) & ~BIT(5)); if (ret) return ret; @@ -652,7 +652,7 @@ static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val) return ov5675_write_reg(ov5675, OV5675_REG_FORMAT2, OV5675_REG_VALUE_08BIT, - ctrl_val ? val | BIT(1) : val); + ctrl_val ? val | BIT(1) : val & ~BIT(1)); } static int ov5675_set_ctrl(struct v4l2_ctrl *ctrl) diff --git a/drivers/media/i2c/ov6650.c b/drivers/media/i2c/ov6650.c index d73f9f540932..85dd13694bd2 100644 --- a/drivers/media/i2c/ov6650.c +++ b/drivers/media/i2c/ov6650.c @@ -22,13 +22,13 @@ */ #include <linux/bitops.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/slab.h> #include <linux/v4l2-mediabus.h> #include <linux/module.h> -#include <media/v4l2-clk.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> @@ -194,7 +194,7 @@ struct ov6650 { struct v4l2_ctrl *blue; struct v4l2_ctrl *red; }; - struct v4l2_clk *clk; + struct clk *clk; bool half_scale; /* scale down output by 2 */ struct v4l2_rect rect; /* sensor cropping window */ struct v4l2_fract tpf; /* as requested with s_frame_interval */ @@ -459,9 +459,9 @@ static int ov6650_s_power(struct v4l2_subdev *sd, int on) int ret = 0; if (on) - ret = v4l2_clk_enable(priv->clk); + ret = clk_prepare_enable(priv->clk); else - v4l2_clk_disable(priv->clk); + clk_disable_unprepare(priv->clk); return ret; } @@ -821,14 +821,14 @@ static int ov6650_video_probe(struct v4l2_subdev *sd) u8 pidh, pidl, midh, midl; int i, ret = 0; - priv->clk = v4l2_clk_get(&client->dev, NULL); + priv->clk = devm_clk_get(&client->dev, NULL); if (IS_ERR(priv->clk)) { ret = PTR_ERR(priv->clk); - dev_err(&client->dev, "v4l2_clk request err: %d\n", ret); + dev_err(&client->dev, "clk request err: %d\n", ret); return ret; } - rate = v4l2_clk_get_rate(priv->clk); + rate = clk_get_rate(priv->clk); for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) { if (rate != ov6650_xclk[i].rate) continue; @@ -839,8 +839,8 @@ static int ov6650_video_probe(struct v4l2_subdev *sd) break; } for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) { - ret = v4l2_clk_set_rate(priv->clk, ov6650_xclk[i].rate); - if (ret || v4l2_clk_get_rate(priv->clk) != ov6650_xclk[i].rate) + ret = clk_set_rate(priv->clk, ov6650_xclk[i].rate); + if (ret || clk_get_rate(priv->clk) != ov6650_xclk[i].rate) continue; xclk = &ov6650_xclk[i]; @@ -852,12 +852,12 @@ static int ov6650_video_probe(struct v4l2_subdev *sd) dev_err(&client->dev, "unable to get supported clock rate\n"); if (!ret) ret = -EINVAL; - goto eclkput; + return ret; } ret = ov6650_s_power(sd, 1); if (ret < 0) - goto eclkput; + return ret; msleep(20); @@ -899,11 +899,6 @@ static int ov6650_video_probe(struct v4l2_subdev *sd) done: ov6650_s_power(sd, 0); - if (!ret) - return 0; -eclkput: - v4l2_clk_put(priv->clk); - return ret; } @@ -1089,7 +1084,6 @@ static int ov6650_remove(struct i2c_client *client) { struct ov6650 *priv = to_ov6650(client); - v4l2_clk_put(priv->clk); v4l2_async_unregister_subdev(&priv->subdev); v4l2_ctrl_handler_free(&priv->hdl); return 0; diff --git a/drivers/media/i2c/ov8856.c b/drivers/media/i2c/ov8856.c index d8cefd3d4045..b337f729d5e3 100644 --- a/drivers/media/i2c/ov8856.c +++ b/drivers/media/i2c/ov8856.c @@ -428,7 +428,7 @@ static const struct ov8856_reg mode_3264x2448_regs[] = { {0x3810, 0x00}, {0x3811, 0x04}, {0x3812, 0x00}, - {0x3813, 0x02}, + {0x3813, 0x01}, {0x3814, 0x01}, {0x3815, 0x01}, {0x3816, 0x00}, @@ -821,7 +821,7 @@ static const struct ov8856_reg mode_1632x1224_regs[] = { {0x3810, 0x00}, {0x3811, 0x02}, {0x3812, 0x00}, - {0x3813, 0x02}, + {0x3813, 0x01}, {0x3814, 0x03}, {0x3815, 0x01}, {0x3816, 0x00}, diff --git a/drivers/media/i2c/ov8865.c b/drivers/media/i2c/ov8865.c new file mode 100644 index 000000000000..36a60fbc211d --- /dev/null +++ b/drivers/media/i2c/ov8865.c @@ -0,0 +1,2972 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2020 Kévin L'hôpital <kevin.lhopital@bootlin.com> + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of_graph.h> +#include <linux/pm_runtime.h> +#include <linux/regulator/consumer.h> +#include <linux/videodev2.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-fwnode.h> +#include <media/v4l2-image-sizes.h> +#include <media/v4l2-mediabus.h> + +/* Clock rate */ + +#define OV8865_EXTCLK_RATE 24000000 + +/* Register definitions */ + +/* System */ + +#define OV8865_SW_STANDBY_REG 0x100 +#define OV8865_SW_STANDBY_STREAM_ON BIT(0) + +#define OV8865_SW_RESET_REG 0x103 +#define OV8865_SW_RESET_RESET BIT(0) + +#define OV8865_PLL_CTRL0_REG 0x300 +#define OV8865_PLL_CTRL0_PRE_DIV(v) ((v) & GENMASK(2, 0)) +#define OV8865_PLL_CTRL1_REG 0x301 +#define OV8865_PLL_CTRL1_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) +#define OV8865_PLL_CTRL2_REG 0x302 +#define OV8865_PLL_CTRL2_MUL_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_PLL_CTRL3_REG 0x303 +#define OV8865_PLL_CTRL3_M_DIV(v) (((v) - 1) & GENMASK(3, 0)) +#define OV8865_PLL_CTRL4_REG 0x304 +#define OV8865_PLL_CTRL4_MIPI_DIV(v) ((v) & GENMASK(1, 0)) +#define OV8865_PLL_CTRL5_REG 0x305 +#define OV8865_PLL_CTRL5_SYS_PRE_DIV(v) ((v) & GENMASK(1, 0)) +#define OV8865_PLL_CTRL6_REG 0x306 +#define OV8865_PLL_CTRL6_SYS_DIV(v) (((v) - 1) & BIT(0)) + +#define OV8865_PLL_CTRL8_REG 0x308 +#define OV8865_PLL_CTRL9_REG 0x309 +#define OV8865_PLL_CTRLA_REG 0x30a +#define OV8865_PLL_CTRLA_PRE_DIV_HALF(v) (((v) - 1) & BIT(0)) +#define OV8865_PLL_CTRLB_REG 0x30b +#define OV8865_PLL_CTRLB_PRE_DIV(v) ((v) & GENMASK(2, 0)) +#define OV8865_PLL_CTRLC_REG 0x30c +#define OV8865_PLL_CTRLC_MUL_H(v) (((v) & GENMASK(9, 8)) >> 8) +#define OV8865_PLL_CTRLD_REG 0x30d +#define OV8865_PLL_CTRLD_MUL_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_PLL_CTRLE_REG 0x30e +#define OV8865_PLL_CTRLE_SYS_DIV(v) ((v) & GENMASK(2, 0)) +#define OV8865_PLL_CTRLF_REG 0x30f +#define OV8865_PLL_CTRLF_SYS_PRE_DIV(v) (((v) - 1) & GENMASK(3, 0)) +#define OV8865_PLL_CTRL10_REG 0x310 +#define OV8865_PLL_CTRL11_REG 0x311 +#define OV8865_PLL_CTRL12_REG 0x312 +#define OV8865_PLL_CTRL12_PRE_DIV_HALF(v) ((((v) - 1) << 4) & BIT(4)) +#define OV8865_PLL_CTRL12_DAC_DIV(v) (((v) - 1) & GENMASK(3, 0)) + +#define OV8865_PLL_CTRL1B_REG 0x31b +#define OV8865_PLL_CTRL1C_REG 0x31c + +#define OV8865_PLL_CTRL1E_REG 0x31e +#define OV8865_PLL_CTRL1E_PLL1_NO_LAT BIT(3) + +#define OV8865_PAD_OEN0_REG 0x3000 + +#define OV8865_PAD_OEN2_REG 0x3002 + +#define OV8865_CLK_RST5_REG 0x3005 + +#define OV8865_CHIP_ID_HH_REG 0x300a +#define OV8865_CHIP_ID_HH_VALUE 0x00 +#define OV8865_CHIP_ID_H_REG 0x300b +#define OV8865_CHIP_ID_H_VALUE 0x88 +#define OV8865_CHIP_ID_L_REG 0x300c +#define OV8865_CHIP_ID_L_VALUE 0x65 +#define OV8865_PAD_OUT2_REG 0x300d + +#define OV8865_PAD_SEL2_REG 0x3010 +#define OV8865_PAD_PK_REG 0x3011 +#define OV8865_PAD_PK_DRIVE_STRENGTH_1X (0 << 5) +#define OV8865_PAD_PK_DRIVE_STRENGTH_2X (1 << 5) +#define OV8865_PAD_PK_DRIVE_STRENGTH_3X (2 << 5) +#define OV8865_PAD_PK_DRIVE_STRENGTH_4X (3 << 5) + +#define OV8865_PUMP_CLK_DIV_REG 0x3015 +#define OV8865_PUMP_CLK_DIV_PUMP_N(v) (((v) << 4) & GENMASK(6, 4)) +#define OV8865_PUMP_CLK_DIV_PUMP_P(v) ((v) & GENMASK(2, 0)) + +#define OV8865_MIPI_SC_CTRL0_REG 0x3018 +#define OV8865_MIPI_SC_CTRL0_LANES(v) ((((v) - 1) << 5) & \ + GENMASK(7, 5)) +#define OV8865_MIPI_SC_CTRL0_MIPI_EN BIT(4) +#define OV8865_MIPI_SC_CTRL0_UNKNOWN BIT(1) +#define OV8865_MIPI_SC_CTRL0_LANES_PD_MIPI BIT(0) +#define OV8865_MIPI_SC_CTRL1_REG 0x3019 +#define OV8865_CLK_RST0_REG 0x301a +#define OV8865_CLK_RST1_REG 0x301b +#define OV8865_CLK_RST2_REG 0x301c +#define OV8865_CLK_RST3_REG 0x301d +#define OV8865_CLK_RST4_REG 0x301e + +#define OV8865_PCLK_SEL_REG 0x3020 +#define OV8865_PCLK_SEL_PCLK_DIV_MASK BIT(3) +#define OV8865_PCLK_SEL_PCLK_DIV(v) ((((v) - 1) << 3) & BIT(3)) + +#define OV8865_MISC_CTRL_REG 0x3021 +#define OV8865_MIPI_SC_CTRL2_REG 0x3022 +#define OV8865_MIPI_SC_CTRL2_CLK_LANES_PD_MIPI BIT(1) +#define OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC BIT(0) + +#define OV8865_MIPI_BIT_SEL_REG 0x3031 +#define OV8865_MIPI_BIT_SEL(v) (((v) << 0) & GENMASK(4, 0)) +#define OV8865_CLK_SEL0_REG 0x3032 +#define OV8865_CLK_SEL0_PLL1_SYS_SEL(v) (((v) << 7) & BIT(7)) +#define OV8865_CLK_SEL1_REG 0x3033 +#define OV8865_CLK_SEL1_MIPI_EOF BIT(5) +#define OV8865_CLK_SEL1_UNKNOWN BIT(2) +#define OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK BIT(1) +#define OV8865_CLK_SEL1_PLL_SCLK_SEL(v) (((v) << 1) & BIT(1)) + +#define OV8865_SCLK_CTRL_REG 0x3106 +#define OV8865_SCLK_CTRL_SCLK_DIV(v) (((v) << 4) & GENMASK(7, 4)) +#define OV8865_SCLK_CTRL_SCLK_PRE_DIV(v) (((v) << 2) & GENMASK(3, 2)) +#define OV8865_SCLK_CTRL_UNKNOWN BIT(0) + +/* Exposure/gain */ + +#define OV8865_EXPOSURE_CTRL_HH_REG 0x3500 +#define OV8865_EXPOSURE_CTRL_HH(v) (((v) & GENMASK(19, 16)) >> 16) +#define OV8865_EXPOSURE_CTRL_H_REG 0x3501 +#define OV8865_EXPOSURE_CTRL_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_EXPOSURE_CTRL_L_REG 0x3502 +#define OV8865_EXPOSURE_CTRL_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_EXPOSURE_GAIN_MANUAL_REG 0x3503 + +#define OV8865_GAIN_CTRL_H_REG 0x3508 +#define OV8865_GAIN_CTRL_H(v) (((v) & GENMASK(12, 8)) >> 8) +#define OV8865_GAIN_CTRL_L_REG 0x3509 +#define OV8865_GAIN_CTRL_L(v) ((v) & GENMASK(7, 0)) + +/* Timing */ + +#define OV8865_CROP_START_X_H_REG 0x3800 +#define OV8865_CROP_START_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_CROP_START_X_L_REG 0x3801 +#define OV8865_CROP_START_X_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_CROP_START_Y_H_REG 0x3802 +#define OV8865_CROP_START_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_CROP_START_Y_L_REG 0x3803 +#define OV8865_CROP_START_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_CROP_END_X_H_REG 0x3804 +#define OV8865_CROP_END_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_CROP_END_X_L_REG 0x3805 +#define OV8865_CROP_END_X_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_CROP_END_Y_H_REG 0x3806 +#define OV8865_CROP_END_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_CROP_END_Y_L_REG 0x3807 +#define OV8865_CROP_END_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_OUTPUT_SIZE_X_H_REG 0x3808 +#define OV8865_OUTPUT_SIZE_X_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_OUTPUT_SIZE_X_L_REG 0x3809 +#define OV8865_OUTPUT_SIZE_X_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_OUTPUT_SIZE_Y_H_REG 0x380a +#define OV8865_OUTPUT_SIZE_Y_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_OUTPUT_SIZE_Y_L_REG 0x380b +#define OV8865_OUTPUT_SIZE_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_HTS_H_REG 0x380c +#define OV8865_HTS_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_HTS_L_REG 0x380d +#define OV8865_HTS_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_VTS_H_REG 0x380e +#define OV8865_VTS_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_VTS_L_REG 0x380f +#define OV8865_VTS_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_OFFSET_X_H_REG 0x3810 +#define OV8865_OFFSET_X_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_OFFSET_X_L_REG 0x3811 +#define OV8865_OFFSET_X_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_OFFSET_Y_H_REG 0x3812 +#define OV8865_OFFSET_Y_H(v) (((v) & GENMASK(14, 8)) >> 8) +#define OV8865_OFFSET_Y_L_REG 0x3813 +#define OV8865_OFFSET_Y_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_INC_X_ODD_REG 0x3814 +#define OV8865_INC_X_ODD(v) ((v) & GENMASK(4, 0)) +#define OV8865_INC_X_EVEN_REG 0x3815 +#define OV8865_INC_X_EVEN(v) ((v) & GENMASK(4, 0)) +#define OV8865_VSYNC_START_H_REG 0x3816 +#define OV8865_VSYNC_START_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_VSYNC_START_L_REG 0x3817 +#define OV8865_VSYNC_START_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_VSYNC_END_H_REG 0x3818 +#define OV8865_VSYNC_END_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_VSYNC_END_L_REG 0x3819 +#define OV8865_VSYNC_END_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_HSYNC_FIRST_H_REG 0x381a +#define OV8865_HSYNC_FIRST_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_HSYNC_FIRST_L_REG 0x381b +#define OV8865_HSYNC_FIRST_L(v) ((v) & GENMASK(7, 0)) + +#define OV8865_FORMAT1_REG 0x3820 +#define OV8865_FORMAT1_FLIP_VERT_ISP_EN BIT(2) +#define OV8865_FORMAT1_FLIP_VERT_SENSOR_EN BIT(1) +#define OV8865_FORMAT2_REG 0x3821 +#define OV8865_FORMAT2_HSYNC_EN BIT(6) +#define OV8865_FORMAT2_FST_VBIN_EN BIT(5) +#define OV8865_FORMAT2_FST_HBIN_EN BIT(4) +#define OV8865_FORMAT2_ISP_HORZ_VAR2_EN BIT(3) +#define OV8865_FORMAT2_FLIP_HORZ_ISP_EN BIT(2) +#define OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN BIT(1) +#define OV8865_FORMAT2_SYNC_HBIN_EN BIT(0) + +#define OV8865_INC_Y_ODD_REG 0x382a +#define OV8865_INC_Y_ODD(v) ((v) & GENMASK(4, 0)) +#define OV8865_INC_Y_EVEN_REG 0x382b +#define OV8865_INC_Y_EVEN(v) ((v) & GENMASK(4, 0)) + +#define OV8865_ABLC_NUM_REG 0x3830 +#define OV8865_ABLC_NUM(v) ((v) & GENMASK(4, 0)) + +#define OV8865_ZLINE_NUM_REG 0x3836 +#define OV8865_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) + +#define OV8865_AUTO_SIZE_CTRL_REG 0x3841 +#define OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG BIT(5) +#define OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG BIT(4) +#define OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG BIT(3) +#define OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG BIT(2) +#define OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG BIT(1) +#define OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG BIT(0) +#define OV8865_AUTO_SIZE_X_OFFSET_H_REG 0x3842 +#define OV8865_AUTO_SIZE_X_OFFSET_L_REG 0x3843 +#define OV8865_AUTO_SIZE_Y_OFFSET_H_REG 0x3844 +#define OV8865_AUTO_SIZE_Y_OFFSET_L_REG 0x3845 +#define OV8865_AUTO_SIZE_BOUNDARIES_REG 0x3846 +#define OV8865_AUTO_SIZE_BOUNDARIES_Y(v) (((v) << 4) & GENMASK(7, 4)) +#define OV8865_AUTO_SIZE_BOUNDARIES_X(v) ((v) & GENMASK(3, 0)) + +/* PSRAM */ + +#define OV8865_PSRAM_CTRL8_REG 0x3f08 + +/* Black Level */ + +#define OV8865_BLC_CTRL0_REG 0x4000 +#define OV8865_BLC_CTRL0_TRIG_RANGE_EN BIT(7) +#define OV8865_BLC_CTRL0_TRIG_FORMAT_EN BIT(6) +#define OV8865_BLC_CTRL0_TRIG_GAIN_EN BIT(5) +#define OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN BIT(4) +#define OV8865_BLC_CTRL0_TRIG_MANUAL_EN BIT(3) +#define OV8865_BLC_CTRL0_FREEZE_EN BIT(2) +#define OV8865_BLC_CTRL0_ALWAYS_EN BIT(1) +#define OV8865_BLC_CTRL0_FILTER_EN BIT(0) +#define OV8865_BLC_CTRL1_REG 0x4001 +#define OV8865_BLC_CTRL1_DITHER_EN BIT(7) +#define OV8865_BLC_CTRL1_ZERO_LINE_DIFF_EN BIT(6) +#define OV8865_BLC_CTRL1_COL_SHIFT_256 (0 << 4) +#define OV8865_BLC_CTRL1_COL_SHIFT_128 (1 << 4) +#define OV8865_BLC_CTRL1_COL_SHIFT_64 (2 << 4) +#define OV8865_BLC_CTRL1_COL_SHIFT_32 (3 << 4) +#define OV8865_BLC_CTRL1_OFFSET_LIMIT_EN BIT(2) +#define OV8865_BLC_CTRL1_COLUMN_CANCEL_EN BIT(1) +#define OV8865_BLC_CTRL2_REG 0x4002 +#define OV8865_BLC_CTRL3_REG 0x4003 +#define OV8865_BLC_CTRL4_REG 0x4004 +#define OV8865_BLC_CTRL5_REG 0x4005 +#define OV8865_BLC_CTRL6_REG 0x4006 +#define OV8865_BLC_CTRL7_REG 0x4007 +#define OV8865_BLC_CTRL8_REG 0x4008 +#define OV8865_BLC_CTRL9_REG 0x4009 +#define OV8865_BLC_CTRLA_REG 0x400a +#define OV8865_BLC_CTRLB_REG 0x400b +#define OV8865_BLC_CTRLC_REG 0x400c +#define OV8865_BLC_CTRLD_REG 0x400d +#define OV8865_BLC_CTRLD_OFFSET_TRIGGER(v) ((v) & GENMASK(7, 0)) + +#define OV8865_BLC_CTRL1F_REG 0x401f +#define OV8865_BLC_CTRL1F_RB_REVERSE BIT(3) +#define OV8865_BLC_CTRL1F_INTERPOL_X_EN BIT(2) +#define OV8865_BLC_CTRL1F_INTERPOL_Y_EN BIT(1) + +#define OV8865_BLC_ANCHOR_LEFT_START_H_REG 0x4020 +#define OV8865_BLC_ANCHOR_LEFT_START_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_BLC_ANCHOR_LEFT_START_L_REG 0x4021 +#define OV8865_BLC_ANCHOR_LEFT_START_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_BLC_ANCHOR_LEFT_END_H_REG 0x4022 +#define OV8865_BLC_ANCHOR_LEFT_END_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_BLC_ANCHOR_LEFT_END_L_REG 0x4023 +#define OV8865_BLC_ANCHOR_LEFT_END_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_BLC_ANCHOR_RIGHT_START_H_REG 0x4024 +#define OV8865_BLC_ANCHOR_RIGHT_START_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_BLC_ANCHOR_RIGHT_START_L_REG 0x4025 +#define OV8865_BLC_ANCHOR_RIGHT_START_L(v) ((v) & GENMASK(7, 0)) +#define OV8865_BLC_ANCHOR_RIGHT_END_H_REG 0x4026 +#define OV8865_BLC_ANCHOR_RIGHT_END_H(v) (((v) & GENMASK(11, 8)) >> 8) +#define OV8865_BLC_ANCHOR_RIGHT_END_L_REG 0x4027 +#define OV8865_BLC_ANCHOR_RIGHT_END_L(v) ((v) & GENMASK(7, 0)) + +#define OV8865_BLC_TOP_ZLINE_START_REG 0x4028 +#define OV8865_BLC_TOP_ZLINE_START(v) ((v) & GENMASK(5, 0)) +#define OV8865_BLC_TOP_ZLINE_NUM_REG 0x4029 +#define OV8865_BLC_TOP_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) +#define OV8865_BLC_TOP_BLKLINE_START_REG 0x402a +#define OV8865_BLC_TOP_BLKLINE_START(v) ((v) & GENMASK(5, 0)) +#define OV8865_BLC_TOP_BLKLINE_NUM_REG 0x402b +#define OV8865_BLC_TOP_BLKLINE_NUM(v) ((v) & GENMASK(4, 0)) +#define OV8865_BLC_BOT_ZLINE_START_REG 0x402c +#define OV8865_BLC_BOT_ZLINE_START(v) ((v) & GENMASK(5, 0)) +#define OV8865_BLC_BOT_ZLINE_NUM_REG 0x402d +#define OV8865_BLC_BOT_ZLINE_NUM(v) ((v) & GENMASK(4, 0)) +#define OV8865_BLC_BOT_BLKLINE_START_REG 0x402e +#define OV8865_BLC_BOT_BLKLINE_START(v) ((v) & GENMASK(5, 0)) +#define OV8865_BLC_BOT_BLKLINE_NUM_REG 0x402f +#define OV8865_BLC_BOT_BLKLINE_NUM(v) ((v) & GENMASK(4, 0)) + +#define OV8865_BLC_OFFSET_LIMIT_REG 0x4034 +#define OV8865_BLC_OFFSET_LIMIT(v) ((v) & GENMASK(7, 0)) + +/* VFIFO */ + +#define OV8865_VFIFO_READ_START_H_REG 0x4600 +#define OV8865_VFIFO_READ_START_H(v) (((v) & GENMASK(15, 8)) >> 8) +#define OV8865_VFIFO_READ_START_L_REG 0x4601 +#define OV8865_VFIFO_READ_START_L(v) ((v) & GENMASK(7, 0)) + +/* MIPI */ + +#define OV8865_MIPI_CTRL0_REG 0x4800 +#define OV8865_MIPI_CTRL1_REG 0x4801 +#define OV8865_MIPI_CTRL2_REG 0x4802 +#define OV8865_MIPI_CTRL3_REG 0x4803 +#define OV8865_MIPI_CTRL4_REG 0x4804 +#define OV8865_MIPI_CTRL5_REG 0x4805 +#define OV8865_MIPI_CTRL6_REG 0x4806 +#define OV8865_MIPI_CTRL7_REG 0x4807 +#define OV8865_MIPI_CTRL8_REG 0x4808 + +#define OV8865_MIPI_FCNT_MAX_H_REG 0x4810 +#define OV8865_MIPI_FCNT_MAX_L_REG 0x4811 + +#define OV8865_MIPI_CTRL13_REG 0x4813 +#define OV8865_MIPI_CTRL14_REG 0x4814 +#define OV8865_MIPI_CTRL15_REG 0x4815 +#define OV8865_MIPI_EMBEDDED_DT_REG 0x4816 + +#define OV8865_MIPI_HS_ZERO_MIN_H_REG 0x4818 +#define OV8865_MIPI_HS_ZERO_MIN_L_REG 0x4819 +#define OV8865_MIPI_HS_TRAIL_MIN_H_REG 0x481a +#define OV8865_MIPI_HS_TRAIL_MIN_L_REG 0x481b +#define OV8865_MIPI_CLK_ZERO_MIN_H_REG 0x481c +#define OV8865_MIPI_CLK_ZERO_MIN_L_REG 0x481d +#define OV8865_MIPI_CLK_PREPARE_MAX_REG 0x481e +#define OV8865_MIPI_CLK_PREPARE_MIN_REG 0x481f +#define OV8865_MIPI_CLK_POST_MIN_H_REG 0x4820 +#define OV8865_MIPI_CLK_POST_MIN_L_REG 0x4821 +#define OV8865_MIPI_CLK_TRAIL_MIN_H_REG 0x4822 +#define OV8865_MIPI_CLK_TRAIL_MIN_L_REG 0x4823 +#define OV8865_MIPI_LPX_P_MIN_H_REG 0x4824 +#define OV8865_MIPI_LPX_P_MIN_L_REG 0x4825 +#define OV8865_MIPI_HS_PREPARE_MIN_REG 0x4826 +#define OV8865_MIPI_HS_PREPARE_MAX_REG 0x4827 +#define OV8865_MIPI_HS_EXIT_MIN_H_REG 0x4828 +#define OV8865_MIPI_HS_EXIT_MIN_L_REG 0x4829 +#define OV8865_MIPI_UI_HS_ZERO_MIN_REG 0x482a +#define OV8865_MIPI_UI_HS_TRAIL_MIN_REG 0x482b +#define OV8865_MIPI_UI_CLK_ZERO_MIN_REG 0x482c +#define OV8865_MIPI_UI_CLK_PREPARE_REG 0x482d +#define OV8865_MIPI_UI_CLK_POST_MIN_REG 0x482e +#define OV8865_MIPI_UI_CLK_TRAIL_MIN_REG 0x482f +#define OV8865_MIPI_UI_LPX_P_MIN_REG 0x4830 +#define OV8865_MIPI_UI_HS_PREPARE_REG 0x4831 +#define OV8865_MIPI_UI_HS_EXIT_MIN_REG 0x4832 +#define OV8865_MIPI_PKT_START_SIZE_REG 0x4833 + +#define OV8865_MIPI_PCLK_PERIOD_REG 0x4837 +#define OV8865_MIPI_LP_GPIO0_REG 0x4838 +#define OV8865_MIPI_LP_GPIO1_REG 0x4839 + +#define OV8865_MIPI_CTRL3C_REG 0x483c +#define OV8865_MIPI_LP_GPIO4_REG 0x483d + +#define OV8865_MIPI_CTRL4A_REG 0x484a +#define OV8865_MIPI_CTRL4B_REG 0x484b +#define OV8865_MIPI_CTRL4C_REG 0x484c +#define OV8865_MIPI_LANE_TEST_PATTERN_REG 0x484d +#define OV8865_MIPI_FRAME_END_DELAY_REG 0x484e +#define OV8865_MIPI_CLOCK_TEST_PATTERN_REG 0x484f +#define OV8865_MIPI_LANE_SEL01_REG 0x4850 +#define OV8865_MIPI_LANE_SEL01_LANE0(v) (((v) << 0) & GENMASK(2, 0)) +#define OV8865_MIPI_LANE_SEL01_LANE1(v) (((v) << 4) & GENMASK(6, 4)) +#define OV8865_MIPI_LANE_SEL23_REG 0x4851 +#define OV8865_MIPI_LANE_SEL23_LANE2(v) (((v) << 0) & GENMASK(2, 0)) +#define OV8865_MIPI_LANE_SEL23_LANE3(v) (((v) << 4) & GENMASK(6, 4)) + +/* ISP */ + +#define OV8865_ISP_CTRL0_REG 0x5000 +#define OV8865_ISP_CTRL0_LENC_EN BIT(7) +#define OV8865_ISP_CTRL0_WHITE_BALANCE_EN BIT(4) +#define OV8865_ISP_CTRL0_DPC_BLACK_EN BIT(2) +#define OV8865_ISP_CTRL0_DPC_WHITE_EN BIT(1) +#define OV8865_ISP_CTRL1_REG 0x5001 +#define OV8865_ISP_CTRL1_BLC_EN BIT(0) +#define OV8865_ISP_CTRL2_REG 0x5002 +#define OV8865_ISP_CTRL2_DEBUG BIT(3) +#define OV8865_ISP_CTRL2_VARIOPIXEL_EN BIT(2) +#define OV8865_ISP_CTRL2_VSYNC_LATCH_EN BIT(0) +#define OV8865_ISP_CTRL3_REG 0x5003 + +#define OV8865_ISP_GAIN_RED_H_REG 0x5018 +#define OV8865_ISP_GAIN_RED_H(v) (((v) & GENMASK(13, 6)) >> 6) +#define OV8865_ISP_GAIN_RED_L_REG 0x5019 +#define OV8865_ISP_GAIN_RED_L(v) ((v) & GENMASK(5, 0)) +#define OV8865_ISP_GAIN_GREEN_H_REG 0x501a +#define OV8865_ISP_GAIN_GREEN_H(v) (((v) & GENMASK(13, 6)) >> 6) +#define OV8865_ISP_GAIN_GREEN_L_REG 0x501b +#define OV8865_ISP_GAIN_GREEN_L(v) ((v) & GENMASK(5, 0)) +#define OV8865_ISP_GAIN_BLUE_H_REG 0x501c +#define OV8865_ISP_GAIN_BLUE_H(v) (((v) & GENMASK(13, 6)) >> 6) +#define OV8865_ISP_GAIN_BLUE_L_REG 0x501d +#define OV8865_ISP_GAIN_BLUE_L(v) ((v) & GENMASK(5, 0)) + +/* VarioPixel */ + +#define OV8865_VAP_CTRL0_REG 0x5900 +#define OV8865_VAP_CTRL1_REG 0x5901 +#define OV8865_VAP_CTRL1_HSUB_COEF(v) ((((v) - 1) << 2) & \ + GENMASK(3, 2)) +#define OV8865_VAP_CTRL1_VSUB_COEF(v) (((v) - 1) & GENMASK(1, 0)) + +/* Pre-DSP */ + +#define OV8865_PRE_CTRL0_REG 0x5e00 +#define OV8865_PRE_CTRL0_PATTERN_EN BIT(7) +#define OV8865_PRE_CTRL0_ROLLING_BAR_EN BIT(6) +#define OV8865_PRE_CTRL0_TRANSPARENT_MODE BIT(5) +#define OV8865_PRE_CTRL0_SQUARES_BW_MODE BIT(4) +#define OV8865_PRE_CTRL0_PATTERN_COLOR_BARS 0 +#define OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA 1 +#define OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES 2 +#define OV8865_PRE_CTRL0_PATTERN_BLACK 3 + +/* Macros */ + +#define ov8865_subdev_sensor(s) \ + container_of(s, struct ov8865_sensor, subdev) + +#define ov8865_ctrl_subdev(c) \ + (&container_of((c)->handler, struct ov8865_sensor, \ + ctrls.handler)->subdev) + +/* Data structures */ + +struct ov8865_register_value { + u16 address; + u8 value; + unsigned int delay_ms; +}; + +/* + * PLL1 Clock Tree: + * + * +-< EXTCLK + * | + * +-+ pll_pre_div_half (0x30a [0]) + * | + * +-+ pll_pre_div (0x300 [2:0], special values: + * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8) + * +-+ pll_mul (0x301 [1:0], 0x302 [7:0]) + * | + * +-+ m_div (0x303 [3:0]) + * | | + * | +-> PHY_SCLK + * | | + * | +-+ mipi_div (0x304 [1:0], special values: 0: 4, 1: 5, 2: 6, 3: 8) + * | | + * | +-+ pclk_div (0x3020 [3]) + * | | + * | +-> PCLK + * | + * +-+ sys_pre_div (0x305 [1:0], special values: 0: 3, 1: 4, 2: 5, 3: 6) + * | + * +-+ sys_div (0x306 [0]) + * | + * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2) + * | + * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK) + * | + * +-+ sclk_pre_div (0x3106 [3:2], special values: + * | 0: 1, 1: 2, 2: 4, 3: 1) + * | + * +-+ sclk_div (0x3106 [7:4], special values: 0: 1) + * | + * +-> SCLK + */ + +struct ov8865_pll1_config { + unsigned int pll_pre_div_half; + unsigned int pll_pre_div; + unsigned int pll_mul; + unsigned int m_div; + unsigned int mipi_div; + unsigned int pclk_div; + unsigned int sys_pre_div; + unsigned int sys_div; +}; + +/* + * PLL2 Clock Tree: + * + * +-< EXTCLK + * | + * +-+ pll_pre_div_half (0x312 [4]) + * | + * +-+ pll_pre_div (0x30b [2:0], special values: + * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 4, 7: 8) + * +-+ pll_mul (0x30c [1:0], 0x30d [7:0]) + * | + * +-+ dac_div (0x312 [3:0]) + * | | + * | +-> DAC_CLK + * | + * +-+ sys_pre_div (0x30f [3:0]) + * | + * +-+ sys_div (0x30e [2:0], special values: + * | 0: 1, 1: 1.5, 3: 2.5, 4: 3, 5: 3.5, 6: 4, 7:5) + * | + * +-+ sys_sel (0x3032 [7], 0: PLL1, 1: PLL2) + * | + * +-+ sclk_sel (0x3033 [1], 0: sys_sel, 1: PLL2 DAC_CLK) + * | + * +-+ sclk_pre_div (0x3106 [3:2], special values: + * | 0: 1, 1: 2, 2: 4, 3: 1) + * | + * +-+ sclk_div (0x3106 [7:4], special values: 0: 1) + * | + * +-> SCLK + */ + +struct ov8865_pll2_config { + unsigned int pll_pre_div_half; + unsigned int pll_pre_div; + unsigned int pll_mul; + unsigned int dac_div; + unsigned int sys_pre_div; + unsigned int sys_div; +}; + +struct ov8865_sclk_config { + unsigned int sys_sel; + unsigned int sclk_sel; + unsigned int sclk_pre_div; + unsigned int sclk_div; +}; + +/* + * General formulas for (array-centered) mode calculation: + * - photo_array_width = 3296 + * - crop_start_x = (photo_array_width - output_size_x) / 2 + * - crop_end_x = crop_start_x + offset_x + output_size_x - 1 + * + * - photo_array_height = 2480 + * - crop_start_y = (photo_array_height - output_size_y) / 2 + * - crop_end_y = crop_start_y + offset_y + output_size_y - 1 + */ + +struct ov8865_mode { + unsigned int crop_start_x; + unsigned int offset_x; + unsigned int output_size_x; + unsigned int crop_end_x; + unsigned int hts; + + unsigned int crop_start_y; + unsigned int offset_y; + unsigned int output_size_y; + unsigned int crop_end_y; + unsigned int vts; + + /* With auto size, only output and total sizes need to be set. */ + bool size_auto; + unsigned int size_auto_boundary_x; + unsigned int size_auto_boundary_y; + + bool binning_x; + bool binning_y; + bool variopixel; + unsigned int variopixel_hsub_coef; + unsigned int variopixel_vsub_coef; + + /* Bits for the format register, used for binning. */ + bool sync_hbin; + bool horz_var2; + + unsigned int inc_x_odd; + unsigned int inc_x_even; + unsigned int inc_y_odd; + unsigned int inc_y_even; + + unsigned int vfifo_read_start; + + unsigned int ablc_num; + unsigned int zline_num; + + unsigned int blc_top_zero_line_start; + unsigned int blc_top_zero_line_num; + unsigned int blc_top_black_line_start; + unsigned int blc_top_black_line_num; + + unsigned int blc_bottom_zero_line_start; + unsigned int blc_bottom_zero_line_num; + unsigned int blc_bottom_black_line_start; + unsigned int blc_bottom_black_line_num; + + u8 blc_col_shift_mask; + + unsigned int blc_anchor_left_start; + unsigned int blc_anchor_left_end; + unsigned int blc_anchor_right_start; + unsigned int blc_anchor_right_end; + + struct v4l2_fract frame_interval; + + const struct ov8865_pll1_config *pll1_config; + const struct ov8865_pll2_config *pll2_config; + const struct ov8865_sclk_config *sclk_config; + + const struct ov8865_register_value *register_values; + unsigned int register_values_count; +}; + +struct ov8865_state { + const struct ov8865_mode *mode; + u32 mbus_code; + + bool streaming; +}; + +struct ov8865_ctrls { + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + + struct v4l2_ctrl_handler handler; +}; + +struct ov8865_sensor { + struct device *dev; + struct i2c_client *i2c_client; + struct gpio_desc *reset; + struct gpio_desc *powerdown; + struct regulator *avdd; + struct regulator *dvdd; + struct regulator *dovdd; + struct clk *extclk; + + struct v4l2_fwnode_endpoint endpoint; + struct v4l2_subdev subdev; + struct media_pad pad; + + struct mutex mutex; + + struct ov8865_state state; + struct ov8865_ctrls ctrls; +}; + +/* Static definitions */ + +/* + * EXTCLK = 24 MHz + * PHY_SCLK = 720 MHz + * MIPI_PCLK = 90 MHz + */ +static const struct ov8865_pll1_config ov8865_pll1_config_native = { + .pll_pre_div_half = 1, + .pll_pre_div = 0, + .pll_mul = 30, + .m_div = 1, + .mipi_div = 3, + .pclk_div = 1, + .sys_pre_div = 1, + .sys_div = 2, +}; + +/* + * EXTCLK = 24 MHz + * DAC_CLK = 360 MHz + * SCLK = 144 MHz + */ + +static const struct ov8865_pll2_config ov8865_pll2_config_native = { + .pll_pre_div_half = 1, + .pll_pre_div = 0, + .pll_mul = 30, + .dac_div = 2, + .sys_pre_div = 5, + .sys_div = 0, +}; + +/* + * EXTCLK = 24 MHz + * DAC_CLK = 360 MHz + * SCLK = 80 MHz + */ + +static const struct ov8865_pll2_config ov8865_pll2_config_binning = { + .pll_pre_div_half = 1, + .pll_pre_div = 0, + .pll_mul = 30, + .dac_div = 2, + .sys_pre_div = 10, + .sys_div = 0, +}; + +static const struct ov8865_sclk_config ov8865_sclk_config_native = { + .sys_sel = 1, + .sclk_sel = 0, + .sclk_pre_div = 0, + .sclk_div = 0, +}; + +static const struct ov8865_register_value ov8865_register_values_native[] = { + /* Sensor */ + + { 0x3700, 0x48 }, + { 0x3701, 0x18 }, + { 0x3702, 0x50 }, + { 0x3703, 0x32 }, + { 0x3704, 0x28 }, + { 0x3706, 0x70 }, + { 0x3707, 0x08 }, + { 0x3708, 0x48 }, + { 0x3709, 0x80 }, + { 0x370a, 0x01 }, + { 0x370b, 0x70 }, + { 0x370c, 0x07 }, + { 0x3718, 0x14 }, + { 0x3712, 0x44 }, + { 0x371e, 0x31 }, + { 0x371f, 0x7f }, + { 0x3720, 0x0a }, + { 0x3721, 0x0a }, + { 0x3724, 0x04 }, + { 0x3725, 0x04 }, + { 0x3726, 0x0c }, + { 0x3728, 0x0a }, + { 0x3729, 0x03 }, + { 0x372a, 0x06 }, + { 0x372b, 0xa6 }, + { 0x372c, 0xa6 }, + { 0x372d, 0xa6 }, + { 0x372e, 0x0c }, + { 0x372f, 0x20 }, + { 0x3730, 0x02 }, + { 0x3731, 0x0c }, + { 0x3732, 0x28 }, + { 0x3736, 0x30 }, + { 0x373a, 0x04 }, + { 0x373b, 0x18 }, + { 0x373c, 0x14 }, + { 0x373e, 0x06 }, + { 0x375a, 0x0c }, + { 0x375b, 0x26 }, + { 0x375d, 0x04 }, + { 0x375f, 0x28 }, + { 0x3767, 0x1e }, + { 0x3772, 0x46 }, + { 0x3773, 0x04 }, + { 0x3774, 0x2c }, + { 0x3775, 0x13 }, + { 0x3776, 0x10 }, + { 0x37a0, 0x88 }, + { 0x37a1, 0x7a }, + { 0x37a2, 0x7a }, + { 0x37a3, 0x02 }, + { 0x37a5, 0x09 }, + { 0x37a7, 0x88 }, + { 0x37a8, 0xb0 }, + { 0x37a9, 0xb0 }, + { 0x37aa, 0x88 }, + { 0x37ab, 0x5c }, + { 0x37ac, 0x5c }, + { 0x37ad, 0x55 }, + { 0x37ae, 0x19 }, + { 0x37af, 0x19 }, + { 0x37b3, 0x84 }, + { 0x37b4, 0x84 }, + { 0x37b5, 0x66 }, + + /* PSRAM */ + + { OV8865_PSRAM_CTRL8_REG, 0x16 }, + + /* ADC Sync */ + + { 0x4500, 0x68 }, +}; + +static const struct ov8865_register_value ov8865_register_values_binning[] = { + /* Sensor */ + + { 0x3700, 0x24 }, + { 0x3701, 0x0c }, + { 0x3702, 0x28 }, + { 0x3703, 0x19 }, + { 0x3704, 0x14 }, + { 0x3706, 0x38 }, + { 0x3707, 0x04 }, + { 0x3708, 0x24 }, + { 0x3709, 0x40 }, + { 0x370a, 0x00 }, + { 0x370b, 0xb8 }, + { 0x370c, 0x04 }, + { 0x3718, 0x12 }, + { 0x3712, 0x42 }, + { 0x371e, 0x19 }, + { 0x371f, 0x40 }, + { 0x3720, 0x05 }, + { 0x3721, 0x05 }, + { 0x3724, 0x02 }, + { 0x3725, 0x02 }, + { 0x3726, 0x06 }, + { 0x3728, 0x05 }, + { 0x3729, 0x02 }, + { 0x372a, 0x03 }, + { 0x372b, 0x53 }, + { 0x372c, 0xa3 }, + { 0x372d, 0x53 }, + { 0x372e, 0x06 }, + { 0x372f, 0x10 }, + { 0x3730, 0x01 }, + { 0x3731, 0x06 }, + { 0x3732, 0x14 }, + { 0x3736, 0x20 }, + { 0x373a, 0x02 }, + { 0x373b, 0x0c }, + { 0x373c, 0x0a }, + { 0x373e, 0x03 }, + { 0x375a, 0x06 }, + { 0x375b, 0x13 }, + { 0x375d, 0x02 }, + { 0x375f, 0x14 }, + { 0x3767, 0x1c }, + { 0x3772, 0x23 }, + { 0x3773, 0x02 }, + { 0x3774, 0x16 }, + { 0x3775, 0x12 }, + { 0x3776, 0x08 }, + { 0x37a0, 0x44 }, + { 0x37a1, 0x3d }, + { 0x37a2, 0x3d }, + { 0x37a3, 0x01 }, + { 0x37a5, 0x08 }, + { 0x37a7, 0x44 }, + { 0x37a8, 0x58 }, + { 0x37a9, 0x58 }, + { 0x37aa, 0x44 }, + { 0x37ab, 0x2e }, + { 0x37ac, 0x2e }, + { 0x37ad, 0x33 }, + { 0x37ae, 0x0d }, + { 0x37af, 0x0d }, + { 0x37b3, 0x42 }, + { 0x37b4, 0x42 }, + { 0x37b5, 0x33 }, + + /* PSRAM */ + + { OV8865_PSRAM_CTRL8_REG, 0x0b }, + + /* ADC Sync */ + + { 0x4500, 0x40 }, +}; + +static const struct ov8865_mode ov8865_modes[] = { + /* 3264x2448 */ + { + /* Horizontal */ + .output_size_x = 3264, + .hts = 1944, + + /* Vertical */ + .output_size_y = 2448, + .vts = 2470, + + .size_auto = true, + .size_auto_boundary_x = 8, + .size_auto_boundary_y = 4, + + /* Subsample increase */ + .inc_x_odd = 1, + .inc_x_even = 1, + .inc_y_odd = 1, + .inc_y_even = 1, + + /* VFIFO */ + .vfifo_read_start = 16, + + .ablc_num = 4, + .zline_num = 1, + + /* Black Level */ + + .blc_top_zero_line_start = 0, + .blc_top_zero_line_num = 2, + .blc_top_black_line_start = 4, + .blc_top_black_line_num = 4, + + .blc_bottom_zero_line_start = 2, + .blc_bottom_zero_line_num = 2, + .blc_bottom_black_line_start = 8, + .blc_bottom_black_line_num = 2, + + .blc_anchor_left_start = 576, + .blc_anchor_left_end = 831, + .blc_anchor_right_start = 1984, + .blc_anchor_right_end = 2239, + + /* Frame Interval */ + .frame_interval = { 1, 30 }, + + /* PLL */ + .pll1_config = &ov8865_pll1_config_native, + .pll2_config = &ov8865_pll2_config_native, + .sclk_config = &ov8865_sclk_config_native, + + /* Registers */ + .register_values = ov8865_register_values_native, + .register_values_count = + ARRAY_SIZE(ov8865_register_values_native), + }, + /* 3264x1836 */ + { + /* Horizontal */ + .output_size_x = 3264, + .hts = 2582, + + /* Vertical */ + .output_size_y = 1836, + .vts = 2002, + + .size_auto = true, + .size_auto_boundary_x = 8, + .size_auto_boundary_y = 4, + + /* Subsample increase */ + .inc_x_odd = 1, + .inc_x_even = 1, + .inc_y_odd = 1, + .inc_y_even = 1, + + /* VFIFO */ + .vfifo_read_start = 16, + + .ablc_num = 4, + .zline_num = 1, + + /* Black Level */ + + .blc_top_zero_line_start = 0, + .blc_top_zero_line_num = 2, + .blc_top_black_line_start = 4, + .blc_top_black_line_num = 4, + + .blc_bottom_zero_line_start = 2, + .blc_bottom_zero_line_num = 2, + .blc_bottom_black_line_start = 8, + .blc_bottom_black_line_num = 2, + + .blc_anchor_left_start = 576, + .blc_anchor_left_end = 831, + .blc_anchor_right_start = 1984, + .blc_anchor_right_end = 2239, + + /* Frame Interval */ + .frame_interval = { 1, 30 }, + + /* PLL */ + .pll1_config = &ov8865_pll1_config_native, + .pll2_config = &ov8865_pll2_config_native, + .sclk_config = &ov8865_sclk_config_native, + + /* Registers */ + .register_values = ov8865_register_values_native, + .register_values_count = + ARRAY_SIZE(ov8865_register_values_native), + }, + /* 1632x1224 */ + { + /* Horizontal */ + .output_size_x = 1632, + .hts = 1923, + + /* Vertical */ + .output_size_y = 1224, + .vts = 1248, + + .size_auto = true, + .size_auto_boundary_x = 8, + .size_auto_boundary_y = 8, + + /* Subsample increase */ + .inc_x_odd = 3, + .inc_x_even = 1, + .inc_y_odd = 3, + .inc_y_even = 1, + + /* Binning */ + .binning_y = true, + .sync_hbin = true, + + /* VFIFO */ + .vfifo_read_start = 116, + + .ablc_num = 8, + .zline_num = 2, + + /* Black Level */ + + .blc_top_zero_line_start = 0, + .blc_top_zero_line_num = 2, + .blc_top_black_line_start = 4, + .blc_top_black_line_num = 4, + + .blc_bottom_zero_line_start = 2, + .blc_bottom_zero_line_num = 2, + .blc_bottom_black_line_start = 8, + .blc_bottom_black_line_num = 2, + + .blc_anchor_left_start = 288, + .blc_anchor_left_end = 415, + .blc_anchor_right_start = 992, + .blc_anchor_right_end = 1119, + + /* Frame Interval */ + .frame_interval = { 1, 30 }, + + /* PLL */ + .pll1_config = &ov8865_pll1_config_native, + .pll2_config = &ov8865_pll2_config_binning, + .sclk_config = &ov8865_sclk_config_native, + + /* Registers */ + .register_values = ov8865_register_values_binning, + .register_values_count = + ARRAY_SIZE(ov8865_register_values_binning), + }, + /* 800x600 (SVGA) */ + { + /* Horizontal */ + .output_size_x = 800, + .hts = 1250, + + /* Vertical */ + .output_size_y = 600, + .vts = 640, + + .size_auto = true, + .size_auto_boundary_x = 8, + .size_auto_boundary_y = 8, + + /* Subsample increase */ + .inc_x_odd = 3, + .inc_x_even = 1, + .inc_y_odd = 5, + .inc_y_even = 3, + + /* Binning */ + .binning_y = true, + .variopixel = true, + .variopixel_hsub_coef = 2, + .variopixel_vsub_coef = 1, + .sync_hbin = true, + .horz_var2 = true, + + /* VFIFO */ + .vfifo_read_start = 80, + + .ablc_num = 8, + .zline_num = 2, + + /* Black Level */ + + .blc_top_zero_line_start = 0, + .blc_top_zero_line_num = 2, + .blc_top_black_line_start = 2, + .blc_top_black_line_num = 2, + + .blc_bottom_zero_line_start = 0, + .blc_bottom_zero_line_num = 0, + .blc_bottom_black_line_start = 4, + .blc_bottom_black_line_num = 2, + + .blc_col_shift_mask = OV8865_BLC_CTRL1_COL_SHIFT_128, + + .blc_anchor_left_start = 288, + .blc_anchor_left_end = 415, + .blc_anchor_right_start = 992, + .blc_anchor_right_end = 1119, + + /* Frame Interval */ + .frame_interval = { 1, 90 }, + + /* PLL */ + .pll1_config = &ov8865_pll1_config_native, + .pll2_config = &ov8865_pll2_config_binning, + .sclk_config = &ov8865_sclk_config_native, + + /* Registers */ + .register_values = ov8865_register_values_binning, + .register_values_count = + ARRAY_SIZE(ov8865_register_values_binning), + }, +}; + +static const u32 ov8865_mbus_codes[] = { + MEDIA_BUS_FMT_SBGGR10_1X10, +}; + +static const struct ov8865_register_value ov8865_init_sequence[] = { + /* Analog */ + + { 0x3604, 0x04 }, + { 0x3602, 0x30 }, + { 0x3605, 0x00 }, + { 0x3607, 0x20 }, + { 0x3608, 0x11 }, + { 0x3609, 0x68 }, + { 0x360a, 0x40 }, + { 0x360c, 0xdd }, + { 0x360e, 0x0c }, + { 0x3610, 0x07 }, + { 0x3612, 0x86 }, + { 0x3613, 0x58 }, + { 0x3614, 0x28 }, + { 0x3617, 0x40 }, + { 0x3618, 0x5a }, + { 0x3619, 0x9b }, + { 0x361c, 0x00 }, + { 0x361d, 0x60 }, + { 0x3631, 0x60 }, + { 0x3633, 0x10 }, + { 0x3634, 0x10 }, + { 0x3635, 0x10 }, + { 0x3636, 0x10 }, + { 0x3638, 0xff }, + { 0x3641, 0x55 }, + { 0x3646, 0x86 }, + { 0x3647, 0x27 }, + { 0x364a, 0x1b }, + + /* Sensor */ + + { 0x3700, 0x24 }, + { 0x3701, 0x0c }, + { 0x3702, 0x28 }, + { 0x3703, 0x19 }, + { 0x3704, 0x14 }, + { 0x3705, 0x00 }, + { 0x3706, 0x38 }, + { 0x3707, 0x04 }, + { 0x3708, 0x24 }, + { 0x3709, 0x40 }, + { 0x370a, 0x00 }, + { 0x370b, 0xb8 }, + { 0x370c, 0x04 }, + { 0x3718, 0x12 }, + { 0x3719, 0x31 }, + { 0x3712, 0x42 }, + { 0x3714, 0x12 }, + { 0x371e, 0x19 }, + { 0x371f, 0x40 }, + { 0x3720, 0x05 }, + { 0x3721, 0x05 }, + { 0x3724, 0x02 }, + { 0x3725, 0x02 }, + { 0x3726, 0x06 }, + { 0x3728, 0x05 }, + { 0x3729, 0x02 }, + { 0x372a, 0x03 }, + { 0x372b, 0x53 }, + { 0x372c, 0xa3 }, + { 0x372d, 0x53 }, + { 0x372e, 0x06 }, + { 0x372f, 0x10 }, + { 0x3730, 0x01 }, + { 0x3731, 0x06 }, + { 0x3732, 0x14 }, + { 0x3733, 0x10 }, + { 0x3734, 0x40 }, + { 0x3736, 0x20 }, + { 0x373a, 0x02 }, + { 0x373b, 0x0c }, + { 0x373c, 0x0a }, + { 0x373e, 0x03 }, + { 0x3755, 0x40 }, + { 0x3758, 0x00 }, + { 0x3759, 0x4c }, + { 0x375a, 0x06 }, + { 0x375b, 0x13 }, + { 0x375c, 0x40 }, + { 0x375d, 0x02 }, + { 0x375e, 0x00 }, + { 0x375f, 0x14 }, + { 0x3767, 0x1c }, + { 0x3768, 0x04 }, + { 0x3769, 0x20 }, + { 0x376c, 0xc0 }, + { 0x376d, 0xc0 }, + { 0x376a, 0x08 }, + { 0x3761, 0x00 }, + { 0x3762, 0x00 }, + { 0x3763, 0x00 }, + { 0x3766, 0xff }, + { 0x376b, 0x42 }, + { 0x3772, 0x23 }, + { 0x3773, 0x02 }, + { 0x3774, 0x16 }, + { 0x3775, 0x12 }, + { 0x3776, 0x08 }, + { 0x37a0, 0x44 }, + { 0x37a1, 0x3d }, + { 0x37a2, 0x3d }, + { 0x37a3, 0x01 }, + { 0x37a4, 0x00 }, + { 0x37a5, 0x08 }, + { 0x37a6, 0x00 }, + { 0x37a7, 0x44 }, + { 0x37a8, 0x58 }, + { 0x37a9, 0x58 }, + { 0x3760, 0x00 }, + { 0x376f, 0x01 }, + { 0x37aa, 0x44 }, + { 0x37ab, 0x2e }, + { 0x37ac, 0x2e }, + { 0x37ad, 0x33 }, + { 0x37ae, 0x0d }, + { 0x37af, 0x0d }, + { 0x37b0, 0x00 }, + { 0x37b1, 0x00 }, + { 0x37b2, 0x00 }, + { 0x37b3, 0x42 }, + { 0x37b4, 0x42 }, + { 0x37b5, 0x33 }, + { 0x37b6, 0x00 }, + { 0x37b7, 0x00 }, + { 0x37b8, 0x00 }, + { 0x37b9, 0xff }, + + /* ADC Sync */ + + { 0x4503, 0x10 }, +}; + +static const s64 ov8865_link_freq_menu[] = { + 360000000, +}; + +static const char *const ov8865_test_pattern_menu[] = { + "Disabled", + "Random data", + "Color bars", + "Color bars with rolling bar", + "Color squares", + "Color squares with rolling bar" +}; + +static const u8 ov8865_test_pattern_bits[] = { + 0, + OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_RANDOM_DATA, + OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_BARS, + OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN | + OV8865_PRE_CTRL0_PATTERN_COLOR_BARS, + OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES, + OV8865_PRE_CTRL0_PATTERN_EN | OV8865_PRE_CTRL0_ROLLING_BAR_EN | + OV8865_PRE_CTRL0_PATTERN_COLOR_SQUARES, +}; + +/* Input/Output */ + +static int ov8865_read(struct ov8865_sensor *sensor, u16 address, u8 *value) +{ + unsigned char data[2] = { address >> 8, address & 0xff }; + struct i2c_client *client = sensor->i2c_client; + int ret; + + ret = i2c_master_send(client, data, sizeof(data)); + if (ret < 0) { + dev_dbg(&client->dev, "i2c send error at address %#04x\n", + address); + return ret; + } + + ret = i2c_master_recv(client, value, 1); + if (ret < 0) { + dev_dbg(&client->dev, "i2c recv error at address %#04x\n", + address); + return ret; + } + + return 0; +} + +static int ov8865_write(struct ov8865_sensor *sensor, u16 address, u8 value) +{ + unsigned char data[3] = { address >> 8, address & 0xff, value }; + struct i2c_client *client = sensor->i2c_client; + int ret; + + ret = i2c_master_send(client, data, sizeof(data)); + if (ret < 0) { + dev_dbg(&client->dev, "i2c send error at address %#04x\n", + address); + return ret; + } + + return 0; +} + +static int ov8865_write_sequence(struct ov8865_sensor *sensor, + const struct ov8865_register_value *sequence, + unsigned int sequence_count) +{ + unsigned int i; + int ret = 0; + + for (i = 0; i < sequence_count; i++) { + ret = ov8865_write(sensor, sequence[i].address, + sequence[i].value); + if (ret) + break; + + if (sequence[i].delay_ms) + msleep(sequence[i].delay_ms); + } + + return ret; +} + +static int ov8865_update_bits(struct ov8865_sensor *sensor, u16 address, + u8 mask, u8 bits) +{ + u8 value = 0; + int ret; + + ret = ov8865_read(sensor, address, &value); + if (ret) + return ret; + + value &= ~mask; + value |= bits; + + return ov8865_write(sensor, address, value); +} + +/* Sensor */ + +static int ov8865_sw_reset(struct ov8865_sensor *sensor) +{ + return ov8865_write(sensor, OV8865_SW_RESET_REG, OV8865_SW_RESET_RESET); +} + +static int ov8865_sw_standby(struct ov8865_sensor *sensor, int standby) +{ + u8 value = 0; + + if (!standby) + value = OV8865_SW_STANDBY_STREAM_ON; + + return ov8865_write(sensor, OV8865_SW_STANDBY_REG, value); +} + +static int ov8865_chip_id_check(struct ov8865_sensor *sensor) +{ + u16 regs[] = { OV8865_CHIP_ID_HH_REG, OV8865_CHIP_ID_H_REG, + OV8865_CHIP_ID_L_REG }; + u8 values[] = { OV8865_CHIP_ID_HH_VALUE, OV8865_CHIP_ID_H_VALUE, + OV8865_CHIP_ID_L_VALUE }; + unsigned int i; + u8 value; + int ret; + + for (i = 0; i < ARRAY_SIZE(regs); i++) { + ret = ov8865_read(sensor, regs[i], &value); + if (ret < 0) + return ret; + + if (value != values[i]) { + dev_err(sensor->dev, + "chip id value mismatch: %#x instead of %#x\n", + value, values[i]); + return -EINVAL; + } + } + + return 0; +} + +static int ov8865_charge_pump_configure(struct ov8865_sensor *sensor) +{ + return ov8865_write(sensor, OV8865_PUMP_CLK_DIV_REG, + OV8865_PUMP_CLK_DIV_PUMP_P(1)); +} + +static int ov8865_mipi_configure(struct ov8865_sensor *sensor) +{ + struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + &sensor->endpoint.bus.mipi_csi2; + unsigned int lanes_count = bus_mipi_csi2->num_data_lanes; + int ret; + + ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL0_REG, + OV8865_MIPI_SC_CTRL0_LANES(lanes_count) | + OV8865_MIPI_SC_CTRL0_MIPI_EN | + OV8865_MIPI_SC_CTRL0_UNKNOWN); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_MIPI_SC_CTRL2_REG, + OV8865_MIPI_SC_CTRL2_PD_MIPI_RST_SYNC); + if (ret) + return ret; + + if (lanes_count >= 2) { + ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL01_REG, + OV8865_MIPI_LANE_SEL01_LANE0(0) | + OV8865_MIPI_LANE_SEL01_LANE1(1)); + if (ret) + return ret; + } + + if (lanes_count >= 4) { + ret = ov8865_write(sensor, OV8865_MIPI_LANE_SEL23_REG, + OV8865_MIPI_LANE_SEL23_LANE2(2) | + OV8865_MIPI_LANE_SEL23_LANE3(3)); + if (ret) + return ret; + } + + ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG, + OV8865_CLK_SEL1_MIPI_EOF, + OV8865_CLK_SEL1_MIPI_EOF); + if (ret) + return ret; + + /* + * This value might need to change depending on PCLK rate, + * but it's unclear how. This value seems to generally work + * while the default value was found to cause transmission errors. + */ + return ov8865_write(sensor, OV8865_MIPI_PCLK_PERIOD_REG, 0x16); +} + +static int ov8865_black_level_configure(struct ov8865_sensor *sensor) +{ + int ret; + + /* Trigger BLC on relevant events and enable filter. */ + ret = ov8865_write(sensor, OV8865_BLC_CTRL0_REG, + OV8865_BLC_CTRL0_TRIG_RANGE_EN | + OV8865_BLC_CTRL0_TRIG_FORMAT_EN | + OV8865_BLC_CTRL0_TRIG_GAIN_EN | + OV8865_BLC_CTRL0_TRIG_EXPOSURE_EN | + OV8865_BLC_CTRL0_FILTER_EN); + if (ret) + return ret; + + /* Lower BLC offset trigger threshold. */ + ret = ov8865_write(sensor, OV8865_BLC_CTRLD_REG, + OV8865_BLC_CTRLD_OFFSET_TRIGGER(16)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_CTRL1F_REG, 0); + if (ret) + return ret; + + /* Increase BLC offset maximum limit. */ + return ov8865_write(sensor, OV8865_BLC_OFFSET_LIMIT_REG, + OV8865_BLC_OFFSET_LIMIT(63)); +} + +static int ov8865_isp_configure(struct ov8865_sensor *sensor) +{ + int ret; + + /* Disable lens correction. */ + ret = ov8865_write(sensor, OV8865_ISP_CTRL0_REG, + OV8865_ISP_CTRL0_WHITE_BALANCE_EN | + OV8865_ISP_CTRL0_DPC_BLACK_EN | + OV8865_ISP_CTRL0_DPC_WHITE_EN); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_ISP_CTRL1_REG, + OV8865_ISP_CTRL1_BLC_EN); +} + +static unsigned long ov8865_mode_pll1_rate(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + const struct ov8865_pll1_config *config = mode->pll1_config; + unsigned long extclk_rate; + unsigned long pll1_rate; + + extclk_rate = clk_get_rate(sensor->extclk); + pll1_rate = extclk_rate * config->pll_mul / config->pll_pre_div_half; + + switch (config->pll_pre_div) { + case 0: + break; + case 1: + pll1_rate *= 3; + pll1_rate /= 2; + break; + case 3: + pll1_rate *= 5; + pll1_rate /= 2; + break; + case 4: + pll1_rate /= 3; + break; + case 5: + pll1_rate /= 4; + break; + case 7: + pll1_rate /= 8; + break; + default: + pll1_rate /= config->pll_pre_div; + break; + } + + return pll1_rate; +} + +static int ov8865_mode_pll1_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode, + u32 mbus_code) +{ + const struct ov8865_pll1_config *config = mode->pll1_config; + u8 value; + int ret; + + switch (mbus_code) { + case MEDIA_BUS_FMT_SBGGR10_1X10: + value = OV8865_MIPI_BIT_SEL(10); + break; + default: + return -EINVAL; + } + + ret = ov8865_write(sensor, OV8865_MIPI_BIT_SEL_REG, value); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRLA_REG, + OV8865_PLL_CTRLA_PRE_DIV_HALF(config->pll_pre_div_half)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL0_REG, + OV8865_PLL_CTRL0_PRE_DIV(config->pll_pre_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL1_REG, + OV8865_PLL_CTRL1_MUL_H(config->pll_mul)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL2_REG, + OV8865_PLL_CTRL2_MUL_L(config->pll_mul)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL3_REG, + OV8865_PLL_CTRL3_M_DIV(config->m_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL4_REG, + OV8865_PLL_CTRL4_MIPI_DIV(config->mipi_div)); + if (ret) + return ret; + + ret = ov8865_update_bits(sensor, OV8865_PCLK_SEL_REG, + OV8865_PCLK_SEL_PCLK_DIV_MASK, + OV8865_PCLK_SEL_PCLK_DIV(config->pclk_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL5_REG, + OV8865_PLL_CTRL5_SYS_PRE_DIV(config->sys_pre_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL6_REG, + OV8865_PLL_CTRL6_SYS_DIV(config->sys_div)); + if (ret) + return ret; + + return ov8865_update_bits(sensor, OV8865_PLL_CTRL1E_REG, + OV8865_PLL_CTRL1E_PLL1_NO_LAT, + OV8865_PLL_CTRL1E_PLL1_NO_LAT); +} + +static int ov8865_mode_pll2_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + const struct ov8865_pll2_config *config = mode->pll2_config; + int ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRL12_REG, + OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) | + OV8865_PLL_CTRL12_DAC_DIV(config->dac_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRLB_REG, + OV8865_PLL_CTRLB_PRE_DIV(config->pll_pre_div)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRLC_REG, + OV8865_PLL_CTRLC_MUL_H(config->pll_mul)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRLD_REG, + OV8865_PLL_CTRLD_MUL_L(config->pll_mul)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_PLL_CTRLF_REG, + OV8865_PLL_CTRLF_SYS_PRE_DIV(config->sys_pre_div)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_PLL_CTRLE_REG, + OV8865_PLL_CTRLE_SYS_DIV(config->sys_div)); +} + +static int ov8865_mode_sclk_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + const struct ov8865_sclk_config *config = mode->sclk_config; + int ret; + + ret = ov8865_write(sensor, OV8865_CLK_SEL0_REG, + OV8865_CLK_SEL0_PLL1_SYS_SEL(config->sys_sel)); + if (ret) + return ret; + + ret = ov8865_update_bits(sensor, OV8865_CLK_SEL1_REG, + OV8865_CLK_SEL1_PLL_SCLK_SEL_MASK, + OV8865_CLK_SEL1_PLL_SCLK_SEL(config->sclk_sel)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_SCLK_CTRL_REG, + OV8865_SCLK_CTRL_UNKNOWN | + OV8865_SCLK_CTRL_SCLK_DIV(config->sclk_div) | + OV8865_SCLK_CTRL_SCLK_PRE_DIV(config->sclk_pre_div)); +} + +static int ov8865_mode_binning_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + unsigned int variopixel_hsub_coef, variopixel_vsub_coef; + u8 value; + int ret; + + ret = ov8865_write(sensor, OV8865_FORMAT1_REG, 0); + if (ret) + return ret; + + value = OV8865_FORMAT2_HSYNC_EN; + + if (mode->binning_x) + value |= OV8865_FORMAT2_FST_HBIN_EN; + + if (mode->binning_y) + value |= OV8865_FORMAT2_FST_VBIN_EN; + + if (mode->sync_hbin) + value |= OV8865_FORMAT2_SYNC_HBIN_EN; + + if (mode->horz_var2) + value |= OV8865_FORMAT2_ISP_HORZ_VAR2_EN; + + ret = ov8865_write(sensor, OV8865_FORMAT2_REG, value); + if (ret) + return ret; + + ret = ov8865_update_bits(sensor, OV8865_ISP_CTRL2_REG, + OV8865_ISP_CTRL2_VARIOPIXEL_EN, + mode->variopixel ? + OV8865_ISP_CTRL2_VARIOPIXEL_EN : 0); + if (ret) + return ret; + + if (mode->variopixel) { + /* VarioPixel coefs needs to be > 1. */ + variopixel_hsub_coef = mode->variopixel_hsub_coef; + variopixel_vsub_coef = mode->variopixel_vsub_coef; + } else { + variopixel_hsub_coef = 1; + variopixel_vsub_coef = 1; + } + + ret = ov8865_write(sensor, OV8865_VAP_CTRL1_REG, + OV8865_VAP_CTRL1_HSUB_COEF(variopixel_hsub_coef) | + OV8865_VAP_CTRL1_VSUB_COEF(variopixel_vsub_coef)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_INC_X_ODD_REG, + OV8865_INC_X_ODD(mode->inc_x_odd)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_INC_X_EVEN_REG, + OV8865_INC_X_EVEN(mode->inc_x_even)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_INC_Y_ODD_REG, + OV8865_INC_Y_ODD(mode->inc_y_odd)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_INC_Y_EVEN_REG, + OV8865_INC_Y_EVEN(mode->inc_y_even)); +} + +static int ov8865_mode_black_level_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + int ret; + + /* Note that a zero value for blc_col_shift_mask is the default 256. */ + ret = ov8865_write(sensor, OV8865_BLC_CTRL1_REG, + mode->blc_col_shift_mask | + OV8865_BLC_CTRL1_OFFSET_LIMIT_EN); + if (ret) + return ret; + + /* BLC top zero line */ + + ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_START_REG, + OV8865_BLC_TOP_ZLINE_START(mode->blc_top_zero_line_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_TOP_ZLINE_NUM_REG, + OV8865_BLC_TOP_ZLINE_NUM(mode->blc_top_zero_line_num)); + if (ret) + return ret; + + /* BLC top black line */ + + ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_START_REG, + OV8865_BLC_TOP_BLKLINE_START(mode->blc_top_black_line_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_TOP_BLKLINE_NUM_REG, + OV8865_BLC_TOP_BLKLINE_NUM(mode->blc_top_black_line_num)); + if (ret) + return ret; + + /* BLC bottom zero line */ + + ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_START_REG, + OV8865_BLC_BOT_ZLINE_START(mode->blc_bottom_zero_line_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_BOT_ZLINE_NUM_REG, + OV8865_BLC_BOT_ZLINE_NUM(mode->blc_bottom_zero_line_num)); + if (ret) + return ret; + + /* BLC bottom black line */ + + ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_START_REG, + OV8865_BLC_BOT_BLKLINE_START(mode->blc_bottom_black_line_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_BOT_BLKLINE_NUM_REG, + OV8865_BLC_BOT_BLKLINE_NUM(mode->blc_bottom_black_line_num)); + if (ret) + return ret; + + /* BLC anchor */ + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_H_REG, + OV8865_BLC_ANCHOR_LEFT_START_H(mode->blc_anchor_left_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_START_L_REG, + OV8865_BLC_ANCHOR_LEFT_START_L(mode->blc_anchor_left_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_H_REG, + OV8865_BLC_ANCHOR_LEFT_END_H(mode->blc_anchor_left_end)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_LEFT_END_L_REG, + OV8865_BLC_ANCHOR_LEFT_END_L(mode->blc_anchor_left_end)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_H_REG, + OV8865_BLC_ANCHOR_RIGHT_START_H(mode->blc_anchor_right_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_START_L_REG, + OV8865_BLC_ANCHOR_RIGHT_START_L(mode->blc_anchor_right_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_H_REG, + OV8865_BLC_ANCHOR_RIGHT_END_H(mode->blc_anchor_right_end)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_BLC_ANCHOR_RIGHT_END_L_REG, + OV8865_BLC_ANCHOR_RIGHT_END_L(mode->blc_anchor_right_end)); +} + +static int ov8865_mode_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode, u32 mbus_code) +{ + int ret; + + /* Output Size X */ + + ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_H_REG, + OV8865_OUTPUT_SIZE_X_H(mode->output_size_x)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_X_L_REG, + OV8865_OUTPUT_SIZE_X_L(mode->output_size_x)); + if (ret) + return ret; + + /* Horizontal Total Size */ + + ret = ov8865_write(sensor, OV8865_HTS_H_REG, OV8865_HTS_H(mode->hts)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_HTS_L_REG, OV8865_HTS_L(mode->hts)); + if (ret) + return ret; + + /* Output Size Y */ + + ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_H_REG, + OV8865_OUTPUT_SIZE_Y_H(mode->output_size_y)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_OUTPUT_SIZE_Y_L_REG, + OV8865_OUTPUT_SIZE_Y_L(mode->output_size_y)); + if (ret) + return ret; + + /* Vertical Total Size */ + + ret = ov8865_write(sensor, OV8865_VTS_H_REG, OV8865_VTS_H(mode->vts)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_VTS_L_REG, OV8865_VTS_L(mode->vts)); + if (ret) + return ret; + + if (mode->size_auto) { + /* Auto Size */ + + ret = ov8865_write(sensor, OV8865_AUTO_SIZE_CTRL_REG, + OV8865_AUTO_SIZE_CTRL_OFFSET_Y_REG | + OV8865_AUTO_SIZE_CTRL_OFFSET_X_REG | + OV8865_AUTO_SIZE_CTRL_CROP_END_Y_REG | + OV8865_AUTO_SIZE_CTRL_CROP_END_X_REG | + OV8865_AUTO_SIZE_CTRL_CROP_START_Y_REG | + OV8865_AUTO_SIZE_CTRL_CROP_START_X_REG); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_AUTO_SIZE_BOUNDARIES_REG, + OV8865_AUTO_SIZE_BOUNDARIES_Y(mode->size_auto_boundary_y) | + OV8865_AUTO_SIZE_BOUNDARIES_X(mode->size_auto_boundary_x)); + if (ret) + return ret; + } else { + /* Crop Start X */ + + ret = ov8865_write(sensor, OV8865_CROP_START_X_H_REG, + OV8865_CROP_START_X_H(mode->crop_start_x)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_CROP_START_X_L_REG, + OV8865_CROP_START_X_L(mode->crop_start_x)); + if (ret) + return ret; + + /* Offset X */ + + ret = ov8865_write(sensor, OV8865_OFFSET_X_H_REG, + OV8865_OFFSET_X_H(mode->offset_x)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_OFFSET_X_L_REG, + OV8865_OFFSET_X_L(mode->offset_x)); + if (ret) + return ret; + + /* Crop End X */ + + ret = ov8865_write(sensor, OV8865_CROP_END_X_H_REG, + OV8865_CROP_END_X_H(mode->crop_end_x)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_CROP_END_X_L_REG, + OV8865_CROP_END_X_L(mode->crop_end_x)); + if (ret) + return ret; + + /* Crop Start Y */ + + ret = ov8865_write(sensor, OV8865_CROP_START_Y_H_REG, + OV8865_CROP_START_Y_H(mode->crop_start_y)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_CROP_START_Y_L_REG, + OV8865_CROP_START_Y_L(mode->crop_start_y)); + if (ret) + return ret; + + /* Offset Y */ + + ret = ov8865_write(sensor, OV8865_OFFSET_Y_H_REG, + OV8865_OFFSET_Y_H(mode->offset_y)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_OFFSET_Y_L_REG, + OV8865_OFFSET_Y_L(mode->offset_y)); + if (ret) + return ret; + + /* Crop End Y */ + + ret = ov8865_write(sensor, OV8865_CROP_END_Y_H_REG, + OV8865_CROP_END_Y_H(mode->crop_end_y)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_CROP_END_Y_L_REG, + OV8865_CROP_END_Y_L(mode->crop_end_y)); + if (ret) + return ret; + } + + /* VFIFO */ + + ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_H_REG, + OV8865_VFIFO_READ_START_H(mode->vfifo_read_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_VFIFO_READ_START_L_REG, + OV8865_VFIFO_READ_START_L(mode->vfifo_read_start)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_ABLC_NUM_REG, + OV8865_ABLC_NUM(mode->ablc_num)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_ZLINE_NUM_REG, + OV8865_ZLINE_NUM(mode->zline_num)); + if (ret) + return ret; + + /* Binning */ + + ret = ov8865_mode_binning_configure(sensor, mode); + if (ret) + return ret; + + /* Black Level */ + + ret = ov8865_mode_black_level_configure(sensor, mode); + if (ret) + return ret; + + /* PLLs */ + + ret = ov8865_mode_pll1_configure(sensor, mode, mbus_code); + if (ret) + return ret; + + ret = ov8865_mode_pll2_configure(sensor, mode); + if (ret) + return ret; + + ret = ov8865_mode_sclk_configure(sensor, mode); + if (ret) + return ret; + + /* Extra registers */ + + if (mode->register_values) { + ret = ov8865_write_sequence(sensor, mode->register_values, + mode->register_values_count); + if (ret) + return ret; + } + + return 0; +} + +static unsigned long ov8865_mode_mipi_clk_rate(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode) +{ + const struct ov8865_pll1_config *config = mode->pll1_config; + unsigned long pll1_rate; + + pll1_rate = ov8865_mode_pll1_rate(sensor, mode); + + return pll1_rate / config->m_div / 2; +} + +/* Exposure */ + +static int ov8865_exposure_configure(struct ov8865_sensor *sensor, u32 exposure) +{ + int ret; + + ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_HH_REG, + OV8865_EXPOSURE_CTRL_HH(exposure)); + if (ret) + return ret; + + ret = ov8865_write(sensor, OV8865_EXPOSURE_CTRL_H_REG, + OV8865_EXPOSURE_CTRL_H(exposure)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_EXPOSURE_CTRL_L_REG, + OV8865_EXPOSURE_CTRL_L(exposure)); +} + +/* Gain */ + +static int ov8865_gain_configure(struct ov8865_sensor *sensor, u32 gain) +{ + int ret; + + ret = ov8865_write(sensor, OV8865_GAIN_CTRL_H_REG, + OV8865_GAIN_CTRL_H(gain)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_GAIN_CTRL_L_REG, + OV8865_GAIN_CTRL_L(gain)); +} + +/* White Balance */ + +static int ov8865_red_balance_configure(struct ov8865_sensor *sensor, + u32 red_balance) +{ + int ret; + + ret = ov8865_write(sensor, OV8865_ISP_GAIN_RED_H_REG, + OV8865_ISP_GAIN_RED_H(red_balance)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_ISP_GAIN_RED_L_REG, + OV8865_ISP_GAIN_RED_L(red_balance)); +} + +static int ov8865_blue_balance_configure(struct ov8865_sensor *sensor, + u32 blue_balance) +{ + int ret; + + ret = ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_H_REG, + OV8865_ISP_GAIN_BLUE_H(blue_balance)); + if (ret) + return ret; + + return ov8865_write(sensor, OV8865_ISP_GAIN_BLUE_L_REG, + OV8865_ISP_GAIN_BLUE_L(blue_balance)); +} + +/* Flip */ + +static int ov8865_flip_vert_configure(struct ov8865_sensor *sensor, bool enable) +{ + u8 bits = OV8865_FORMAT1_FLIP_VERT_ISP_EN | + OV8865_FORMAT1_FLIP_VERT_SENSOR_EN; + + return ov8865_update_bits(sensor, OV8865_FORMAT1_REG, bits, + enable ? bits : 0); +} + +static int ov8865_flip_horz_configure(struct ov8865_sensor *sensor, bool enable) +{ + u8 bits = OV8865_FORMAT2_FLIP_HORZ_ISP_EN | + OV8865_FORMAT2_FLIP_HORZ_SENSOR_EN; + + return ov8865_update_bits(sensor, OV8865_FORMAT2_REG, bits, + enable ? bits : 0); +} + +/* Test Pattern */ + +static int ov8865_test_pattern_configure(struct ov8865_sensor *sensor, + unsigned int index) +{ + if (index >= ARRAY_SIZE(ov8865_test_pattern_bits)) + return -EINVAL; + + return ov8865_write(sensor, OV8865_PRE_CTRL0_REG, + ov8865_test_pattern_bits[index]); +} + +/* State */ + +static int ov8865_state_mipi_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode, + u32 mbus_code) +{ + struct ov8865_ctrls *ctrls = &sensor->ctrls; + struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 = + &sensor->endpoint.bus.mipi_csi2; + unsigned long mipi_clk_rate; + unsigned int bits_per_sample; + unsigned int lanes_count; + unsigned int i, j; + s64 mipi_pixel_rate; + + mipi_clk_rate = ov8865_mode_mipi_clk_rate(sensor, mode); + if (!mipi_clk_rate) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(ov8865_link_freq_menu); i++) { + s64 freq = ov8865_link_freq_menu[i]; + + if (freq == mipi_clk_rate) + break; + } + + for (j = 0; j < sensor->endpoint.nr_of_link_frequencies; j++) { + u64 freq = sensor->endpoint.link_frequencies[j]; + + if (freq == mipi_clk_rate) + break; + } + + if (i == ARRAY_SIZE(ov8865_link_freq_menu)) { + dev_err(sensor->dev, + "failed to find %lu clk rate in link freq\n", + mipi_clk_rate); + } else if (j == sensor->endpoint.nr_of_link_frequencies) { + dev_err(sensor->dev, + "failed to find %lu clk rate in endpoint link-frequencies\n", + mipi_clk_rate); + } else { + __v4l2_ctrl_s_ctrl(ctrls->link_freq, i); + } + + switch (mbus_code) { + case MEDIA_BUS_FMT_SBGGR10_1X10: + bits_per_sample = 10; + break; + default: + return -EINVAL; + } + + lanes_count = bus_mipi_csi2->num_data_lanes; + mipi_pixel_rate = mipi_clk_rate * 2 * lanes_count / bits_per_sample; + + __v4l2_ctrl_s_ctrl_int64(ctrls->pixel_rate, mipi_pixel_rate); + + return 0; +} + +static int ov8865_state_configure(struct ov8865_sensor *sensor, + const struct ov8865_mode *mode, + u32 mbus_code) +{ + int ret; + + if (sensor->state.streaming) + return -EBUSY; + + /* State will be configured at first power on otherwise. */ + if (pm_runtime_enabled(sensor->dev) && + !pm_runtime_suspended(sensor->dev)) { + ret = ov8865_mode_configure(sensor, mode, mbus_code); + if (ret) + return ret; + } + + ret = ov8865_state_mipi_configure(sensor, mode, mbus_code); + if (ret) + return ret; + + sensor->state.mode = mode; + sensor->state.mbus_code = mbus_code; + + return 0; +} + +static int ov8865_state_init(struct ov8865_sensor *sensor) +{ + return ov8865_state_configure(sensor, &ov8865_modes[0], + ov8865_mbus_codes[0]); +} + +/* Sensor Base */ + +static int ov8865_sensor_init(struct ov8865_sensor *sensor) +{ + int ret; + + ret = ov8865_sw_reset(sensor); + if (ret) { + dev_err(sensor->dev, "failed to perform sw reset\n"); + return ret; + } + + ret = ov8865_sw_standby(sensor, 1); + if (ret) { + dev_err(sensor->dev, "failed to set sensor standby\n"); + return ret; + } + + ret = ov8865_chip_id_check(sensor); + if (ret) { + dev_err(sensor->dev, "failed to check sensor chip id\n"); + return ret; + } + + ret = ov8865_write_sequence(sensor, ov8865_init_sequence, + ARRAY_SIZE(ov8865_init_sequence)); + if (ret) { + dev_err(sensor->dev, "failed to write init sequence\n"); + return ret; + } + + ret = ov8865_charge_pump_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure pad\n"); + return ret; + } + + ret = ov8865_mipi_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure MIPI\n"); + return ret; + } + + ret = ov8865_isp_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure ISP\n"); + return ret; + } + + ret = ov8865_black_level_configure(sensor); + if (ret) { + dev_err(sensor->dev, "failed to configure black level\n"); + return ret; + } + + /* Configure current mode. */ + ret = ov8865_state_configure(sensor, sensor->state.mode, + sensor->state.mbus_code); + if (ret) { + dev_err(sensor->dev, "failed to configure state\n"); + return ret; + } + + return 0; +} + +static int ov8865_sensor_power(struct ov8865_sensor *sensor, bool on) +{ + /* Keep initialized to zero for disable label. */ + int ret = 0; + + if (on) { + gpiod_set_value_cansleep(sensor->reset, 1); + gpiod_set_value_cansleep(sensor->powerdown, 1); + + ret = regulator_enable(sensor->dovdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable DOVDD regulator\n"); + goto disable; + } + + ret = regulator_enable(sensor->avdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable AVDD regulator\n"); + goto disable; + } + + ret = regulator_enable(sensor->dvdd); + if (ret) { + dev_err(sensor->dev, + "failed to enable DVDD regulator\n"); + goto disable; + } + + ret = clk_prepare_enable(sensor->extclk); + if (ret) { + dev_err(sensor->dev, "failed to enable EXTCLK clock\n"); + goto disable; + } + + gpiod_set_value_cansleep(sensor->reset, 0); + gpiod_set_value_cansleep(sensor->powerdown, 0); + + /* Time to enter streaming mode according to power timings. */ + usleep_range(10000, 12000); + } else { +disable: + gpiod_set_value_cansleep(sensor->powerdown, 1); + gpiod_set_value_cansleep(sensor->reset, 1); + + clk_disable_unprepare(sensor->extclk); + + regulator_disable(sensor->dvdd); + regulator_disable(sensor->avdd); + regulator_disable(sensor->dovdd); + } + + return ret; +} + +/* Controls */ + +static int ov8865_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *subdev = ov8865_ctrl_subdev(ctrl); + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + unsigned int index; + int ret; + + /* Wait for the sensor to be on before setting controls. */ + if (pm_runtime_suspended(sensor->dev)) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + ret = ov8865_exposure_configure(sensor, ctrl->val); + if (ret) + return ret; + break; + case V4L2_CID_GAIN: + ret = ov8865_gain_configure(sensor, ctrl->val); + if (ret) + return ret; + break; + case V4L2_CID_RED_BALANCE: + return ov8865_red_balance_configure(sensor, ctrl->val); + case V4L2_CID_BLUE_BALANCE: + return ov8865_blue_balance_configure(sensor, ctrl->val); + case V4L2_CID_HFLIP: + return ov8865_flip_horz_configure(sensor, !!ctrl->val); + case V4L2_CID_VFLIP: + return ov8865_flip_vert_configure(sensor, !!ctrl->val); + case V4L2_CID_TEST_PATTERN: + index = (unsigned int)ctrl->val; + return ov8865_test_pattern_configure(sensor, index); + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops ov8865_ctrl_ops = { + .s_ctrl = ov8865_s_ctrl, +}; + +static int ov8865_ctrls_init(struct ov8865_sensor *sensor) +{ + struct ov8865_ctrls *ctrls = &sensor->ctrls; + struct v4l2_ctrl_handler *handler = &ctrls->handler; + const struct v4l2_ctrl_ops *ops = &ov8865_ctrl_ops; + int ret; + + v4l2_ctrl_handler_init(handler, 32); + + /* Use our mutex for ctrl locking. */ + handler->lock = &sensor->mutex; + + /* Exposure */ + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_EXPOSURE, 16, 1048575, 16, + 512); + + /* Gain */ + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_GAIN, 128, 8191, 128, 128); + + /* White Balance */ + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_RED_BALANCE, 1, 32767, 1, + 1024); + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_BLUE_BALANCE, 1, 32767, 1, + 1024); + + /* Flip */ + + v4l2_ctrl_new_std(handler, ops, V4L2_CID_HFLIP, 0, 1, 1, 0); + v4l2_ctrl_new_std(handler, ops, V4L2_CID_VFLIP, 0, 1, 1, 0); + + /* Test Pattern */ + + v4l2_ctrl_new_std_menu_items(handler, ops, V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(ov8865_test_pattern_menu) - 1, + 0, 0, ov8865_test_pattern_menu); + + /* MIPI CSI-2 */ + + ctrls->link_freq = + v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, + ARRAY_SIZE(ov8865_link_freq_menu) - 1, + 0, ov8865_link_freq_menu); + + ctrls->pixel_rate = + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 1, + INT_MAX, 1, 1); + + if (handler->error) { + ret = handler->error; + goto error_ctrls; + } + + ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; + ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY; + + sensor->subdev.ctrl_handler = handler; + + return 0; + +error_ctrls: + v4l2_ctrl_handler_free(handler); + + return ret; +} + +/* Subdev Video Operations */ + +static int ov8865_s_stream(struct v4l2_subdev *subdev, int enable) +{ + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + struct ov8865_state *state = &sensor->state; + int ret; + + if (enable) { + ret = pm_runtime_get_sync(sensor->dev); + if (ret < 0) { + pm_runtime_put_noidle(sensor->dev); + return ret; + } + } + + mutex_lock(&sensor->mutex); + ret = ov8865_sw_standby(sensor, !enable); + mutex_unlock(&sensor->mutex); + + if (ret) + return ret; + + state->streaming = !!enable; + + if (!enable) + pm_runtime_put(sensor->dev); + + return 0; +} + +static int ov8865_g_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + const struct ov8865_mode *mode; + int ret = 0; + + mutex_lock(&sensor->mutex); + + mode = sensor->state.mode; + interval->interval = mode->frame_interval; + + mutex_unlock(&sensor->mutex); + + return ret; +} + +static const struct v4l2_subdev_video_ops ov8865_subdev_video_ops = { + .s_stream = ov8865_s_stream, + .g_frame_interval = ov8865_g_frame_interval, + .s_frame_interval = ov8865_g_frame_interval, +}; + +/* Subdev Pad Operations */ + +static int ov8865_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_mbus_code_enum *code_enum) +{ + if (code_enum->index >= ARRAY_SIZE(ov8865_mbus_codes)) + return -EINVAL; + + code_enum->code = ov8865_mbus_codes[code_enum->index]; + + return 0; +} + +static void ov8865_mbus_format_fill(struct v4l2_mbus_framefmt *mbus_format, + u32 mbus_code, + const struct ov8865_mode *mode) +{ + mbus_format->width = mode->output_size_x; + mbus_format->height = mode->output_size_y; + mbus_format->code = mbus_code; + + mbus_format->field = V4L2_FIELD_NONE; + mbus_format->colorspace = V4L2_COLORSPACE_RAW; + mbus_format->ycbcr_enc = + V4L2_MAP_YCBCR_ENC_DEFAULT(mbus_format->colorspace); + mbus_format->quantization = V4L2_QUANTIZATION_FULL_RANGE; + mbus_format->xfer_func = + V4L2_MAP_XFER_FUNC_DEFAULT(mbus_format->colorspace); +} + +static int ov8865_get_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_format *format) +{ + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + struct v4l2_mbus_framefmt *mbus_format = &format->format; + + mutex_lock(&sensor->mutex); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + *mbus_format = *v4l2_subdev_get_try_format(subdev, config, + format->pad); + else + ov8865_mbus_format_fill(mbus_format, sensor->state.mbus_code, + sensor->state.mode); + + mutex_unlock(&sensor->mutex); + + return 0; +} + +static int ov8865_set_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_format *format) +{ + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + struct v4l2_mbus_framefmt *mbus_format = &format->format; + const struct ov8865_mode *mode; + u32 mbus_code = 0; + unsigned int index; + int ret = 0; + + mutex_lock(&sensor->mutex); + + if (sensor->state.streaming) { + ret = -EBUSY; + goto complete; + } + + /* Try to find requested mbus code. */ + for (index = 0; index < ARRAY_SIZE(ov8865_mbus_codes); index++) { + if (ov8865_mbus_codes[index] == mbus_format->code) { + mbus_code = mbus_format->code; + break; + } + } + + /* Fallback to default. */ + if (!mbus_code) + mbus_code = ov8865_mbus_codes[0]; + + /* Find the mode with nearest dimensions. */ + mode = v4l2_find_nearest_size(ov8865_modes, ARRAY_SIZE(ov8865_modes), + output_size_x, output_size_y, + mbus_format->width, mbus_format->height); + if (!mode) { + ret = -EINVAL; + goto complete; + } + + ov8865_mbus_format_fill(mbus_format, mbus_code, mode); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + *v4l2_subdev_get_try_format(subdev, config, format->pad) = + *mbus_format; + else if (sensor->state.mode != mode || + sensor->state.mbus_code != mbus_code) + ret = ov8865_state_configure(sensor, mode, mbus_code); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov8865_enum_frame_size(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_frame_size_enum *size_enum) +{ + const struct ov8865_mode *mode; + + if (size_enum->index >= ARRAY_SIZE(ov8865_modes)) + return -EINVAL; + + mode = &ov8865_modes[size_enum->index]; + + size_enum->min_width = size_enum->max_width = mode->output_size_x; + size_enum->min_height = size_enum->max_height = mode->output_size_y; + + return 0; +} + +static int ov8865_enum_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *config, + struct v4l2_subdev_frame_interval_enum *interval_enum) +{ + const struct ov8865_mode *mode = NULL; + unsigned int mode_index; + unsigned int interval_index; + + if (interval_enum->index > 0) + return -EINVAL; + /* + * Multiple modes with the same dimensions may have different frame + * intervals, so look up each relevant mode. + */ + for (mode_index = 0, interval_index = 0; + mode_index < ARRAY_SIZE(ov8865_modes); mode_index++) { + mode = &ov8865_modes[mode_index]; + + if (mode->output_size_x == interval_enum->width && + mode->output_size_y == interval_enum->height) { + if (interval_index == interval_enum->index) + break; + + interval_index++; + } + } + + if (mode_index == ARRAY_SIZE(ov8865_modes) || !mode) + return -EINVAL; + + interval_enum->interval = mode->frame_interval; + + return 0; +} + +static const struct v4l2_subdev_pad_ops ov8865_subdev_pad_ops = { + .enum_mbus_code = ov8865_enum_mbus_code, + .get_fmt = ov8865_get_fmt, + .set_fmt = ov8865_set_fmt, + .enum_frame_size = ov8865_enum_frame_size, + .enum_frame_interval = ov8865_enum_frame_interval, +}; + +static const struct v4l2_subdev_ops ov8865_subdev_ops = { + .video = &ov8865_subdev_video_ops, + .pad = &ov8865_subdev_pad_ops, +}; + +static int ov8865_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + struct ov8865_state *state = &sensor->state; + int ret = 0; + + mutex_lock(&sensor->mutex); + + if (state->streaming) { + ret = ov8865_sw_standby(sensor, true); + if (ret) + goto complete; + } + + ret = ov8865_sensor_power(sensor, false); + if (ret) + ov8865_sw_standby(sensor, false); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov8865_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + struct ov8865_state *state = &sensor->state; + int ret = 0; + + mutex_lock(&sensor->mutex); + + ret = ov8865_sensor_power(sensor, true); + if (ret) + goto complete; + + ret = ov8865_sensor_init(sensor); + if (ret) + goto error_power; + + ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); + if (ret) + goto error_power; + + if (state->streaming) { + ret = ov8865_sw_standby(sensor, false); + if (ret) + goto error_power; + } + + goto complete; + +error_power: + ov8865_sensor_power(sensor, false); + +complete: + mutex_unlock(&sensor->mutex); + + return ret; +} + +static int ov8865_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct fwnode_handle *handle; + struct ov8865_sensor *sensor; + struct v4l2_subdev *subdev; + struct media_pad *pad; + unsigned long rate; + int ret; + + sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->dev = dev; + sensor->i2c_client = client; + + /* Graph Endpoint */ + + handle = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL); + if (!handle) { + dev_err(dev, "unable to find endpoint node\n"); + return -EINVAL; + } + + sensor->endpoint.bus_type = V4L2_MBUS_CSI2_DPHY; + + ret = v4l2_fwnode_endpoint_alloc_parse(handle, &sensor->endpoint); + fwnode_handle_put(handle); + if (ret) { + dev_err(dev, "failed to parse endpoint node\n"); + return ret; + } + + /* GPIOs */ + + sensor->powerdown = devm_gpiod_get_optional(dev, "powerdown", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->powerdown)) { + ret = PTR_ERR(sensor->powerdown); + goto error_endpoint; + } + + sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(sensor->reset)) { + ret = PTR_ERR(sensor->reset); + goto error_endpoint; + } + + /* Regulators */ + + /* DVDD: digital core */ + sensor->dvdd = devm_regulator_get(dev, "dvdd"); + if (IS_ERR(sensor->dvdd)) { + dev_err(dev, "cannot get DVDD (digital core) regulator\n"); + ret = PTR_ERR(sensor->dvdd); + goto error_endpoint; + } + + /* DOVDD: digital I/O */ + sensor->dovdd = devm_regulator_get(dev, "dovdd"); + if (IS_ERR(sensor->dovdd)) { + dev_err(dev, "cannot get DOVDD (digital I/O) regulator\n"); + ret = PTR_ERR(sensor->dovdd); + goto error_endpoint; + } + + /* AVDD: analog */ + sensor->avdd = devm_regulator_get(dev, "avdd"); + if (IS_ERR(sensor->avdd)) { + dev_err(dev, "cannot get AVDD (analog) regulator\n"); + ret = PTR_ERR(sensor->avdd); + goto error_endpoint; + } + + /* External Clock */ + + sensor->extclk = devm_clk_get(dev, NULL); + if (IS_ERR(sensor->extclk)) { + dev_err(dev, "failed to get external clock\n"); + ret = PTR_ERR(sensor->extclk); + goto error_endpoint; + } + + rate = clk_get_rate(sensor->extclk); + if (rate != OV8865_EXTCLK_RATE) { + dev_err(dev, "clock rate %lu Hz is unsupported\n", rate); + ret = -EINVAL; + goto error_endpoint; + } + + /* Subdev, entity and pad */ + + subdev = &sensor->subdev; + v4l2_i2c_subdev_init(subdev, client, &ov8865_subdev_ops); + + subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + subdev->entity.function = MEDIA_ENT_F_CAM_SENSOR; + + pad = &sensor->pad; + pad->flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&subdev->entity, 1, pad); + if (ret) + goto error_entity; + + /* Mutex */ + + mutex_init(&sensor->mutex); + + /* Sensor */ + + ret = ov8865_ctrls_init(sensor); + if (ret) + goto error_mutex; + + ret = ov8865_state_init(sensor); + if (ret) + goto error_ctrls; + + /* Runtime PM */ + + pm_runtime_enable(sensor->dev); + pm_runtime_set_suspended(sensor->dev); + + /* V4L2 subdev register */ + + ret = v4l2_async_register_subdev_sensor_common(subdev); + if (ret) + goto error_pm; + + return 0; + +error_pm: + pm_runtime_disable(sensor->dev); + +error_ctrls: + v4l2_ctrl_handler_free(&sensor->ctrls.handler); + +error_mutex: + mutex_destroy(&sensor->mutex); + +error_entity: + media_entity_cleanup(&sensor->subdev.entity); + +error_endpoint: + v4l2_fwnode_endpoint_free(&sensor->endpoint); + + return ret; +} + +static int ov8865_remove(struct i2c_client *client) +{ + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct ov8865_sensor *sensor = ov8865_subdev_sensor(subdev); + + v4l2_async_unregister_subdev(subdev); + pm_runtime_disable(sensor->dev); + v4l2_ctrl_handler_free(&sensor->ctrls.handler); + mutex_destroy(&sensor->mutex); + media_entity_cleanup(&subdev->entity); + + v4l2_fwnode_endpoint_free(&sensor->endpoint); + + return 0; +} + +static const struct dev_pm_ops ov8865_pm_ops = { + SET_RUNTIME_PM_OPS(ov8865_suspend, ov8865_resume, NULL) +}; + +static const struct of_device_id ov8865_of_match[] = { + { .compatible = "ovti,ov8865" }, + { } +}; +MODULE_DEVICE_TABLE(of, ov8865_of_match); + +static struct i2c_driver ov8865_driver = { + .driver = { + .name = "ov8865", + .of_match_table = ov8865_of_match, + .pm = &ov8865_pm_ops, + }, + .probe_new = ov8865_probe, + .remove = ov8865_remove, +}; + +module_i2c_driver(ov8865_driver); + +MODULE_AUTHOR("Paul Kocialkowski <paul.kocialkowski@bootlin.com>"); +MODULE_DESCRIPTION("V4L2 driver for the OmniVision OV8865 image sensor"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/ov9640.c b/drivers/media/i2c/ov9640.c index e2a25240fc85..d36b04c49628 100644 --- a/drivers/media/i2c/ov9640.c +++ b/drivers/media/i2c/ov9640.c @@ -17,6 +17,7 @@ * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> */ +#include <linux/clk.h> #include <linux/init.h> #include <linux/module.h> #include <linux/i2c.h> @@ -26,7 +27,6 @@ #include <linux/videodev2.h> #include <media/v4l2-async.h> -#include <media/v4l2-clk.h> #include <media/v4l2-common.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> @@ -333,13 +333,13 @@ static int ov9640_s_power(struct v4l2_subdev *sd, int on) if (on) { gpiod_set_value(priv->gpio_power, 1); usleep_range(1000, 2000); - ret = v4l2_clk_enable(priv->clk); + ret = clk_prepare_enable(priv->clk); usleep_range(1000, 2000); gpiod_set_value(priv->gpio_reset, 0); } else { gpiod_set_value(priv->gpio_reset, 1); usleep_range(1000, 2000); - v4l2_clk_disable(priv->clk); + clk_disable_unprepare(priv->clk); usleep_range(1000, 2000); gpiod_set_value(priv->gpio_power, 0); } @@ -719,7 +719,7 @@ static int ov9640_probe(struct i2c_client *client, priv->subdev.ctrl_handler = &priv->hdl; - priv->clk = v4l2_clk_get(&client->dev, "mclk"); + priv->clk = devm_clk_get(&client->dev, "mclk"); if (IS_ERR(priv->clk)) { ret = PTR_ERR(priv->clk); goto ectrlinit; @@ -727,17 +727,15 @@ static int ov9640_probe(struct i2c_client *client, ret = ov9640_video_probe(client); if (ret) - goto eprobe; + goto ectrlinit; priv->subdev.dev = &client->dev; ret = v4l2_async_register_subdev(&priv->subdev); if (ret) - goto eprobe; + goto ectrlinit; return 0; -eprobe: - v4l2_clk_put(priv->clk); ectrlinit: v4l2_ctrl_handler_free(&priv->hdl); @@ -749,7 +747,6 @@ static int ov9640_remove(struct i2c_client *client) struct v4l2_subdev *sd = i2c_get_clientdata(client); struct ov9640_priv *priv = to_ov9640_sensor(sd); - v4l2_clk_put(priv->clk); v4l2_async_unregister_subdev(&priv->subdev); v4l2_ctrl_handler_free(&priv->hdl); diff --git a/drivers/media/i2c/ov9640.h b/drivers/media/i2c/ov9640.h index a8ed6992c1a8..c105594b2472 100644 --- a/drivers/media/i2c/ov9640.h +++ b/drivers/media/i2c/ov9640.h @@ -196,7 +196,7 @@ struct ov9640_reg { struct ov9640_priv { struct v4l2_subdev subdev; struct v4l2_ctrl_handler hdl; - struct v4l2_clk *clk; + struct clk *clk; struct gpio_desc *gpio_power; struct gpio_desc *gpio_reset; diff --git a/drivers/media/i2c/rdacm20.c b/drivers/media/i2c/rdacm20.c index 16bcb764b0e0..90eb73f0e6e9 100644 --- a/drivers/media/i2c/rdacm20.c +++ b/drivers/media/i2c/rdacm20.c @@ -435,7 +435,7 @@ static int rdacm20_get_fmt(struct v4l2_subdev *sd, return 0; } -static struct v4l2_subdev_video_ops rdacm20_video_ops = { +static const struct v4l2_subdev_video_ops rdacm20_video_ops = { .s_stream = rdacm20_s_stream, }; @@ -445,7 +445,7 @@ static const struct v4l2_subdev_pad_ops rdacm20_subdev_pad_ops = { .set_fmt = rdacm20_get_fmt, }; -static struct v4l2_subdev_ops rdacm20_subdev_ops = { +static const struct v4l2_subdev_ops rdacm20_subdev_ops = { .video = &rdacm20_video_ops, .pad = &rdacm20_subdev_pad_ops, }; diff --git a/drivers/media/i2c/rdacm21.c b/drivers/media/i2c/rdacm21.c new file mode 100644 index 000000000000..dcc21515e5a4 --- /dev/null +++ b/drivers/media/i2c/rdacm21.c @@ -0,0 +1,623 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * IMI RDACM21 GMSL Camera Driver + * + * Copyright (C) 2017-2020 Jacopo Mondi + * Copyright (C) 2017-2019 Kieran Bingham + * Copyright (C) 2017-2019 Laurent Pinchart + * Copyright (C) 2017-2019 Niklas Söderlund + * Copyright (C) 2016 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + */ + +#include <linux/delay.h> +#include <linux/fwnode.h> +#include <linux/init.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/videodev2.h> + +#include <media/v4l2-async.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-subdev.h> +#include "max9271.h" + +#define MAX9271_RESET_CYCLES 10 + +#define OV490_I2C_ADDRESS 0x24 + +#define OV490_PAGE_HIGH_REG 0xfffd +#define OV490_PAGE_LOW_REG 0xfffe + +/* + * The SCCB slave handling is undocumented; the registers naming scheme is + * totally arbitrary. + */ +#define OV490_SCCB_SLAVE_WRITE 0x00 +#define OV490_SCCB_SLAVE_READ 0x01 +#define OV490_SCCB_SLAVE0_DIR 0x80195000 +#define OV490_SCCB_SLAVE0_ADDR_HIGH 0x80195001 +#define OV490_SCCB_SLAVE0_ADDR_LOW 0x80195002 + +#define OV490_DVP_CTRL3 0x80286009 + +#define OV490_ODS_CTRL_FRAME_OUTPUT_EN 0x0c +#define OV490_ODS_CTRL 0x8029d000 + +#define OV490_HOST_CMD 0x808000c0 +#define OV490_HOST_CMD_TRIGGER 0xc1 + +#define OV490_ID_VAL 0x0490 +#define OV490_ID(_p, _v) ((((_p) & 0xff) << 8) | ((_v) & 0xff)) +#define OV490_PID 0x8080300a +#define OV490_VER 0x8080300b +#define OV490_PID_TIMEOUT 20 +#define OV490_OUTPUT_EN_TIMEOUT 300 + +#define OV490_GPIO0 BIT(0) +#define OV490_SPWDN0 BIT(0) +#define OV490_GPIO_SEL0 0x80800050 +#define OV490_GPIO_SEL1 0x80800051 +#define OV490_GPIO_DIRECTION0 0x80800054 +#define OV490_GPIO_DIRECTION1 0x80800055 +#define OV490_GPIO_OUTPUT_VALUE0 0x80800058 +#define OV490_GPIO_OUTPUT_VALUE1 0x80800059 + +#define OV490_ISP_HSIZE_LOW 0x80820060 +#define OV490_ISP_HSIZE_HIGH 0x80820061 +#define OV490_ISP_VSIZE_LOW 0x80820062 +#define OV490_ISP_VSIZE_HIGH 0x80820063 + +#define OV10640_ID_HIGH 0xa6 +#define OV10640_CHIP_ID 0x300a +#define OV10640_PIXEL_RATE 55000000 + +struct rdacm21_device { + struct device *dev; + struct max9271_device serializer; + struct i2c_client *isp; + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt fmt; + struct v4l2_ctrl_handler ctrls; + u32 addrs[2]; + u16 last_page; +}; + +static inline struct rdacm21_device *sd_to_rdacm21(struct v4l2_subdev *sd) +{ + return container_of(sd, struct rdacm21_device, sd); +} + +static const struct ov490_reg { + u16 reg; + u8 val; +} ov490_regs_wizard[] = { + {0xfffd, 0x80}, + {0xfffe, 0x82}, + {0x0071, 0x11}, + {0x0075, 0x11}, + {0xfffe, 0x29}, + {0x6010, 0x01}, + /* + * OV490 EMB line disable in YUV and RAW data, + * NOTE: EMB line is still used in ISP and sensor + */ + {0xe000, 0x14}, + {0xfffe, 0x28}, + {0x6000, 0x04}, + {0x6004, 0x00}, + /* + * PCLK polarity - useless due to silicon bug. + * Use 0x808000bb register instead. + */ + {0x6008, 0x00}, + {0xfffe, 0x80}, + {0x0091, 0x00}, + /* bit[3]=0 - PCLK polarity workaround. */ + {0x00bb, 0x1d}, + /* Ov490 FSIN: app_fsin_from_fsync */ + {0xfffe, 0x85}, + {0x0008, 0x00}, + {0x0009, 0x01}, + /* FSIN0 source. */ + {0x000A, 0x05}, + {0x000B, 0x00}, + /* FSIN0 delay. */ + {0x0030, 0x02}, + {0x0031, 0x00}, + {0x0032, 0x00}, + {0x0033, 0x00}, + /* FSIN1 delay. */ + {0x0038, 0x02}, + {0x0039, 0x00}, + {0x003A, 0x00}, + {0x003B, 0x00}, + /* FSIN0 length. */ + {0x0070, 0x2C}, + {0x0071, 0x01}, + {0x0072, 0x00}, + {0x0073, 0x00}, + /* FSIN1 length. */ + {0x0074, 0x64}, + {0x0075, 0x00}, + {0x0076, 0x00}, + {0x0077, 0x00}, + {0x0000, 0x14}, + {0x0001, 0x00}, + {0x0002, 0x00}, + {0x0003, 0x00}, + /* + * Load fsin0,load fsin1,load other, + * It will be cleared automatically. + */ + {0x0004, 0x32}, + {0x0005, 0x00}, + {0x0006, 0x00}, + {0x0007, 0x00}, + {0xfffe, 0x80}, + /* Sensor FSIN. */ + {0x0081, 0x00}, + /* ov10640 FSIN enable */ + {0xfffe, 0x19}, + {0x5000, 0x00}, + {0x5001, 0x30}, + {0x5002, 0x8c}, + {0x5003, 0xb2}, + {0xfffe, 0x80}, + {0x00c0, 0xc1}, + /* ov10640 HFLIP=1 by default */ + {0xfffe, 0x19}, + {0x5000, 0x01}, + {0x5001, 0x00}, + {0xfffe, 0x80}, + {0x00c0, 0xdc}, +}; + +static int ov490_read(struct rdacm21_device *dev, u16 reg, u8 *val) +{ + u8 buf[2] = { reg >> 8, reg }; + int ret; + + ret = i2c_master_send(dev->isp, buf, 2); + if (ret == 2) + ret = i2c_master_recv(dev->isp, val, 1); + + if (ret < 0) { + dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n", + __func__, reg, ret); + return ret; + } + + return 0; +} + +static int ov490_write(struct rdacm21_device *dev, u16 reg, u8 val) +{ + u8 buf[3] = { reg >> 8, reg, val }; + int ret; + + ret = i2c_master_send(dev->isp, buf, 3); + if (ret < 0) { + dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n", + __func__, reg, ret); + return ret; + } + + return 0; +} + +static int ov490_set_page(struct rdacm21_device *dev, u16 page) +{ + u8 page_high = page >> 8; + u8 page_low = page; + int ret; + + if (page == dev->last_page) + return 0; + + if (page_high != (dev->last_page >> 8)) { + ret = ov490_write(dev, OV490_PAGE_HIGH_REG, page_high); + if (ret) + return ret; + } + + if (page_low != (u8)dev->last_page) { + ret = ov490_write(dev, OV490_PAGE_LOW_REG, page_low); + if (ret) + return ret; + } + + dev->last_page = page; + usleep_range(100, 150); + + return 0; +} + +static int ov490_read_reg(struct rdacm21_device *dev, u32 reg, u8 *val) +{ + int ret; + + ret = ov490_set_page(dev, reg >> 16); + if (ret) + return ret; + + ret = ov490_read(dev, (u16)reg, val); + if (ret) + return ret; + + dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, *val); + + return 0; +} + +static int ov490_write_reg(struct rdacm21_device *dev, u32 reg, u8 val) +{ + int ret; + + ret = ov490_set_page(dev, reg >> 16); + if (ret) + return ret; + + ret = ov490_write(dev, (u16)reg, val); + if (ret) + return ret; + + dev_dbg(dev->dev, "%s: 0x%08x = 0x%02x\n", __func__, reg, val); + + return 0; +} + +static int rdacm21_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct rdacm21_device *dev = sd_to_rdacm21(sd); + + /* + * Enable serial link now that the ISP provides a valid pixel clock + * to start serializing video data on the GMSL link. + */ + return max9271_set_serial_link(&dev->serializer, enable); +} + +static int rdacm21_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->pad || code->index > 0) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_YUYV8_1X16; + + return 0; +} + +static int rdacm21_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct rdacm21_device *dev = sd_to_rdacm21(sd); + + if (format->pad) + return -EINVAL; + + mf->width = dev->fmt.width; + mf->height = dev->fmt.height; + mf->code = MEDIA_BUS_FMT_YUYV8_1X16; + mf->colorspace = V4L2_COLORSPACE_SRGB; + mf->field = V4L2_FIELD_NONE; + mf->ycbcr_enc = V4L2_YCBCR_ENC_601; + mf->quantization = V4L2_QUANTIZATION_FULL_RANGE; + mf->xfer_func = V4L2_XFER_FUNC_NONE; + + return 0; +} + +static const struct v4l2_subdev_video_ops rdacm21_video_ops = { + .s_stream = rdacm21_s_stream, +}; + +static const struct v4l2_subdev_pad_ops rdacm21_subdev_pad_ops = { + .enum_mbus_code = rdacm21_enum_mbus_code, + .get_fmt = rdacm21_get_fmt, + .set_fmt = rdacm21_get_fmt, +}; + +static const struct v4l2_subdev_ops rdacm21_subdev_ops = { + .video = &rdacm21_video_ops, + .pad = &rdacm21_subdev_pad_ops, +}; + +static int ov10640_initialize(struct rdacm21_device *dev) +{ + u8 val; + + /* Power-up OV10640 by setting RESETB and PWDNB pins high. */ + ov490_write_reg(dev, OV490_GPIO_SEL0, OV490_GPIO0); + ov490_write_reg(dev, OV490_GPIO_SEL1, OV490_SPWDN0); + ov490_write_reg(dev, OV490_GPIO_DIRECTION0, OV490_GPIO0); + ov490_write_reg(dev, OV490_GPIO_DIRECTION1, OV490_SPWDN0); + ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_GPIO0); + ov490_write_reg(dev, OV490_GPIO_OUTPUT_VALUE0, OV490_SPWDN0); + usleep_range(3000, 5000); + + /* Read OV10640 ID to test communications. */ + ov490_write_reg(dev, OV490_SCCB_SLAVE0_DIR, OV490_SCCB_SLAVE_READ); + ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_HIGH, OV10640_CHIP_ID >> 8); + ov490_write_reg(dev, OV490_SCCB_SLAVE0_ADDR_LOW, (u8)OV10640_CHIP_ID); + + /* Trigger SCCB slave transaction and give it some time to complete. */ + ov490_write_reg(dev, OV490_HOST_CMD, OV490_HOST_CMD_TRIGGER); + usleep_range(1000, 1500); + + ov490_read_reg(dev, OV490_SCCB_SLAVE0_DIR, &val); + if (val != OV10640_ID_HIGH) { + dev_err(dev->dev, "OV10640 ID mismatch: (0x%02x)\n", val); + return -ENODEV; + } + + dev_dbg(dev->dev, "OV10640 ID = 0x%2x\n", val); + + return 0; +} + +static int ov490_initialize(struct rdacm21_device *dev) +{ + u8 pid, ver, val; + unsigned int i; + int ret; + + /* + * Read OV490 Id to test communications. Give it up to 40msec to + * exit from reset. + */ + for (i = 0; i < OV490_PID_TIMEOUT; ++i) { + ret = ov490_read_reg(dev, OV490_PID, &pid); + if (ret == 0) + break; + usleep_range(1000, 2000); + } + if (i == OV490_PID_TIMEOUT) { + dev_err(dev->dev, "OV490 PID read failed (%d)\n", ret); + return ret; + } + + ret = ov490_read_reg(dev, OV490_VER, &ver); + if (ret < 0) + return ret; + + if (OV490_ID(pid, ver) != OV490_ID_VAL) { + dev_err(dev->dev, "OV490 ID mismatch (0x%04x)\n", + OV490_ID(pid, ver)); + return -ENODEV; + } + + /* Wait for firmware boot by reading streamon status. */ + for (i = 0; i < OV490_OUTPUT_EN_TIMEOUT; ++i) { + ov490_read_reg(dev, OV490_ODS_CTRL, &val); + if (val == OV490_ODS_CTRL_FRAME_OUTPUT_EN) + break; + usleep_range(1000, 2000); + } + if (i == OV490_OUTPUT_EN_TIMEOUT) { + dev_err(dev->dev, "Timeout waiting for firmware boot\n"); + return -ENODEV; + } + + ret = ov10640_initialize(dev); + if (ret) + return ret; + + /* Program OV490 with register-value table. */ + for (i = 0; i < ARRAY_SIZE(ov490_regs_wizard); ++i) { + ret = ov490_write(dev, ov490_regs_wizard[i].reg, + ov490_regs_wizard[i].val); + if (ret < 0) { + dev_err(dev->dev, + "%s: register %u (0x%04x) write failed (%d)\n", + __func__, i, ov490_regs_wizard[i].reg, ret); + + return -EIO; + } + + usleep_range(100, 150); + } + + /* + * The ISP is programmed with the content of a serial flash memory. + * Read the firmware configuration to reflect it through the V4L2 APIs. + */ + ov490_read_reg(dev, OV490_ISP_HSIZE_HIGH, &val); + dev->fmt.width = (val & 0xf) << 8; + ov490_read_reg(dev, OV490_ISP_HSIZE_LOW, &val); + dev->fmt.width |= (val & 0xff); + + ov490_read_reg(dev, OV490_ISP_VSIZE_HIGH, &val); + dev->fmt.height = (val & 0xf) << 8; + ov490_read_reg(dev, OV490_ISP_VSIZE_LOW, &val); + dev->fmt.height |= val & 0xff; + + /* Set bus width to 12 bits with [0:11] ordering. */ + ov490_write_reg(dev, OV490_DVP_CTRL3, 0x10); + + dev_info(dev->dev, "Identified RDACM21 camera module\n"); + + return 0; +} + +static int rdacm21_initialize(struct rdacm21_device *dev) +{ + int ret; + + /* Verify communication with the MAX9271: ping to wakeup. */ + dev->serializer.client->addr = MAX9271_DEFAULT_ADDR; + i2c_smbus_read_byte(dev->serializer.client); + usleep_range(3000, 5000); + + /* Enable reverse channel and disable the serial link. */ + ret = max9271_set_serial_link(&dev->serializer, false); + if (ret) + return ret; + + /* Configure I2C bus at 105Kbps speed and configure GMSL. */ + ret = max9271_configure_i2c(&dev->serializer, + MAX9271_I2CSLVSH_469NS_234NS | + MAX9271_I2CSLVTO_1024US | + MAX9271_I2CMSTBT_105KBPS); + if (ret) + return ret; + + ret = max9271_verify_id(&dev->serializer); + if (ret) + return ret; + + /* Enable GPIO1 and hold OV490 in reset during max9271 configuration. */ + ret = max9271_enable_gpios(&dev->serializer, MAX9271_GPIO1OUT); + if (ret) + return ret; + + ret = max9271_clear_gpios(&dev->serializer, MAX9271_GPIO1OUT); + if (ret) + return ret; + + ret = max9271_configure_gmsl_link(&dev->serializer); + if (ret) + return ret; + + ret = max9271_set_address(&dev->serializer, dev->addrs[0]); + if (ret) + return ret; + dev->serializer.client->addr = dev->addrs[0]; + + ret = max9271_set_translation(&dev->serializer, dev->addrs[1], + OV490_I2C_ADDRESS); + if (ret) + return ret; + dev->isp->addr = dev->addrs[1]; + + /* Release OV490 from reset and initialize it. */ + ret = max9271_set_gpios(&dev->serializer, MAX9271_GPIO1OUT); + if (ret) + return ret; + usleep_range(3000, 5000); + + ret = ov490_initialize(dev); + if (ret) + return ret; + + /* + * Set reverse channel high threshold to increase noise immunity. + * + * This should be compensated by increasing the reverse channel + * amplitude on the remote deserializer side. + */ + return max9271_set_high_threshold(&dev->serializer, true); +} + +static int rdacm21_probe(struct i2c_client *client) +{ + struct rdacm21_device *dev; + struct fwnode_handle *ep; + int ret; + + dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + dev->dev = &client->dev; + dev->serializer.client = client; + + ret = of_property_read_u32_array(client->dev.of_node, "reg", + dev->addrs, 2); + if (ret < 0) { + dev_err(dev->dev, "Invalid DT reg property: %d\n", ret); + return -EINVAL; + } + + /* Create the dummy I2C client for the sensor. */ + dev->isp = i2c_new_dummy_device(client->adapter, OV490_I2C_ADDRESS); + if (IS_ERR(dev->isp)) + return PTR_ERR(dev->isp); + + ret = rdacm21_initialize(dev); + if (ret < 0) + goto error; + + /* Initialize and register the subdevice. */ + v4l2_i2c_subdev_init(&dev->sd, client, &rdacm21_subdev_ops); + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + v4l2_ctrl_handler_init(&dev->ctrls, 1); + v4l2_ctrl_new_std(&dev->ctrls, NULL, V4L2_CID_PIXEL_RATE, + OV10640_PIXEL_RATE, OV10640_PIXEL_RATE, 1, + OV10640_PIXEL_RATE); + dev->sd.ctrl_handler = &dev->ctrls; + + ret = dev->ctrls.error; + if (ret) + goto error_free_ctrls; + + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR; + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret < 0) + goto error_free_ctrls; + + ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL); + if (!ep) { + dev_err(&client->dev, + "Unable to get endpoint in node %pOF\n", + client->dev.of_node); + ret = -ENOENT; + goto error_free_ctrls; + } + dev->sd.fwnode = ep; + + ret = v4l2_async_register_subdev(&dev->sd); + if (ret) + goto error_put_node; + + return 0; + +error_put_node: + fwnode_handle_put(dev->sd.fwnode); +error_free_ctrls: + v4l2_ctrl_handler_free(&dev->ctrls); +error: + i2c_unregister_device(dev->isp); + + return ret; +} + +static int rdacm21_remove(struct i2c_client *client) +{ + struct rdacm21_device *dev = sd_to_rdacm21(i2c_get_clientdata(client)); + + v4l2_async_unregister_subdev(&dev->sd); + v4l2_ctrl_handler_free(&dev->ctrls); + i2c_unregister_device(dev->isp); + fwnode_handle_put(dev->sd.fwnode); + + return 0; +} + +static const struct of_device_id rdacm21_of_ids[] = { + { .compatible = "imi,rdacm21" }, + { } +}; +MODULE_DEVICE_TABLE(of, rdacm21_of_ids); + +static struct i2c_driver rdacm21_i2c_driver = { + .driver = { + .name = "rdacm21", + .of_match_table = rdacm21_of_ids, + }, + .probe_new = rdacm21_probe, + .remove = rdacm21_remove, +}; + +module_i2c_driver(rdacm21_i2c_driver); + +MODULE_DESCRIPTION("GMSL Camera driver for RDACM21"); +MODULE_AUTHOR("Jacopo Mondi"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c index 003ba22334cd..7f07ef56fbbd 100644 --- a/drivers/media/i2c/st-mipid02.c +++ b/drivers/media/i2c/st-mipid02.c @@ -92,7 +92,6 @@ struct mipid02_dev { u64 link_frequency; struct v4l2_fwnode_endpoint tx; /* remote source */ - struct v4l2_async_subdev asd; struct v4l2_async_notifier notifier; struct v4l2_subdev *s_subdev; /* registers */ @@ -844,6 +843,7 @@ static int mipid02_parse_rx_ep(struct mipid02_dev *bridge) { struct v4l2_fwnode_endpoint ep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; struct i2c_client *client = bridge->i2c_client; + struct v4l2_async_subdev *asd; struct device_node *ep_node; int ret; @@ -875,18 +875,17 @@ static int mipid02_parse_rx_ep(struct mipid02_dev *bridge) bridge->rx = ep; /* register async notifier so we get noticed when sensor is connected */ - bridge->asd.match.fwnode = - fwnode_graph_get_remote_port_parent(of_fwnode_handle(ep_node)); - bridge->asd.match_type = V4L2_ASYNC_MATCH_FWNODE; + v4l2_async_notifier_init(&bridge->notifier); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &bridge->notifier, + of_fwnode_handle(ep_node), + struct v4l2_async_subdev); of_node_put(ep_node); - v4l2_async_notifier_init(&bridge->notifier); - ret = v4l2_async_notifier_add_subdev(&bridge->notifier, &bridge->asd); - if (ret) { - dev_err(&client->dev, "fail to register asd to notifier %d", - ret); - fwnode_handle_put(bridge->asd.match.fwnode); - return ret; + if (IS_ERR(asd)) { + dev_err(&client->dev, "fail to register asd to notifier %ld", + PTR_ERR(asd)); + return PTR_ERR(asd); } bridge->notifier.ops = &mipid02_notifier_ops; diff --git a/drivers/media/pci/cx25821/cx25821-core.c b/drivers/media/pci/cx25821/cx25821-core.c index 6f8ffab8840f..07b6d0c49bbf 100644 --- a/drivers/media/pci/cx25821/cx25821-core.c +++ b/drivers/media/pci/cx25821/cx25821-core.c @@ -976,8 +976,10 @@ int cx25821_riscmem_alloc(struct pci_dev *pci, __le32 *cpu; dma_addr_t dma = 0; - if (NULL != risc->cpu && risc->size < size) + if (risc->cpu && risc->size < size) { pci_free_consistent(pci, risc->size, risc->cpu, risc->dma); + risc->cpu = NULL; + } if (NULL == risc->cpu) { cpu = pci_zalloc_consistent(pci, size, &dma); if (NULL == cpu) diff --git a/drivers/media/pci/intel/ipu3/Kconfig b/drivers/media/pci/intel/ipu3/Kconfig index 82d7f17e6a02..dce8274c81e6 100644 --- a/drivers/media/pci/intel/ipu3/Kconfig +++ b/drivers/media/pci/intel/ipu3/Kconfig @@ -2,7 +2,8 @@ config VIDEO_IPU3_CIO2 tristate "Intel ipu3-cio2 driver" depends on VIDEO_V4L2 && PCI - depends on (X86 && ACPI) || COMPILE_TEST + depends on ACPI || COMPILE_TEST + depends on X86 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select V4L2_FWNODE @@ -16,3 +17,21 @@ config VIDEO_IPU3_CIO2 Say Y or M here if you have a Skylake/Kaby Lake SoC with MIPI CSI-2 connected camera. The module will be called ipu3-cio2. + +config CIO2_BRIDGE + bool "IPU3 CIO2 Sensors Bridge" + depends on VIDEO_IPU3_CIO2 && ACPI + help + This extension provides an API for the ipu3-cio2 driver to create + connections to cameras that are hidden in the SSDB buffer in ACPI. + It can be used to enable support for cameras in detachable / hybrid + devices that ship with Windows. + + Say Y here if your device is a detachable / hybrid laptop that comes + with Windows installed by the OEM, for example: + + - Microsoft Surface models (except Surface Pro 3) + - The Lenovo Miix line (for example the 510, 520, 710 and 720) + - Dell 7285 + + If in doubt, say N here. diff --git a/drivers/media/pci/intel/ipu3/Makefile b/drivers/media/pci/intel/ipu3/Makefile index 98ddd5beafe0..933777e6ea8a 100644 --- a/drivers/media/pci/intel/ipu3/Makefile +++ b/drivers/media/pci/intel/ipu3/Makefile @@ -1,2 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_VIDEO_IPU3_CIO2) += ipu3-cio2.o + +ipu3-cio2-y += ipu3-cio2-main.o +ipu3-cio2-$(CONFIG_CIO2_BRIDGE) += cio2-bridge.o diff --git a/drivers/media/pci/intel/ipu3/cio2-bridge.c b/drivers/media/pci/intel/ipu3/cio2-bridge.c new file mode 100644 index 000000000000..c2199042d3db --- /dev/null +++ b/drivers/media/pci/intel/ipu3/cio2-bridge.c @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Author: Dan Scally <djrscally@gmail.com> */ + +#include <linux/acpi.h> +#include <linux/device.h> +#include <linux/pci.h> +#include <linux/property.h> +#include <media/v4l2-fwnode.h> + +#include "cio2-bridge.h" + +/* + * Extend this array with ACPI Hardware IDs of devices known to be working + * plus the number of link-frequencies expected by their drivers, along with + * the frequency values in hertz. This is somewhat opportunistic way of adding + * support for this for now in the hopes of a better source for the information + * (possibly some encoded value in the SSDB buffer that we're unaware of) + * becoming apparent in the future. + * + * Do not add an entry for a sensor that is not actually supported. + */ +static const struct cio2_sensor_config cio2_supported_sensors[] = { + /* Omnivision OV5693 */ + CIO2_SENSOR_CONFIG("INT33BE", 0), + /* Omnivision OV2680 */ + CIO2_SENSOR_CONFIG("OVTI2680", 0), +}; + +static const struct cio2_property_names prop_names = { + .clock_frequency = "clock-frequency", + .rotation = "rotation", + .bus_type = "bus-type", + .data_lanes = "data-lanes", + .remote_endpoint = "remote-endpoint", + .link_frequencies = "link-frequencies", +}; + +static int cio2_bridge_read_acpi_buffer(struct acpi_device *adev, char *id, + void *data, u32 size) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object *obj; + acpi_status status; + int ret = 0; + + status = acpi_evaluate_object(adev->handle, id, NULL, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj = buffer.pointer; + if (!obj) { + dev_err(&adev->dev, "Couldn't locate ACPI buffer\n"); + return -ENODEV; + } + + if (obj->type != ACPI_TYPE_BUFFER) { + dev_err(&adev->dev, "Not an ACPI buffer\n"); + ret = -ENODEV; + goto out_free_buff; + } + + if (obj->buffer.length > size) { + dev_err(&adev->dev, "Given buffer is too small\n"); + ret = -EINVAL; + goto out_free_buff; + } + + memcpy(data, obj->buffer.pointer, obj->buffer.length); + +out_free_buff: + kfree(buffer.pointer); + return ret; +} + +static void cio2_bridge_create_fwnode_properties( + struct cio2_sensor *sensor, + struct cio2_bridge *bridge, + const struct cio2_sensor_config *cfg) +{ + sensor->prop_names = prop_names; + + sensor->local_ref[0].node = &sensor->swnodes[SWNODE_CIO2_ENDPOINT]; + sensor->remote_ref[0].node = &sensor->swnodes[SWNODE_SENSOR_ENDPOINT]; + + sensor->dev_properties[0] = PROPERTY_ENTRY_U32( + sensor->prop_names.clock_frequency, + sensor->ssdb.mclkspeed); + sensor->dev_properties[1] = PROPERTY_ENTRY_U8( + sensor->prop_names.rotation, + sensor->ssdb.degree); + + sensor->ep_properties[0] = PROPERTY_ENTRY_U32( + sensor->prop_names.bus_type, + V4L2_FWNODE_BUS_TYPE_CSI2_DPHY); + sensor->ep_properties[1] = PROPERTY_ENTRY_U32_ARRAY_LEN( + sensor->prop_names.data_lanes, + bridge->data_lanes, + sensor->ssdb.lanes); + sensor->ep_properties[2] = PROPERTY_ENTRY_REF_ARRAY( + sensor->prop_names.remote_endpoint, + sensor->local_ref); + + if (cfg->nr_link_freqs > 0) + sensor->ep_properties[3] = PROPERTY_ENTRY_U64_ARRAY_LEN( + sensor->prop_names.link_frequencies, + cfg->link_freqs, + cfg->nr_link_freqs); + + sensor->cio2_properties[0] = PROPERTY_ENTRY_U32_ARRAY_LEN( + sensor->prop_names.data_lanes, + bridge->data_lanes, + sensor->ssdb.lanes); + sensor->cio2_properties[1] = PROPERTY_ENTRY_REF_ARRAY( + sensor->prop_names.remote_endpoint, + sensor->remote_ref); +} + +static void cio2_bridge_init_swnode_names(struct cio2_sensor *sensor) +{ + snprintf(sensor->node_names.remote_port, + sizeof(sensor->node_names.remote_port), + SWNODE_GRAPH_PORT_NAME_FMT, sensor->ssdb.link); + snprintf(sensor->node_names.port, + sizeof(sensor->node_names.port), + SWNODE_GRAPH_PORT_NAME_FMT, 0); /* Always port 0 */ + snprintf(sensor->node_names.endpoint, + sizeof(sensor->node_names.endpoint), + SWNODE_GRAPH_ENDPOINT_NAME_FMT, 0); /* And endpoint 0 */ +} + +static void cio2_bridge_create_connection_swnodes(struct cio2_bridge *bridge, + struct cio2_sensor *sensor) +{ + struct software_node *nodes = sensor->swnodes; + + cio2_bridge_init_swnode_names(sensor); + + nodes[SWNODE_SENSOR_HID] = NODE_SENSOR(sensor->name, + sensor->dev_properties); + nodes[SWNODE_SENSOR_PORT] = NODE_PORT(sensor->node_names.port, + &nodes[SWNODE_SENSOR_HID]); + nodes[SWNODE_SENSOR_ENDPOINT] = NODE_ENDPOINT( + sensor->node_names.endpoint, + &nodes[SWNODE_SENSOR_PORT], + sensor->ep_properties); + nodes[SWNODE_CIO2_PORT] = NODE_PORT(sensor->node_names.remote_port, + &bridge->cio2_hid_node); + nodes[SWNODE_CIO2_ENDPOINT] = NODE_ENDPOINT( + sensor->node_names.endpoint, + &nodes[SWNODE_CIO2_PORT], + sensor->cio2_properties); +} + +static void cio2_bridge_unregister_sensors(struct cio2_bridge *bridge) +{ + struct cio2_sensor *sensor; + unsigned int i; + + for (i = 0; i < bridge->n_sensors; i++) { + sensor = &bridge->sensors[i]; + software_node_unregister_nodes(sensor->swnodes); + acpi_dev_put(sensor->adev); + } +} + +static int cio2_bridge_connect_sensor(const struct cio2_sensor_config *cfg, + struct cio2_bridge *bridge, + struct pci_dev *cio2) +{ + struct fwnode_handle *fwnode; + struct cio2_sensor *sensor; + struct acpi_device *adev; + int ret; + + for_each_acpi_dev_match(adev, cfg->hid, NULL, -1) { + if (!adev->status.enabled) + continue; + + if (bridge->n_sensors >= CIO2_NUM_PORTS) { + dev_err(&cio2->dev, "Exceeded available CIO2 ports\n"); + cio2_bridge_unregister_sensors(bridge); + ret = -EINVAL; + goto err_out; + } + + sensor = &bridge->sensors[bridge->n_sensors]; + sensor->adev = adev; + strscpy(sensor->name, cfg->hid, sizeof(sensor->name)); + + ret = cio2_bridge_read_acpi_buffer(adev, "SSDB", + &sensor->ssdb, + sizeof(sensor->ssdb)); + if (ret) + goto err_put_adev; + + if (sensor->ssdb.lanes > CIO2_MAX_LANES) { + dev_err(&adev->dev, + "Number of lanes in SSDB is invalid\n"); + ret = -EINVAL; + goto err_put_adev; + } + + cio2_bridge_create_fwnode_properties(sensor, bridge, cfg); + cio2_bridge_create_connection_swnodes(bridge, sensor); + + ret = software_node_register_nodes(sensor->swnodes); + if (ret) + goto err_put_adev; + + fwnode = software_node_fwnode(&sensor->swnodes[ + SWNODE_SENSOR_HID]); + if (!fwnode) { + ret = -ENODEV; + goto err_free_swnodes; + } + + adev->fwnode.secondary = fwnode; + + dev_info(&cio2->dev, "Found supported sensor %s\n", + acpi_dev_name(adev)); + + bridge->n_sensors++; + } + + return 0; + +err_free_swnodes: + software_node_unregister_nodes(sensor->swnodes); +err_put_adev: + acpi_dev_put(sensor->adev); +err_out: + return ret; +} + +static int cio2_bridge_connect_sensors(struct cio2_bridge *bridge, + struct pci_dev *cio2) +{ + unsigned int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(cio2_supported_sensors); i++) { + const struct cio2_sensor_config *cfg = + &cio2_supported_sensors[i]; + + ret = cio2_bridge_connect_sensor(cfg, bridge, cio2); + if (ret) + goto err_unregister_sensors; + } + + return 0; + +err_unregister_sensors: + cio2_bridge_unregister_sensors(bridge); + return ret; +} + +int cio2_bridge_init(struct pci_dev *cio2) +{ + struct device *dev = &cio2->dev; + struct fwnode_handle *fwnode; + struct cio2_bridge *bridge; + unsigned int i; + int ret; + + bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); + if (!bridge) + return -ENOMEM; + + strscpy(bridge->cio2_node_name, CIO2_HID, + sizeof(bridge->cio2_node_name)); + bridge->cio2_hid_node.name = bridge->cio2_node_name; + + ret = software_node_register(&bridge->cio2_hid_node); + if (ret < 0) { + dev_err(dev, "Failed to register the CIO2 HID node\n"); + goto err_free_bridge; + } + + /* + * Map the lane arrangement, which is fixed for the IPU3 (meaning we + * only need one, rather than one per sensor). We include it as a + * member of the struct cio2_bridge rather than a global variable so + * that it survives if the module is unloaded along with the rest of + * the struct. + */ + for (i = 0; i < CIO2_MAX_LANES; i++) + bridge->data_lanes[i] = i + 1; + + ret = cio2_bridge_connect_sensors(bridge, cio2); + if (ret || bridge->n_sensors == 0) + goto err_unregister_cio2; + + dev_info(dev, "Connected %d cameras\n", bridge->n_sensors); + + fwnode = software_node_fwnode(&bridge->cio2_hid_node); + if (!fwnode) { + dev_err(dev, "Error getting fwnode from cio2 software_node\n"); + ret = -ENODEV; + goto err_unregister_sensors; + } + + set_secondary_fwnode(dev, fwnode); + + return 0; + +err_unregister_sensors: + cio2_bridge_unregister_sensors(bridge); +err_unregister_cio2: + software_node_unregister(&bridge->cio2_hid_node); +err_free_bridge: + kfree(bridge); + + return ret; +} diff --git a/drivers/media/pci/intel/ipu3/cio2-bridge.h b/drivers/media/pci/intel/ipu3/cio2-bridge.h new file mode 100644 index 000000000000..dd0ffcafa489 --- /dev/null +++ b/drivers/media/pci/intel/ipu3/cio2-bridge.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Author: Dan Scally <djrscally@gmail.com> */ +#ifndef __CIO2_BRIDGE_H +#define __CIO2_BRIDGE_H + +#include <linux/property.h> +#include <linux/types.h> + +#include "ipu3-cio2.h" + +#define CIO2_HID "INT343E" +#define CIO2_MAX_LANES 4 +#define MAX_NUM_LINK_FREQS 3 + +#define CIO2_SENSOR_CONFIG(_HID, _NR, ...) \ + (const struct cio2_sensor_config) { \ + .hid = _HID, \ + .nr_link_freqs = _NR, \ + .link_freqs = { __VA_ARGS__ } \ + } + +#define NODE_SENSOR(_HID, _PROPS) \ + (const struct software_node) { \ + .name = _HID, \ + .properties = _PROPS, \ + } + +#define NODE_PORT(_PORT, _SENSOR_NODE) \ + (const struct software_node) { \ + .name = _PORT, \ + .parent = _SENSOR_NODE, \ + } + +#define NODE_ENDPOINT(_EP, _PORT, _PROPS) \ + (const struct software_node) { \ + .name = _EP, \ + .parent = _PORT, \ + .properties = _PROPS, \ + } + +enum cio2_sensor_swnodes { + SWNODE_SENSOR_HID, + SWNODE_SENSOR_PORT, + SWNODE_SENSOR_ENDPOINT, + SWNODE_CIO2_PORT, + SWNODE_CIO2_ENDPOINT, + SWNODE_COUNT +}; + +/* Data representation as it is in ACPI SSDB buffer */ +struct cio2_sensor_ssdb { + u8 version; + u8 sku; + u8 guid_csi2[16]; + u8 devfunction; + u8 bus; + u32 dphylinkenfuses; + u32 clockdiv; + u8 link; + u8 lanes; + u32 csiparams[10]; + u32 maxlanespeed; + u8 sensorcalibfileidx; + u8 sensorcalibfileidxInMBZ[3]; + u8 romtype; + u8 vcmtype; + u8 platforminfo; + u8 platformsubinfo; + u8 flash; + u8 privacyled; + u8 degree; + u8 mipilinkdefined; + u32 mclkspeed; + u8 controllogicid; + u8 reserved1[3]; + u8 mclkport; + u8 reserved2[13]; +} __packed; + +struct cio2_property_names { + char clock_frequency[16]; + char rotation[9]; + char bus_type[9]; + char data_lanes[11]; + char remote_endpoint[16]; + char link_frequencies[17]; +}; + +struct cio2_node_names { + char port[7]; + char endpoint[11]; + char remote_port[7]; +}; + +struct cio2_sensor_config { + const char *hid; + const u8 nr_link_freqs; + const u64 link_freqs[MAX_NUM_LINK_FREQS]; +}; + +struct cio2_sensor { + char name[ACPI_ID_LEN]; + struct acpi_device *adev; + + struct software_node swnodes[6]; + struct cio2_node_names node_names; + + struct cio2_sensor_ssdb ssdb; + struct cio2_property_names prop_names; + struct property_entry ep_properties[5]; + struct property_entry dev_properties[3]; + struct property_entry cio2_properties[3]; + struct software_node_ref_args local_ref[1]; + struct software_node_ref_args remote_ref[1]; +}; + +struct cio2_bridge { + char cio2_node_name[ACPI_ID_LEN]; + struct software_node cio2_hid_node; + u32 data_lanes[4]; + unsigned int n_sensors; + struct cio2_sensor sensors[CIO2_NUM_PORTS]; +}; + +#endif diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2-main.c index 6cada8a6e50c..6e8c0c230e11 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.c +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2-main.c @@ -1094,12 +1094,9 @@ static int cio2_v4l2_try_fmt(struct file *file, void *fh, struct v4l2_format *f) mpix->pixelformat = fmt->fourcc; mpix->colorspace = V4L2_COLORSPACE_RAW; mpix->field = V4L2_FIELD_NONE; - memset(mpix->reserved, 0, sizeof(mpix->reserved)); mpix->plane_fmt[0].bytesperline = cio2_bytesperline(mpix->width); mpix->plane_fmt[0].sizeimage = mpix->plane_fmt[0].bytesperline * mpix->height; - memset(mpix->plane_fmt[0].reserved, 0, - sizeof(mpix->plane_fmt[0].reserved)); /* use default */ mpix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; @@ -1269,7 +1266,7 @@ static int cio2_subdev_set_fmt(struct v4l2_subdev *sd, fmt->format.code = formats[0].mbus_code; for (i = 0; i < ARRAY_SIZE(formats); i++) { - if (formats[i].mbus_code == fmt->format.code) { + if (formats[i].mbus_code == mbus_code) { fmt->format.code = mbus_code; break; } @@ -1467,7 +1464,7 @@ static int cio2_parse_firmware(struct cio2_device *cio2) struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; - struct sensor_async_subdev *s_asd = NULL; + struct sensor_async_subdev *s_asd; struct fwnode_handle *ep; ep = fwnode_graph_get_endpoint_by_id( @@ -1481,27 +1478,22 @@ static int cio2_parse_firmware(struct cio2_device *cio2) if (ret) goto err_parse; - s_asd = kzalloc(sizeof(*s_asd), GFP_KERNEL); - if (!s_asd) { - ret = -ENOMEM; + s_asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &cio2->notifier, ep, struct sensor_async_subdev); + if (IS_ERR(s_asd)) { + ret = PTR_ERR(s_asd); goto err_parse; } s_asd->csi2.port = vep.base.port; s_asd->csi2.lanes = vep.bus.mipi_csi2.num_data_lanes; - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &cio2->notifier, ep, &s_asd->asd); - if (ret) - goto err_parse; - fwnode_handle_put(ep); continue; err_parse: fwnode_handle_put(ep); - kfree(s_asd); return ret; } @@ -1702,11 +1694,28 @@ static void cio2_queues_exit(struct cio2_device *cio2) cio2_queue_exit(cio2, &cio2->queue[i]); } +static int cio2_check_fwnode_graph(struct fwnode_handle *fwnode) +{ + struct fwnode_handle *endpoint; + + if (IS_ERR_OR_NULL(fwnode)) + return -EINVAL; + + endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); + if (endpoint) { + fwnode_handle_put(endpoint); + return 0; + } + + return cio2_check_fwnode_graph(fwnode->secondary); +} + /**************** PCI interface ****************/ static int cio2_pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) { + struct fwnode_handle *fwnode = dev_fwnode(&pci_dev->dev); struct cio2_device *cio2; int r; @@ -1715,6 +1724,23 @@ static int cio2_pci_probe(struct pci_dev *pci_dev, return -ENOMEM; cio2->pci_dev = pci_dev; + /* + * On some platforms no connections to sensors are defined in firmware, + * if the device has no endpoints then we can try to build those as + * software_nodes parsed from SSDB. + */ + r = cio2_check_fwnode_graph(fwnode); + if (r) { + if (fwnode && !IS_ERR_OR_NULL(fwnode->secondary)) { + dev_err(&pci_dev->dev, "fwnode graph has no endpoints connected\n"); + return -EINVAL; + } + + r = cio2_bridge_init(pci_dev); + if (r) + return r; + } + r = pcim_enable_device(pci_dev); if (r) { dev_err(&pci_dev->dev, "failed to enable device (%d)\n", r); diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.h b/drivers/media/pci/intel/ipu3/ipu3-cio2.h index ccf0b85ae36f..3806d7f04d69 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.h +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.h @@ -4,8 +4,26 @@ #ifndef __IPU3_CIO2_H #define __IPU3_CIO2_H +#include <linux/bits.h> +#include <linux/dma-mapping.h> +#include <linux/kernel.h> +#include <linux/mutex.h> #include <linux/types.h> +#include <asm/page.h> + +#include <media/media-device.h> +#include <media/media-entity.h> +#include <media/v4l2-async.h> +#include <media/v4l2-dev.h> +#include <media/v4l2-device.h> +#include <media/v4l2-subdev.h> +#include <media/videobuf2-core.h> +#include <media/videobuf2-v4l2.h> + +struct cio2_fbpt_entry; /* defined here, after the first usage */ +struct pci_dev; + #define CIO2_NAME "ipu3-cio2" #define CIO2_DEVICE_NAME "Intel IPU3 CIO2" #define CIO2_ENTITY_NAME "ipu3-csi2" @@ -437,4 +455,10 @@ static inline struct cio2_queue *vb2q_to_cio2_queue(struct vb2_queue *vq) return container_of(vq, struct cio2_queue, vbq); } +#if IS_ENABLED(CONFIG_CIO2_BRIDGE) +int cio2_bridge_init(struct pci_dev *cio2); +#else +static inline int cio2_bridge_init(struct pci_dev *cio2) { return 0; } +#endif + #endif diff --git a/drivers/media/pci/ivtv/ivtv-driver.c b/drivers/media/pci/ivtv/ivtv-driver.c index 28acb14490d5..6e448cb3b51c 100644 --- a/drivers/media/pci/ivtv/ivtv-driver.c +++ b/drivers/media/pci/ivtv/ivtv-driver.c @@ -873,6 +873,11 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, pci_read_config_word(pdev, PCI_COMMAND, &cmd); if (!(cmd & PCI_COMMAND_MASTER)) { IVTV_ERR("Bus Mastering is not enabled\n"); + if (itv->has_cx23415) + release_mem_region(itv->base_addr + IVTV_DECODER_OFFSET, + IVTV_DECODER_SIZE); + release_mem_region(itv->base_addr, IVTV_ENCODER_SIZE); + release_mem_region(itv->base_addr + IVTV_REG_OFFSET, IVTV_REG_SIZE); return -ENXIO; } } diff --git a/drivers/media/pci/saa7134/saa7134-empress.c b/drivers/media/pci/saa7134/saa7134-empress.c index 39e3c7f8c5b4..76a37fbd8458 100644 --- a/drivers/media/pci/saa7134/saa7134-empress.c +++ b/drivers/media/pci/saa7134/saa7134-empress.c @@ -282,8 +282,11 @@ static int empress_init(struct saa7134_dev *dev) q->lock = &dev->lock; q->dev = &dev->pci->dev; err = vb2_queue_init(q); - if (err) + if (err) { + video_device_release(dev->empress_dev); + dev->empress_dev = NULL; return err; + } dev->empress_dev->queue = q; dev->empress_dev->device_caps = V4L2_CAP_READWRITE | V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE; diff --git a/drivers/media/pci/saa7134/saa7134-tvaudio.c b/drivers/media/pci/saa7134/saa7134-tvaudio.c index 5cc4ef21f9d3..aa0895d2d735 100644 --- a/drivers/media/pci/saa7134/saa7134-tvaudio.c +++ b/drivers/media/pci/saa7134/saa7134-tvaudio.c @@ -871,23 +871,24 @@ void saa7134_enable_i2s(struct saa7134_dev *dev) switch (dev->pci->device) { case PCI_DEVICE_ID_PHILIPS_SAA7133: case PCI_DEVICE_ID_PHILIPS_SAA7135: - /* Set I2S format (SONY)  */ - saa_writeb(SAA7133_I2S_AUDIO_CONTROL, 0x00); - /* Start I2S */ - saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x11); - break; + /* Set I2S format (SONY)  */ + saa_writeb(SAA7133_I2S_AUDIO_CONTROL, 0x00); + /* Start I2S */ + saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x11); + break; case PCI_DEVICE_ID_PHILIPS_SAA7134: - i2s_format = (dev->input->amux == TV) ? 0x00 : 0x01; + i2s_format = (dev->input->amux == TV) ? 0x00 : 0x01; - /* enable I2S audio output for the mpeg encoder */ - saa_writeb(SAA7134_I2S_OUTPUT_SELECT, 0x80); - saa_writeb(SAA7134_I2S_OUTPUT_FORMAT, i2s_format); - saa_writeb(SAA7134_I2S_OUTPUT_LEVEL, 0x0F); - saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x01); + /* enable I2S audio output for the mpeg encoder */ + saa_writeb(SAA7134_I2S_OUTPUT_SELECT, 0x80); + saa_writeb(SAA7134_I2S_OUTPUT_FORMAT, i2s_format); + saa_writeb(SAA7134_I2S_OUTPUT_LEVEL, 0x0F); + saa_writeb(SAA7134_I2S_AUDIO_OUTPUT, 0x01); + break; default: - break; + break; } } diff --git a/drivers/media/pci/saa7164/saa7164-buffer.c b/drivers/media/pci/saa7164/saa7164-buffer.c index 245d9db280aa..89c5b79a5b24 100644 --- a/drivers/media/pci/saa7164/saa7164-buffer.c +++ b/drivers/media/pci/saa7164/saa7164-buffer.c @@ -103,13 +103,13 @@ struct saa7164_buffer *saa7164_buffer_alloc(struct saa7164_port *port, buf->pt_size = (SAA7164_PT_ENTRIES * sizeof(u64)) + 0x1000; /* Allocate contiguous memory */ - buf->cpu = pci_alloc_consistent(port->dev->pci, buf->pci_size, - &buf->dma); + buf->cpu = dma_alloc_coherent(&port->dev->pci->dev, buf->pci_size, + &buf->dma, GFP_KERNEL); if (!buf->cpu) goto fail1; - buf->pt_cpu = pci_alloc_consistent(port->dev->pci, buf->pt_size, - &buf->pt_dma); + buf->pt_cpu = dma_alloc_coherent(&port->dev->pci->dev, buf->pt_size, + &buf->pt_dma, GFP_KERNEL); if (!buf->pt_cpu) goto fail2; @@ -137,7 +137,8 @@ struct saa7164_buffer *saa7164_buffer_alloc(struct saa7164_port *port, goto ret; fail2: - pci_free_consistent(port->dev->pci, buf->pci_size, buf->cpu, buf->dma); + dma_free_coherent(&port->dev->pci->dev, buf->pci_size, buf->cpu, + buf->dma); fail1: kfree(buf); @@ -160,8 +161,9 @@ int saa7164_buffer_dealloc(struct saa7164_buffer *buf) if (buf->flags != SAA7164_BUFFER_FREE) log_warn(" freeing a non-free buffer\n"); - pci_free_consistent(dev->pci, buf->pci_size, buf->cpu, buf->dma); - pci_free_consistent(dev->pci, buf->pt_size, buf->pt_cpu, buf->pt_dma); + dma_free_coherent(&dev->pci->dev, buf->pci_size, buf->cpu, buf->dma); + dma_free_coherent(&dev->pci->dev, buf->pt_size, buf->pt_cpu, + buf->pt_dma); kfree(buf); diff --git a/drivers/media/pci/saa7164/saa7164-core.c b/drivers/media/pci/saa7164/saa7164-core.c index f3a4e575a782..7973ae42873a 100644 --- a/drivers/media/pci/saa7164/saa7164-core.c +++ b/drivers/media/pci/saa7164/saa7164-core.c @@ -1273,7 +1273,7 @@ static int saa7164_initdev(struct pci_dev *pci_dev, pci_set_master(pci_dev); /* TODO */ - err = pci_set_dma_mask(pci_dev, 0xffffffff); + err = dma_set_mask(&pci_dev->dev, 0xffffffff); if (err) { printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); goto fail_irq; diff --git a/drivers/media/pci/saa7164/saa7164.h b/drivers/media/pci/saa7164/saa7164.h index 2801a2b03fa0..4b4eb156e214 100644 --- a/drivers/media/pci/saa7164/saa7164.h +++ b/drivers/media/pci/saa7164/saa7164.h @@ -24,7 +24,7 @@ saa7164_bus..() : Manage a read/write memory ring buffer in the | : PCIe Address space. | - | saa7164_fw...() : Load any frimware + | saa7164_fw...() : Load any firmware | | : direct into the device V V <- ----------------- PCIe address space -------------------- -> diff --git a/drivers/media/pci/smipcie/smipcie-ir.c b/drivers/media/pci/smipcie/smipcie-ir.c index e6b74e161a05..c0604d9c7011 100644 --- a/drivers/media/pci/smipcie/smipcie-ir.c +++ b/drivers/media/pci/smipcie/smipcie-ir.c @@ -60,38 +60,44 @@ static void smi_ir_decode(struct smi_rc *ir) { struct smi_dev *dev = ir->dev; struct rc_dev *rc_dev = ir->rc_dev; - u32 dwIRControl, dwIRData; - u8 index, ucIRCount, readLoop; + u32 control, data; + u8 index, ir_count, read_loop; - dwIRControl = smi_read(IR_Init_Reg); + control = smi_read(IR_Init_Reg); - if (dwIRControl & rbIRVld) { - ucIRCount = (u8) smi_read(IR_Data_Cnt); + dev_dbg(&rc_dev->dev, "ircontrol: 0x%08x\n", control); - readLoop = ucIRCount/4; - if (ucIRCount % 4) - readLoop += 1; - for (index = 0; index < readLoop; index++) { - dwIRData = smi_read(IR_DATA_BUFFER_BASE + (index * 4)); + if (control & rbIRVld) { + ir_count = (u8)smi_read(IR_Data_Cnt); - ir->irData[index*4 + 0] = (u8)(dwIRData); - ir->irData[index*4 + 1] = (u8)(dwIRData >> 8); - ir->irData[index*4 + 2] = (u8)(dwIRData >> 16); - ir->irData[index*4 + 3] = (u8)(dwIRData >> 24); + dev_dbg(&rc_dev->dev, "ircount %d\n", ir_count); + + read_loop = ir_count / 4; + if (ir_count % 4) + read_loop += 1; + for (index = 0; index < read_loop; index++) { + data = smi_read(IR_DATA_BUFFER_BASE + (index * 4)); + dev_dbg(&rc_dev->dev, "IRData 0x%08x\n", data); + + ir->irData[index * 4 + 0] = (u8)(data); + ir->irData[index * 4 + 1] = (u8)(data >> 8); + ir->irData[index * 4 + 2] = (u8)(data >> 16); + ir->irData[index * 4 + 3] = (u8)(data >> 24); } - smi_raw_process(rc_dev, ir->irData, ucIRCount); - smi_set(IR_Init_Reg, rbIRVld); + smi_raw_process(rc_dev, ir->irData, ir_count); } - if (dwIRControl & rbIRhighidle) { + if (control & rbIRhighidle) { struct ir_raw_event rawir = {}; + dev_dbg(&rc_dev->dev, "high idle\n"); + rawir.pulse = 0; rawir.duration = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN; ir_raw_event_store_with_filter(rc_dev, &rawir); - smi_set(IR_Init_Reg, rbIRhighidle); } + smi_set(IR_Init_Reg, rbIRVld); ir_raw_event_handle(rc_dev); } @@ -150,7 +156,7 @@ int smi_ir_init(struct smi_dev *dev) rc_dev->dev.parent = &dev->pci_dev->dev; rc_dev->map_name = dev->info->rc_map; - rc_dev->timeout = MS_TO_US(100); + rc_dev->timeout = SMI_SAMPLE_PERIOD * SMI_SAMPLE_IDLEMIN; rc_dev->rx_resolution = SMI_SAMPLE_PERIOD; ir->rc_dev = rc_dev; @@ -173,7 +179,7 @@ void smi_ir_exit(struct smi_dev *dev) struct smi_rc *ir = &dev->ir; struct rc_dev *rc_dev = ir->rc_dev; - smi_ir_stop(ir); rc_unregister_device(rc_dev); + smi_ir_stop(ir); ir->rc_dev = NULL; } diff --git a/drivers/media/pci/smipcie/smipcie-main.c b/drivers/media/pci/smipcie/smipcie-main.c index e7604b7ecc8d..0c300d019d9c 100644 --- a/drivers/media/pci/smipcie/smipcie-main.c +++ b/drivers/media/pci/smipcie/smipcie-main.c @@ -351,13 +351,15 @@ static void smi_dma_xfer(struct tasklet_struct *t) static void smi_port_dma_free(struct smi_port *port) { if (port->cpu_addr[0]) { - pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE, - port->cpu_addr[0], port->dma_addr[0]); + dma_free_coherent(&port->dev->pci_dev->dev, + SMI_TS_DMA_BUF_SIZE, port->cpu_addr[0], + port->dma_addr[0]); port->cpu_addr[0] = NULL; } if (port->cpu_addr[1]) { - pci_free_consistent(port->dev->pci_dev, SMI_TS_DMA_BUF_SIZE, - port->cpu_addr[1], port->dma_addr[1]); + dma_free_coherent(&port->dev->pci_dev->dev, + SMI_TS_DMA_BUF_SIZE, port->cpu_addr[1], + port->dma_addr[1]); port->cpu_addr[1] = NULL; } } @@ -398,9 +400,10 @@ static int smi_port_init(struct smi_port *port, int dmaChanUsed) } if (port->_dmaInterruptCH0) { - port->cpu_addr[0] = pci_alloc_consistent(port->dev->pci_dev, - SMI_TS_DMA_BUF_SIZE, - &port->dma_addr[0]); + port->cpu_addr[0] = dma_alloc_coherent(&port->dev->pci_dev->dev, + SMI_TS_DMA_BUF_SIZE, + &port->dma_addr[0], + GFP_KERNEL); if (!port->cpu_addr[0]) { dev_err(&port->dev->pci_dev->dev, "Port[%d] DMA CH0 memory allocation failed!\n", @@ -410,9 +413,10 @@ static int smi_port_init(struct smi_port *port, int dmaChanUsed) } if (port->_dmaInterruptCH1) { - port->cpu_addr[1] = pci_alloc_consistent(port->dev->pci_dev, - SMI_TS_DMA_BUF_SIZE, - &port->dma_addr[1]); + port->cpu_addr[1] = dma_alloc_coherent(&port->dev->pci_dev->dev, + SMI_TS_DMA_BUF_SIZE, + &port->dma_addr[1], + GFP_KERNEL); if (!port->cpu_addr[1]) { dev_err(&port->dev->pci_dev->dev, "Port[%d] DMA CH1 memory allocation failed!\n", @@ -963,7 +967,7 @@ static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id) } /* should we set to 32bit DMA? */ - ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret < 0) goto err_pci_iounmap; diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 35a18d388f3f..fd1831e97b22 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -199,6 +199,21 @@ menuconfig V4L_MEM2MEM_DRIVERS if V4L_MEM2MEM_DRIVERS +config VIDEO_ALLEGRO_DVT + tristate "Allegro DVT Video IP Core" + depends on VIDEO_DEV && VIDEO_V4L2 + depends on ARCH_ZYNQMP || COMPILE_TEST + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + help + Support for the encoder video IP core by Allegro DVT. This core is + found for example on the Xilinx ZynqMP SoC in the EV family and is + called VCU in the reference manual. + + To compile this driver as a module, choose M here: the module + will be called allegro. + config VIDEO_CODA tristate "Chips&Media Coda multi-standard codec IP" depends on VIDEO_DEV && VIDEO_V4L2 && OF && (ARCH_MXC || COMPILE_TEST) @@ -530,10 +545,9 @@ config VIDEO_QCOM_VENUS tristate "Qualcomm Venus V4L2 encoder/decoder driver" depends on VIDEO_DEV && VIDEO_V4L2 depends on (ARCH_QCOM && IOMMU_DMA) || COMPILE_TEST - depends on INTERCONNECT || !INTERCONNECT select QCOM_MDT_LOADER if ARCH_QCOM select QCOM_SCM if ARCH_QCOM - select VIDEOBUF2_DMA_SG + select VIDEOBUF2_DMA_CONTIG select V4L2_MEM2MEM_DEV help This is a V4L2 driver for Qualcomm Venus video accelerator diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 1d63aa956bcd..9d4d6370908d 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -3,6 +3,7 @@ # Makefile for the video capture/playback device drivers. # +obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro-dvt/ obj-$(CONFIG_VIDEO_ASPEED) += aspeed-video.o obj-$(CONFIG_VIDEO_CADENCE) += cadence/ obj-$(CONFIG_VIDEO_VIA_CAMERA) += via-camera.o diff --git a/drivers/media/platform/allegro-dvt/Makefile b/drivers/media/platform/allegro-dvt/Makefile new file mode 100644 index 000000000000..66108a303774 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +allegro-objs := allegro-core.o allegro-mail.o +allegro-objs += nal-rbsp.o nal-h264.o nal-hevc.o + +obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro.o diff --git a/drivers/staging/media/allegro-dvt/allegro-core.c b/drivers/media/platform/allegro-dvt/allegro-core.c index 9f718f43282b..887b492e4ad1 100644 --- a/drivers/staging/media/allegro-dvt/allegro-core.c +++ b/drivers/media/platform/allegro-dvt/allegro-core.c @@ -30,6 +30,7 @@ #include "allegro-mail.h" #include "nal-h264.h" +#include "nal-hevc.h" /* * Support up to 4k video streams. The hardware actually supports higher @@ -90,10 +91,16 @@ * because it needs to write SPS/PPS NAL units. The encoder writes the actual * frame data after the offset. */ -#define ENCODER_STREAM_OFFSET SZ_64 +#define ENCODER_STREAM_OFFSET SZ_128 #define SIZE_MACROBLOCK 16 +/* Encoding options */ +#define LOG2_MAX_FRAME_NUM 4 +#define LOG2_MAX_PIC_ORDER_CNT 10 +#define BETA_OFFSET_DIV_2 -1 +#define TC_OFFSET_DIV_2 -1 + static int debug; module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Debug level (0-2)"); @@ -167,13 +174,6 @@ static struct regmap_config allegro_sram_config = { .cache_type = REGCACHE_NONE, }; -enum allegro_state { - ALLEGRO_STATE_ENCODING, - ALLEGRO_STATE_DRAIN, - ALLEGRO_STATE_WAIT_FOR_BUFFER, - ALLEGRO_STATE_STOPPED, -}; - #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh) struct allegro_channel { @@ -196,22 +196,41 @@ struct allegro_channel { unsigned int osequence; u32 codec; - enum v4l2_mpeg_video_h264_profile profile; - enum v4l2_mpeg_video_h264_level level; unsigned int sizeimage_encoded; unsigned int csequence; bool frame_rc_enable; unsigned int bitrate; unsigned int bitrate_peak; - unsigned int cpb_size; - unsigned int gop_size; struct allegro_buffer config_blob; + unsigned int log2_max_frame_num; + bool temporal_mvp_enable; + + bool enable_loop_filter_across_tiles; + bool enable_loop_filter_across_slices; + bool enable_deblocking_filter_override; + bool enable_reordering; + bool dbf_ovr_en; + unsigned int num_ref_idx_l0; unsigned int num_ref_idx_l1; + /* Maximum range for motion estimation */ + int b_hrz_me_range; + int b_vrt_me_range; + int p_hrz_me_range; + int p_vrt_me_range; + /* Size limits of coding unit */ + int min_cu_size; + int max_cu_size; + /* Size limits of transform unit */ + int min_tu_size; + int max_tu_size; + int max_transfo_depth_intra; + int max_transfo_depth_inter; + struct v4l2_ctrl *mpeg_video_h264_profile; struct v4l2_ctrl *mpeg_video_h264_level; struct v4l2_ctrl *mpeg_video_h264_i_frame_qp; @@ -219,6 +238,16 @@ struct allegro_channel { struct v4l2_ctrl *mpeg_video_h264_min_qp; struct v4l2_ctrl *mpeg_video_h264_p_frame_qp; struct v4l2_ctrl *mpeg_video_h264_b_frame_qp; + + struct v4l2_ctrl *mpeg_video_hevc_profile; + struct v4l2_ctrl *mpeg_video_hevc_level; + struct v4l2_ctrl *mpeg_video_hevc_tier; + struct v4l2_ctrl *mpeg_video_hevc_i_frame_qp; + struct v4l2_ctrl *mpeg_video_hevc_max_qp; + struct v4l2_ctrl *mpeg_video_hevc_min_qp; + struct v4l2_ctrl *mpeg_video_hevc_p_frame_qp; + struct v4l2_ctrl *mpeg_video_hevc_b_frame_qp; + struct v4l2_ctrl *mpeg_video_frame_rc_enable; struct { /* video bitrate mode control cluster */ struct v4l2_ctrl *mpeg_video_bitrate_mode; @@ -246,21 +275,51 @@ struct allegro_channel { struct completion completion; unsigned int error; - enum allegro_state state; }; static inline int -allegro_set_state(struct allegro_channel *channel, enum allegro_state state) +allegro_channel_get_i_frame_qp(struct allegro_channel *channel) { - channel->state = state; + if (channel->codec == V4L2_PIX_FMT_HEVC) + return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_i_frame_qp); + else + return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp); +} - return 0; +static inline int +allegro_channel_get_p_frame_qp(struct allegro_channel *channel) +{ + if (channel->codec == V4L2_PIX_FMT_HEVC) + return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_p_frame_qp); + else + return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp); } -static inline enum allegro_state -allegro_get_state(struct allegro_channel *channel) +static inline int +allegro_channel_get_b_frame_qp(struct allegro_channel *channel) { - return channel->state; + if (channel->codec == V4L2_PIX_FMT_HEVC) + return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_b_frame_qp); + else + return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp); +} + +static inline int +allegro_channel_get_min_qp(struct allegro_channel *channel) +{ + if (channel->codec == V4L2_PIX_FMT_HEVC) + return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_min_qp); + else + return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp); +} + +static inline int +allegro_channel_get_max_qp(struct allegro_channel *channel) +{ + if (channel->codec == V4L2_PIX_FMT_HEVC) + return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_max_qp); + else + return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp); } struct allegro_m2m_buffer { @@ -476,7 +535,7 @@ select_minimum_h264_level(unsigned int width, unsigned int height) return level; } -static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level) +static unsigned int h264_maximum_bitrate(enum v4l2_mpeg_video_h264_level level) { switch (level) { case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: @@ -515,7 +574,7 @@ static unsigned int maximum_bitrate(enum v4l2_mpeg_video_h264_level level) } } -static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level) +static unsigned int h264_maximum_cpb_size(enum v4l2_mpeg_video_h264_level level) { switch (level) { case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: @@ -554,6 +613,86 @@ static unsigned int maximum_cpb_size(enum v4l2_mpeg_video_h264_level level) } } +static enum v4l2_mpeg_video_hevc_level +select_minimum_hevc_level(unsigned int width, unsigned int height) +{ + unsigned int luma_picture_size = width * height; + enum v4l2_mpeg_video_hevc_level level; + + if (luma_picture_size <= 36864) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_1; + else if (luma_picture_size <= 122880) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2; + else if (luma_picture_size <= 245760) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1; + else if (luma_picture_size <= 552960) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3; + else if (luma_picture_size <= 983040) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1; + else if (luma_picture_size <= 2228224) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; + else if (luma_picture_size <= 8912896) + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5; + else + level = V4L2_MPEG_VIDEO_HEVC_LEVEL_6; + + return level; +} + +static unsigned int hevc_maximum_bitrate(enum v4l2_mpeg_video_hevc_level level) +{ + /* + * See Rec. ITU-T H.265 v5 (02/2018), A.4.2 Profile-specific level + * limits for the video profiles. + */ + switch (level) { + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: + return 128; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: + return 1500; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: + return 3000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: + return 6000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: + return 10000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: + return 12000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: + return 20000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: + return 25000; + default: + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: + return 40000; + } +} + +static unsigned int hevc_maximum_cpb_size(enum v4l2_mpeg_video_hevc_level level) +{ + switch (level) { + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: + return 350; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: + return 1500; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: + return 3000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: + return 6000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: + return 10000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: + return 12000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: + return 20000; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: + return 25000; + default: + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: + return 40000; + } +} + static const struct fw_info * allegro_get_firmware_info(struct allegro_dev *dev, const struct firmware *fw, @@ -877,6 +1016,55 @@ static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level) } } +static u8 hevc_profile_to_mcu_profile(enum v4l2_mpeg_video_hevc_profile profile) +{ + switch (profile) { + default: + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: + return 1; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: + return 2; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: + return 3; + } +} + +static u16 hevc_level_to_mcu_level(enum v4l2_mpeg_video_hevc_level level) +{ + switch (level) { + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: + return 10; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: + return 20; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: + return 21; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: + return 30; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: + return 31; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: + return 40; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: + return 41; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: + return 50; + default: + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: + return 51; + } +} + +static u8 hevc_tier_to_mcu_tier(enum v4l2_mpeg_video_hevc_tier tier) +{ + switch (tier) { + default: + case V4L2_MPEG_VIDEO_HEVC_TIER_MAIN: + return 0; + case V4L2_MPEG_VIDEO_HEVC_TIER_HIGH: + return 1; + } +} + static u32 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode) { @@ -913,13 +1101,26 @@ static s16 get_qp_delta(int minuend, int subtrahend) return minuend - subtrahend; } +static u32 allegro_channel_get_entropy_mode(struct allegro_channel *channel) +{ +#define ALLEGRO_ENTROPY_MODE_CAVLC 0 +#define ALLEGRO_ENTROPY_MODE_CABAC 1 + + /* HEVC always uses CABAC, but this has to be explicitly set */ + if (channel->codec == V4L2_PIX_FMT_HEVC) + return ALLEGRO_ENTROPY_MODE_CABAC; + + return ALLEGRO_ENTROPY_MODE_CAVLC; +} + static int fill_create_channel_param(struct allegro_channel *channel, struct create_channel_param *param) { - int i_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp); - int p_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp); - int b_frame_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp); + int i_frame_qp = allegro_channel_get_i_frame_qp(channel); + int p_frame_qp = allegro_channel_get_p_frame_qp(channel); + int b_frame_qp = allegro_channel_get_b_frame_qp(channel); int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode); + unsigned int cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size); param->width = channel->width; param->height = channel->height; @@ -927,38 +1128,61 @@ static int fill_create_channel_param(struct allegro_channel *channel, param->colorspace = v4l2_colorspace_to_mcu_colorspace(channel->colorspace); param->src_mode = 0x0; - param->profile = v4l2_profile_to_mcu_profile(channel->profile); - param->constraint_set_flags = BIT(1); + param->codec = channel->codec; - param->level = v4l2_level_to_mcu_level(channel->level); - param->tier = 0; + if (channel->codec == V4L2_PIX_FMT_H264) { + enum v4l2_mpeg_video_h264_profile profile; + enum v4l2_mpeg_video_h264_level level; + + profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile); + level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level); + + param->profile = v4l2_profile_to_mcu_profile(profile); + param->constraint_set_flags = BIT(1); + param->level = v4l2_level_to_mcu_level(level); + } else { + enum v4l2_mpeg_video_hevc_profile profile; + enum v4l2_mpeg_video_hevc_level level; + enum v4l2_mpeg_video_hevc_tier tier; - param->log2_max_poc = 10; - param->log2_max_frame_num = 4; - param->temporal_mvp_enable = 1; + profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile); + level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level); + tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier); - param->dbf_ovr_en = 1; + param->profile = hevc_profile_to_mcu_profile(profile); + param->level = hevc_level_to_mcu_level(level); + param->tier = hevc_tier_to_mcu_tier(tier); + } + + param->log2_max_poc = LOG2_MAX_PIC_ORDER_CNT; + param->log2_max_frame_num = channel->log2_max_frame_num; + param->temporal_mvp_enable = channel->temporal_mvp_enable; + + param->dbf_ovr_en = channel->dbf_ovr_en; + param->override_lf = channel->enable_deblocking_filter_override; + param->enable_reordering = channel->enable_reordering; + param->entropy_mode = allegro_channel_get_entropy_mode(channel); param->rdo_cost_mode = 1; param->custom_lda = 1; param->lf = 1; - param->lf_x_tile = 1; - param->lf_x_slice = 1; + param->lf_x_tile = channel->enable_loop_filter_across_tiles; + param->lf_x_slice = channel->enable_loop_filter_across_slices; param->src_bit_depth = 8; - param->beta_offset = -1; - param->tc_offset = -1; + param->beta_offset = BETA_OFFSET_DIV_2; + param->tc_offset = TC_OFFSET_DIV_2; param->num_slices = 1; - param->me_range[0] = 8; - param->me_range[1] = 8; - param->me_range[2] = 16; - param->me_range[3] = 16; - param->max_cu_size = ilog2(SIZE_MACROBLOCK); - param->min_cu_size = ilog2(8); - param->max_tu_size = 2; - param->min_tu_size = 2; - param->max_transfo_depth_intra = 1; - param->max_transfo_depth_inter = 1; + param->me_range[0] = channel->b_hrz_me_range; + param->me_range[1] = channel->b_vrt_me_range; + param->me_range[2] = channel->p_hrz_me_range; + param->me_range[3] = channel->p_vrt_me_range; + param->max_cu_size = channel->max_cu_size; + param->min_cu_size = channel->min_cu_size; + param->max_tu_size = channel->max_tu_size; + param->min_tu_size = channel->min_tu_size; + param->max_transfo_depth_intra = channel->max_transfo_depth_intra; + param->max_transfo_depth_inter = channel->max_transfo_depth_inter; param->prefetch_auto = 0; param->prefetch_mem_offset = 0; @@ -967,8 +1191,7 @@ static int fill_create_channel_param(struct allegro_channel *channel, param->rate_control_mode = channel->frame_rc_enable ? v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0; - param->cpb_size = v4l2_cpb_size_to_mcu(channel->cpb_size, - channel->bitrate_peak); + param->cpb_size = v4l2_cpb_size_to_mcu(cpb_size, channel->bitrate_peak); /* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */ param->initial_rem_delay = param->cpb_size; param->framerate = DIV_ROUND_UP(channel->framerate.numerator, @@ -977,8 +1200,8 @@ static int fill_create_channel_param(struct allegro_channel *channel, param->target_bitrate = channel->bitrate; param->max_bitrate = channel->bitrate_peak; param->initial_qp = i_frame_qp; - param->min_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp); - param->max_qp = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp); + param->min_qp = allegro_channel_get_min_qp(channel); + param->max_qp = allegro_channel_get_max_qp(channel); param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp); param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp); param->golden_ref = 0; @@ -991,10 +1214,10 @@ static int fill_create_channel_param(struct allegro_channel *channel, param->max_pixel_value = 255; param->gop_ctrl_mode = 0x00000002; - param->freq_idr = channel->gop_size; + param->freq_idr = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size); param->freq_lt = 0; param->gdr_mode = 0x00000000; - param->gop_length = channel->gop_size; + param->gop_length = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size); param->subframe_latency = 0x00000000; param->lda_factors[0] = 51; @@ -1060,7 +1283,7 @@ static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev, struct allegro_channel *channel, dma_addr_t paddr, unsigned long size, - u64 stream_id) + u64 dst_handle) { struct mcu_msg_put_stream_buffer msg; @@ -1075,7 +1298,7 @@ static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev, msg.size = size; msg.offset = ENCODER_STREAM_OFFSET; /* copied to mcu_msg_encode_frame_response */ - msg.stream_id = stream_id; + msg.dst_handle = dst_handle; allegro_mbox_send(dev->mbox_command, &msg); @@ -1274,23 +1497,30 @@ static ssize_t allegro_h264_write_sps(struct allegro_channel *channel, /* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */ unsigned int crop_unit_x = 2; unsigned int crop_unit_y = 2; + enum v4l2_mpeg_video_h264_profile profile; + enum v4l2_mpeg_video_h264_level level; + unsigned int cpb_size; + unsigned int cpb_size_scale; sps = kzalloc(sizeof(*sps), GFP_KERNEL); if (!sps) return -ENOMEM; - sps->profile_idc = nal_h264_profile_from_v4l2(channel->profile); + profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile); + level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level); + + sps->profile_idc = nal_h264_profile_from_v4l2(profile); sps->constraint_set0_flag = 0; sps->constraint_set1_flag = 1; sps->constraint_set2_flag = 0; sps->constraint_set3_flag = 0; sps->constraint_set4_flag = 0; sps->constraint_set5_flag = 0; - sps->level_idc = nal_h264_level_from_v4l2(channel->level); + sps->level_idc = nal_h264_level_from_v4l2(level); sps->seq_parameter_set_id = 0; - sps->log2_max_frame_num_minus4 = 0; + sps->log2_max_frame_num_minus4 = LOG2_MAX_FRAME_NUM - 4; sps->pic_order_cnt_type = 0; - sps->log2_max_pic_order_cnt_lsb_minus4 = 6; + sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4; sps->max_num_ref_frames = 3; sps->gaps_in_frame_num_value_allowed_flag = 0; sps->pic_width_in_mbs_minus1 = @@ -1331,13 +1561,15 @@ static ssize_t allegro_h264_write_sps(struct allegro_channel *channel, sps->vui.vcl_hrd_parameters_present_flag = 1; sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0; sps->vui.vcl_hrd_parameters.bit_rate_scale = 0; - sps->vui.vcl_hrd_parameters.cpb_size_scale = 1; /* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */ sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] = channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1; /* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */ + cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size); + cpb_size_scale = ffs(cpb_size) - 4; + sps->vui.vcl_hrd_parameters.cpb_size_scale = cpb_size_scale; sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] = - (channel->cpb_size * 1000) / (1 << (4 + sps->vui.vcl_hrd_parameters.cpb_size_scale)) - 1; + (cpb_size * 1000) / (1 << (4 + cpb_size_scale)) - 1; sps->vui.vcl_hrd_parameters.cbr_flag[0] = !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable); sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31; @@ -1392,45 +1624,165 @@ static ssize_t allegro_h264_write_pps(struct allegro_channel *channel, return size; } -static bool allegro_channel_is_at_eos(struct allegro_channel *channel) +static void allegro_channel_eos_event(struct allegro_channel *channel) { - bool is_at_eos = false; + const struct v4l2_event eos_event = { + .type = V4L2_EVENT_EOS + }; - switch (allegro_get_state(channel)) { - case ALLEGRO_STATE_STOPPED: - is_at_eos = true; - break; - case ALLEGRO_STATE_DRAIN: - case ALLEGRO_STATE_WAIT_FOR_BUFFER: - mutex_lock(&channel->shadow_list_lock); - if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) == 0 && - list_empty(&channel->source_shadow_list)) - is_at_eos = true; - mutex_unlock(&channel->shadow_list_lock); - break; - default: - break; - } + v4l2_event_queue_fh(&channel->fh, &eos_event); +} - return is_at_eos; +static ssize_t allegro_hevc_write_vps(struct allegro_channel *channel, + void *dest, size_t n) +{ + struct allegro_dev *dev = channel->dev; + struct nal_hevc_vps *vps; + struct nal_hevc_profile_tier_level *ptl; + ssize_t size; + unsigned int num_ref_frames = channel->num_ref_idx_l0; + s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile); + s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level); + s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier); + + vps = kzalloc(sizeof(*vps), GFP_KERNEL); + if (!vps) + return -ENOMEM; + + vps->base_layer_internal_flag = 1; + vps->base_layer_available_flag = 1; + vps->temporal_id_nesting_flag = 1; + + ptl = &vps->profile_tier_level; + ptl->general_profile_idc = nal_hevc_profile_from_v4l2(profile); + ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1; + ptl->general_tier_flag = nal_hevc_tier_from_v4l2(tier); + ptl->general_progressive_source_flag = 1; + ptl->general_frame_only_constraint_flag = 1; + ptl->general_level_idc = nal_hevc_level_from_v4l2(level); + + vps->sub_layer_ordering_info_present_flag = 0; + vps->max_dec_pic_buffering_minus1[0] = num_ref_frames; + vps->max_num_reorder_pics[0] = num_ref_frames; + + size = nal_hevc_write_vps(&dev->plat_dev->dev, dest, n, vps); + + kfree(vps); + + return size; } -static void allegro_channel_buf_done(struct allegro_channel *channel, - struct vb2_v4l2_buffer *buf, - enum vb2_buffer_state state) +static ssize_t allegro_hevc_write_sps(struct allegro_channel *channel, + void *dest, size_t n) { - const struct v4l2_event eos_event = { - .type = V4L2_EVENT_EOS - }; + struct allegro_dev *dev = channel->dev; + struct nal_hevc_sps *sps; + struct nal_hevc_profile_tier_level *ptl; + ssize_t size; + unsigned int num_ref_frames = channel->num_ref_idx_l0; + s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile); + s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level); + s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier); + + sps = kzalloc(sizeof(*sps), GFP_KERNEL); + if (!sps) + return -ENOMEM; + + sps->temporal_id_nesting_flag = 1; + + ptl = &sps->profile_tier_level; + ptl->general_profile_idc = nal_hevc_profile_from_v4l2(profile); + ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1; + ptl->general_tier_flag = nal_hevc_tier_from_v4l2(tier); + ptl->general_progressive_source_flag = 1; + ptl->general_frame_only_constraint_flag = 1; + ptl->general_level_idc = nal_hevc_level_from_v4l2(level); + + sps->seq_parameter_set_id = 0; + sps->chroma_format_idc = 1; /* Only 4:2:0 sampling supported */ + sps->pic_width_in_luma_samples = round_up(channel->width, 8); + sps->pic_height_in_luma_samples = round_up(channel->height, 8); + sps->conf_win_right_offset = + sps->pic_width_in_luma_samples - channel->width; + sps->conf_win_bottom_offset = + sps->pic_height_in_luma_samples - channel->height; + sps->conformance_window_flag = + sps->conf_win_right_offset || sps->conf_win_bottom_offset; + + sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4; + + sps->sub_layer_ordering_info_present_flag = 1; + sps->max_dec_pic_buffering_minus1[0] = num_ref_frames; + sps->max_num_reorder_pics[0] = num_ref_frames; + + sps->log2_min_luma_coding_block_size_minus3 = + channel->min_cu_size - 3; + sps->log2_diff_max_min_luma_coding_block_size = + channel->max_cu_size - channel->min_cu_size; + sps->log2_min_luma_transform_block_size_minus2 = + channel->min_tu_size - 2; + sps->log2_diff_max_min_luma_transform_block_size = + channel->max_tu_size - channel->min_tu_size; + sps->max_transform_hierarchy_depth_intra = + channel->max_transfo_depth_intra; + sps->max_transform_hierarchy_depth_inter = + channel->max_transfo_depth_inter; + + sps->sps_temporal_mvp_enabled_flag = channel->temporal_mvp_enable; + sps->strong_intra_smoothing_enabled_flag = channel->max_cu_size > 4; + + size = nal_hevc_write_sps(&dev->plat_dev->dev, dest, n, sps); + + kfree(sps); + + return size; +} + +static ssize_t allegro_hevc_write_pps(struct allegro_channel *channel, + struct mcu_msg_encode_frame_response *msg, + void *dest, size_t n) +{ + struct allegro_dev *dev = channel->dev; + struct nal_hevc_pps *pps; + ssize_t size; + int i; + + pps = kzalloc(sizeof(*pps), GFP_KERNEL); + if (!pps) + return -ENOMEM; + + pps->pps_pic_parameter_set_id = 0; + pps->pps_seq_parameter_set_id = 0; + + if (msg->num_column > 1 || msg->num_row > 1) { + pps->tiles_enabled_flag = 1; + pps->num_tile_columns_minus1 = msg->num_column - 1; + pps->num_tile_rows_minus1 = msg->num_row - 1; - if (allegro_channel_is_at_eos(channel)) { - buf->flags |= V4L2_BUF_FLAG_LAST; - v4l2_event_queue_fh(&channel->fh, &eos_event); + for (i = 0; i < msg->num_column; i++) + pps->column_width_minus1[i] = msg->tile_width[i] - 1; - allegro_set_state(channel, ALLEGRO_STATE_STOPPED); + for (i = 0; i < msg->num_row; i++) + pps->row_height_minus1[i] = msg->tile_height[i] - 1; } - v4l2_m2m_buf_done(buf, state); + pps->loop_filter_across_tiles_enabled_flag = + channel->enable_loop_filter_across_tiles; + pps->pps_loop_filter_across_slices_enabled_flag = + channel->enable_loop_filter_across_slices; + pps->deblocking_filter_control_present_flag = 1; + pps->deblocking_filter_override_enabled_flag = + channel->enable_deblocking_filter_override; + pps->pps_beta_offset_div2 = BETA_OFFSET_DIV_2; + pps->pps_tc_offset_div2 = TC_OFFSET_DIV_2; + + pps->lists_modification_present_flag = channel->enable_reordering; + + size = nal_hevc_write_pps(&dev->plat_dev->dev, dest, n, pps); + + kfree(pps); + + return size; } static u64 allegro_put_buffer(struct allegro_channel *channel, @@ -1491,7 +1843,7 @@ static void allegro_channel_finish_frame(struct allegro_channel *channel, channel->mcu_channel_id); dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list, - msg->stream_id); + msg->dst_handle); if (!dst_buf) v4l2_warn(&dev->v4l2_dev, "channel %d: invalid stream buffer\n", @@ -1500,6 +1852,12 @@ static void allegro_channel_finish_frame(struct allegro_channel *channel, if (!src_buf || !dst_buf) goto err; + if (v4l2_m2m_is_last_draining_src_buf(channel->fh.m2m_ctx, src_buf)) { + dst_buf->flags |= V4L2_BUF_FLAG_LAST; + allegro_channel_eos_event(channel); + v4l2_m2m_mark_stopped(channel->fh.m2m_ctx); + } + dst_buf->sequence = channel->csequence++; if (msg->error_code & AL_ERROR) { @@ -1550,8 +1908,27 @@ static void allegro_channel_finish_frame(struct allegro_channel *channel, curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0); free = partition->offset; + + if (channel->codec == V4L2_PIX_FMT_HEVC && msg->is_idr) { + len = allegro_hevc_write_vps(channel, curr, free); + if (len < 0) { + v4l2_err(&dev->v4l2_dev, + "not enough space for video parameter set: %zd left\n", + free); + goto err; + } + curr += len; + free -= len; + v4l2_dbg(1, debug, &dev->v4l2_dev, + "channel %d: wrote %zd byte VPS nal unit\n", + channel->mcu_channel_id, len); + } + if (msg->is_idr) { - len = allegro_h264_write_sps(channel, curr, free); + if (channel->codec == V4L2_PIX_FMT_H264) + len = allegro_h264_write_sps(channel, curr, free); + else + len = allegro_hevc_write_sps(channel, curr, free); if (len < 0) { v4l2_err(&dev->v4l2_dev, "not enough space for sequence parameter set: %zd left\n", @@ -1566,7 +1943,10 @@ static void allegro_channel_finish_frame(struct allegro_channel *channel, } if (msg->slice_type == AL_ENC_SLICE_TYPE_I) { - len = allegro_h264_write_pps(channel, curr, free); + if (channel->codec == V4L2_PIX_FMT_H264) + len = allegro_h264_write_pps(channel, curr, free); + else + len = allegro_hevc_write_pps(channel, msg, curr, free); if (len < 0) { v4l2_err(&dev->v4l2_dev, "not enough space for picture parameter set: %zd left\n", @@ -1584,7 +1964,10 @@ static void allegro_channel_finish_frame(struct allegro_channel *channel, dst_buf->vb2_buf.planes[0].data_offset = free; free = 0; } else { - len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free); + if (channel->codec == V4L2_PIX_FMT_H264) + len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free); + else + len = nal_hevc_write_filler(&dev->plat_dev->dev, curr, free); if (len < 0) { v4l2_err(&dev->v4l2_dev, "failed to write %zd filler data\n", free); @@ -1626,7 +2009,7 @@ err: v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); if (dst_buf) - allegro_channel_buf_done(channel, dst_buf, state); + v4l2_m2m_buf_done(dst_buf, state); } static int allegro_handle_init(struct allegro_dev *dev, @@ -1984,6 +2367,16 @@ static void allegro_destroy_channel(struct allegro_channel *channel) v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false); v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false); v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false); + + v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_level, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, false); + v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, false); + v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false); v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false); v4l2_ctrl_grab(channel->mpeg_video_bitrate, false); @@ -2011,7 +2404,6 @@ static int allegro_create_channel(struct allegro_channel *channel) { struct allegro_dev *dev = channel->dev; unsigned long timeout; - enum v4l2_mpeg_video_h264_level min_level; if (channel_exists(channel)) { v4l2_warn(&dev->v4l2_dev, @@ -2034,16 +2426,6 @@ static int allegro_create_channel(struct allegro_channel *channel) DIV_ROUND_UP(channel->framerate.numerator, channel->framerate.denominator)); - min_level = select_minimum_h264_level(channel->width, channel->height); - if (channel->level < min_level) { - v4l2_warn(&dev->v4l2_dev, - "user %d: selected Level %s too low: increasing to Level %s\n", - channel->user_id, - v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[channel->level], - v4l2_ctrl_get_menu(V4L2_CID_MPEG_VIDEO_H264_LEVEL)[min_level]); - channel->level = min_level; - } - v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true); v4l2_ctrl_grab(channel->mpeg_video_h264_level, true); v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true); @@ -2051,6 +2433,16 @@ static int allegro_create_channel(struct allegro_channel *channel) v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true); v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true); v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true); + + v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_level, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, true); + v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, true); + v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true); v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true); v4l2_ctrl_grab(channel->mpeg_video_bitrate, true); @@ -2079,6 +2471,124 @@ err: return channel->error; } +/** + * allegro_channel_adjust() - Adjust channel parameters to current format + * @channel: the channel to adjust + * + * Various parameters of a channel and their limits depend on the currently + * set format. Adjust the parameters after a format change in one go. + */ +static void allegro_channel_adjust(struct allegro_channel *channel) +{ + struct allegro_dev *dev = channel->dev; + u32 codec = channel->codec; + struct v4l2_ctrl *ctrl; + s64 min; + s64 max; + + channel->sizeimage_encoded = + estimate_stream_size(channel->width, channel->height); + + if (codec == V4L2_PIX_FMT_H264) { + ctrl = channel->mpeg_video_h264_level; + min = select_minimum_h264_level(channel->width, channel->height); + } else { + ctrl = channel->mpeg_video_hevc_level; + min = select_minimum_hevc_level(channel->width, channel->height); + } + if (ctrl->minimum > min) + v4l2_dbg(1, debug, &dev->v4l2_dev, + "%s.minimum: %lld -> %lld\n", + v4l2_ctrl_get_name(ctrl->id), ctrl->minimum, min); + v4l2_ctrl_lock(ctrl); + __v4l2_ctrl_modify_range(ctrl, min, ctrl->maximum, + ctrl->step, ctrl->default_value); + v4l2_ctrl_unlock(ctrl); + + ctrl = channel->mpeg_video_bitrate; + if (codec == V4L2_PIX_FMT_H264) + max = h264_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level)); + else + max = hevc_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level)); + if (ctrl->maximum < max) + v4l2_dbg(1, debug, &dev->v4l2_dev, + "%s: maximum: %lld -> %lld\n", + v4l2_ctrl_get_name(ctrl->id), ctrl->maximum, max); + v4l2_ctrl_lock(ctrl); + __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, + ctrl->step, ctrl->default_value); + v4l2_ctrl_unlock(ctrl); + + ctrl = channel->mpeg_video_bitrate_peak; + v4l2_ctrl_lock(ctrl); + __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, + ctrl->step, ctrl->default_value); + v4l2_ctrl_unlock(ctrl); + + v4l2_ctrl_activate(channel->mpeg_video_h264_profile, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_level, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_i_frame_qp, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_max_qp, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_min_qp, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_p_frame_qp, + codec == V4L2_PIX_FMT_H264); + v4l2_ctrl_activate(channel->mpeg_video_h264_b_frame_qp, + codec == V4L2_PIX_FMT_H264); + + v4l2_ctrl_activate(channel->mpeg_video_hevc_profile, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_level, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_tier, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_i_frame_qp, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_max_qp, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_min_qp, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_p_frame_qp, + codec == V4L2_PIX_FMT_HEVC); + v4l2_ctrl_activate(channel->mpeg_video_hevc_b_frame_qp, + codec == V4L2_PIX_FMT_HEVC); + + if (codec == V4L2_PIX_FMT_H264) + channel->log2_max_frame_num = LOG2_MAX_FRAME_NUM; + channel->temporal_mvp_enable = true; + channel->dbf_ovr_en = (codec == V4L2_PIX_FMT_H264); + channel->enable_deblocking_filter_override = (codec == V4L2_PIX_FMT_HEVC); + channel->enable_reordering = (codec == V4L2_PIX_FMT_HEVC); + channel->enable_loop_filter_across_tiles = true; + channel->enable_loop_filter_across_slices = true; + + if (codec == V4L2_PIX_FMT_H264) { + channel->b_hrz_me_range = 8; + channel->b_vrt_me_range = 8; + channel->p_hrz_me_range = 16; + channel->p_vrt_me_range = 16; + channel->max_cu_size = ilog2(16); + channel->min_cu_size = ilog2(8); + channel->max_tu_size = ilog2(4); + channel->min_tu_size = ilog2(4); + } else { + channel->b_hrz_me_range = 16; + channel->b_vrt_me_range = 16; + channel->p_hrz_me_range = 32; + channel->p_vrt_me_range = 32; + channel->max_cu_size = ilog2(32); + channel->min_cu_size = ilog2(8); + channel->max_tu_size = ilog2(32); + channel->min_tu_size = ilog2(4); + } + channel->max_transfo_depth_intra = 1; + channel->max_transfo_depth_inter = 1; +} + static void allegro_set_default_params(struct allegro_channel *channel) { channel->width = ALLEGRO_WIDTH_DEFAULT; @@ -2095,16 +2605,6 @@ static void allegro_set_default_params(struct allegro_channel *channel) channel->sizeimage_raw = channel->stride * channel->height * 3 / 2; channel->codec = V4L2_PIX_FMT_H264; - channel->profile = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE; - channel->level = - select_minimum_h264_level(channel->width, channel->height); - channel->sizeimage_encoded = - estimate_stream_size(channel->width, channel->height); - - channel->bitrate = maximum_bitrate(channel->level); - channel->bitrate_peak = maximum_bitrate(channel->level); - channel->cpb_size = maximum_cpb_size(channel->level); - channel->gop_size = ALLEGRO_GOP_SIZE_DEFAULT; } static int allegro_queue_setup(struct vb2_queue *vq, @@ -2145,10 +2645,6 @@ static int allegro_buf_prepare(struct vb2_buffer *vb) struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue); struct allegro_dev *dev = channel->dev; - if (allegro_get_state(channel) == ALLEGRO_STATE_DRAIN && - V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) - return -EBUSY; - if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { if (vbuf->field == V4L2_FIELD_ANY) vbuf->field = V4L2_FIELD_NONE; @@ -2167,10 +2663,21 @@ static void allegro_buf_queue(struct vb2_buffer *vb) { struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue); struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vb2_queue *q = vb->vb2_queue; + + if (V4L2_TYPE_IS_CAPTURE(q->type) && + vb2_is_streaming(q) && + v4l2_m2m_dst_buf_is_last(channel->fh.m2m_ctx)) { + unsigned int i; + + for (i = 0; i < vb->num_planes; i++) + vb->planes[i].bytesused = 0; - if (allegro_get_state(channel) == ALLEGRO_STATE_WAIT_FOR_BUFFER && - vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { - allegro_channel_buf_done(channel, vbuf, VB2_BUF_STATE_DONE); + vbuf->field = V4L2_FIELD_NONE; + vbuf->sequence = channel->csequence++; + + v4l2_m2m_last_buffer_done(channel->fh.m2m_ctx, vbuf); + allegro_channel_eos_event(channel); return; } @@ -2186,12 +2693,12 @@ static int allegro_start_streaming(struct vb2_queue *q, unsigned int count) "%s: start streaming\n", V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture"); - if (V4L2_TYPE_IS_OUTPUT(q->type)) { + v4l2_m2m_update_start_streaming_state(channel->fh.m2m_ctx, q); + + if (V4L2_TYPE_IS_OUTPUT(q->type)) channel->osequence = 0; - allegro_set_state(channel, ALLEGRO_STATE_ENCODING); - } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + else channel->csequence = 0; - } return 0; } @@ -2216,10 +2723,9 @@ static void allegro_stop_streaming(struct vb2_queue *q) } mutex_unlock(&channel->shadow_list_lock); - allegro_set_state(channel, ALLEGRO_STATE_STOPPED); while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx))) v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR); - } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) { + } else { mutex_lock(&channel->shadow_list_lock); list_for_each_entry_safe(shadow, tmp, &channel->stream_shadow_list, head) { @@ -2232,6 +2738,12 @@ static void allegro_stop_streaming(struct vb2_queue *q) while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx))) v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR); } + + v4l2_m2m_update_stop_streaming_state(channel->fh.m2m_ctx, q); + + if (V4L2_TYPE_IS_OUTPUT(q->type) && + v4l2_m2m_has_stopped(channel->fh.m2m_ctx)) + allegro_channel_eos_event(channel); } static const struct vb2_ops allegro_queue_ops = { @@ -2337,9 +2849,6 @@ static int allegro_s_ctrl(struct v4l2_ctrl *ctrl) "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val); switch (ctrl->id) { - case V4L2_CID_MPEG_VIDEO_H264_LEVEL: - channel->level = ctrl->val; - break; case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: channel->frame_rc_enable = ctrl->val; break; @@ -2349,12 +2858,6 @@ static int allegro_s_ctrl(struct v4l2_ctrl *ctrl) v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak, ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR); break; - case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE: - channel->cpb_size = ctrl->val; - break; - case V4L2_CID_MPEG_VIDEO_GOP_SIZE: - channel->gop_size = ctrl->val; - break; case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: @@ -2378,6 +2881,10 @@ static int allegro_open(struct file *file) struct v4l2_ctrl_handler *handler; u64 mask; int ret; + unsigned int bitrate_max; + unsigned int bitrate_def; + unsigned int cpb_size_max; + unsigned int cpb_size_def; channel = kzalloc(sizeof(*channel), GFP_KERNEL); if (!channel) @@ -2432,6 +2939,51 @@ static int allegro_open(struct file *file) &allegro_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, 0, 51, 1, 30); + + channel->mpeg_video_hevc_profile = + v4l2_ctrl_new_std_menu(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 0x0, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); + channel->mpeg_video_hevc_level = + v4l2_ctrl_new_std_menu(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0x0, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1); + channel->mpeg_video_hevc_tier = + v4l2_ctrl_new_std_menu(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_TIER, + V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, 0x0, + V4L2_MPEG_VIDEO_HEVC_TIER_MAIN); + channel->mpeg_video_hevc_i_frame_qp = + v4l2_ctrl_new_std(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, + 0, 51, 1, 30); + channel->mpeg_video_hevc_max_qp = + v4l2_ctrl_new_std(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + 0, 51, 1, 51); + channel->mpeg_video_hevc_min_qp = + v4l2_ctrl_new_std(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + 0, 51, 1, 0); + channel->mpeg_video_hevc_p_frame_qp = + v4l2_ctrl_new_std(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP, + 0, 51, 1, 30); + channel->mpeg_video_hevc_b_frame_qp = + v4l2_ctrl_new_std(handler, + &allegro_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP, + 0, 51, 1, 30); + channel->mpeg_video_frame_rc_enable = v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, @@ -2443,26 +2995,35 @@ static int allegro_open(struct file *file) V4L2_CID_MPEG_VIDEO_BITRATE_MODE, V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); + + if (channel->codec == V4L2_PIX_FMT_H264) { + bitrate_max = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1); + bitrate_def = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1); + cpb_size_max = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1); + cpb_size_def = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1); + } else { + bitrate_max = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1); + bitrate_def = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1); + cpb_size_max = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1); + cpb_size_def = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1); + } channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, V4L2_CID_MPEG_VIDEO_BITRATE, - 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), - 1, channel->bitrate); + 0, bitrate_max, 1, bitrate_def); channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, - 0, maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), - 1, channel->bitrate_peak); + 0, bitrate_max, 1, bitrate_def); channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE, - 0, maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), - 1, channel->cpb_size); + 0, cpb_size_max, 1, cpb_size_def); channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE, 0, ALLEGRO_GOP_SIZE_MAX, - 1, channel->gop_size); + 1, ALLEGRO_GOP_SIZE_DEFAULT); v4l2_ctrl_new_std(handler, &allegro_ctrl_ops, V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, @@ -2477,14 +3038,14 @@ static int allegro_open(struct file *file) v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode); + v4l2_ctrl_handler_setup(handler); + channel->mcu_channel_id = -1; channel->user_id = -1; INIT_LIST_HEAD(&channel->buffers_reference); INIT_LIST_HEAD(&channel->buffers_intermediate); - list_add(&channel->list, &dev->channels); - channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel, allegro_queue_init); @@ -2493,9 +3054,12 @@ static int allegro_open(struct file *file) goto error; } + list_add(&channel->list, &dev->channels); file->private_data = &channel->fh; v4l2_fh_add(&channel->fh); + allegro_channel_adjust(channel); + return 0; error: @@ -2539,14 +3103,19 @@ static int allegro_querycap(struct file *file, void *fh, static int allegro_enum_fmt_vid(struct file *file, void *fh, struct v4l2_fmtdesc *f) { - if (f->index) - return -EINVAL; switch (f->type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT: + if (f->index >= 1) + return -EINVAL; f->pixelformat = V4L2_PIX_FMT_NV12; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE: - f->pixelformat = V4L2_PIX_FMT_H264; + if (f->index >= 2) + return -EINVAL; + if (f->index == 0) + f->pixelformat = V4L2_PIX_FMT_H264; + if (f->index == 1) + f->pixelformat = V4L2_PIX_FMT_HEVC; break; default: return -EINVAL; @@ -2585,7 +3154,10 @@ static int allegro_try_fmt_vid_cap(struct file *file, void *fh, f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height, ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX); - f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264; + if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_HEVC && + f->fmt.pix.pixelformat != V4L2_PIX_FMT_H264) + f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264; + f->fmt.pix.bytesperline = 0; f->fmt.pix.sizeimage = estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height); @@ -2593,6 +3165,30 @@ static int allegro_try_fmt_vid_cap(struct file *file, void *fh, return 0; } +static int allegro_s_fmt_vid_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct allegro_channel *channel = fh_to_channel(fh); + struct vb2_queue *vq; + int err; + + err = allegro_try_fmt_vid_cap(file, fh, f); + if (err) + return err; + + vq = v4l2_m2m_get_vq(channel->fh.m2m_ctx, f->type); + if (!vq) + return -EINVAL; + if (vb2_is_busy(vq)) + return -EBUSY; + + channel->codec = f->fmt.pix.pixelformat; + + allegro_channel_adjust(channel); + + return 0; +} + static int allegro_g_fmt_vid_out(struct file *file, void *fh, struct v4l2_format *f) { @@ -2660,72 +3256,23 @@ static int allegro_s_fmt_vid_out(struct file *file, void *fh, channel->quantization = f->fmt.pix.quantization; channel->xfer_func = f->fmt.pix.xfer_func; - channel->level = - select_minimum_h264_level(channel->width, channel->height); - channel->sizeimage_encoded = - estimate_stream_size(channel->width, channel->height); + allegro_channel_adjust(channel); return 0; } static int allegro_channel_cmd_stop(struct allegro_channel *channel) { - struct allegro_dev *dev = channel->dev; - struct vb2_v4l2_buffer *dst_buf; - - switch (allegro_get_state(channel)) { - case ALLEGRO_STATE_DRAIN: - case ALLEGRO_STATE_WAIT_FOR_BUFFER: - return -EBUSY; - case ALLEGRO_STATE_ENCODING: - allegro_set_state(channel, ALLEGRO_STATE_DRAIN); - break; - default: - return 0; - } - - /* If there are output buffers, they must be encoded */ - if (v4l2_m2m_num_src_bufs_ready(channel->fh.m2m_ctx) != 0) { - v4l2_dbg(1, debug, &dev->v4l2_dev, - "channel %d: CMD_STOP: continue encoding src buffers\n", - channel->mcu_channel_id); - return 0; - } - - /* If there are capture buffers, use it to signal EOS */ - dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx); - if (dst_buf) { - v4l2_dbg(1, debug, &dev->v4l2_dev, - "channel %d: CMD_STOP: signaling EOS\n", - channel->mcu_channel_id); - allegro_channel_buf_done(channel, dst_buf, VB2_BUF_STATE_DONE); - return 0; - } - - /* - * If there are no capture buffers, we need to wait for the next - * buffer to signal EOS. - */ - v4l2_dbg(1, debug, &dev->v4l2_dev, - "channel %d: CMD_STOP: wait for CAPTURE buffer to signal EOS\n", - channel->mcu_channel_id); - allegro_set_state(channel, ALLEGRO_STATE_WAIT_FOR_BUFFER); + if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx)) + allegro_channel_eos_event(channel); return 0; } static int allegro_channel_cmd_start(struct allegro_channel *channel) { - switch (allegro_get_state(channel)) { - case ALLEGRO_STATE_DRAIN: - case ALLEGRO_STATE_WAIT_FOR_BUFFER: - return -EBUSY; - case ALLEGRO_STATE_STOPPED: - allegro_set_state(channel, ALLEGRO_STATE_ENCODING); - break; - default: - return 0; - } + if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx)) + vb2_clear_last_buffer_dequeued(&channel->fh.m2m_ctx->cap_q_ctx.q); return 0; } @@ -2740,17 +3287,15 @@ static int allegro_encoder_cmd(struct file *file, void *fh, if (err) return err; - switch (cmd->cmd) { - case V4L2_ENC_CMD_STOP: + err = v4l2_m2m_ioctl_encoder_cmd(file, fh, cmd); + if (err) + return err; + + if (cmd->cmd == V4L2_ENC_CMD_STOP) err = allegro_channel_cmd_stop(channel); - break; - case V4L2_ENC_CMD_START: + + if (cmd->cmd == V4L2_ENC_CMD_START) err = allegro_channel_cmd_start(channel); - break; - default: - err = -EINVAL; - break; - } return err; } @@ -2759,6 +3304,7 @@ static int allegro_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize) { switch (fsize->pixel_format) { + case V4L2_PIX_FMT_HEVC: case V4L2_PIX_FMT_H264: case V4L2_PIX_FMT_NV12: break; @@ -2853,7 +3399,7 @@ static const struct v4l2_ioctl_ops allegro_ioctl_ops = { .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid, .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap, .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap, - .vidioc_s_fmt_vid_cap = allegro_try_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = allegro_s_fmt_vid_cap, .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out, .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out, .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out, diff --git a/drivers/staging/media/allegro-dvt/allegro-mail.c b/drivers/media/platform/allegro-dvt/allegro-mail.c index 9286d2162377..7e08c5050f2e 100644 --- a/drivers/staging/media/allegro-dvt/allegro-mail.c +++ b/drivers/media/platform/allegro-dvt/allegro-mail.c @@ -67,12 +67,16 @@ static inline u32 settings_get_mcu_codec(struct create_channel_param *param) if (version < MCU_MSG_VERSION_2019_2) { switch (pixelformat) { + case V4L2_PIX_FMT_HEVC: + return 2; case V4L2_PIX_FMT_H264: default: return 1; } } else { switch (pixelformat) { + case V4L2_PIX_FMT_HEVC: + return 1; case V4L2_PIX_FMT_H264: default: return 0; @@ -109,12 +113,17 @@ allegro_encode_config_blob(u32 *dst, struct create_channel_param *param) val = 0; val |= param->temporal_mvp_enable ? BIT(20) : 0; - val |= FIELD_PREP(GENMASK(7, 4), param->log2_max_frame_num) | - FIELD_PREP(GENMASK(3, 0), param->log2_max_poc); + val |= FIELD_PREP(GENMASK(7, 4), param->log2_max_frame_num); + if (version >= MCU_MSG_VERSION_2019_2) + val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc - 1); + else + val |= FIELD_PREP(GENMASK(3, 0), param->log2_max_poc); dst[i++] = val; val = 0; + val |= param->enable_reordering ? BIT(0) : 0; val |= param->dbf_ovr_en ? BIT(2) : 0; + val |= param->override_lf ? BIT(12) : 0; dst[i++] = val; if (version >= MCU_MSG_VERSION_2019_2) { @@ -302,8 +311,8 @@ allegro_enc_put_stream_buffer(u32 *dst, dst[i++] = msg->mcu_addr; dst[i++] = msg->size; dst[i++] = msg->offset; - dst[i++] = lower_32_bits(msg->stream_id); - dst[i++] = upper_32_bits(msg->stream_id); + dst[i++] = lower_32_bits(msg->dst_handle); + dst[i++] = upper_32_bits(msg->dst_handle); return i * sizeof(*dst); } @@ -406,8 +415,8 @@ allegro_dec_encode_frame(struct mcu_msg_encode_frame_response *msg, u32 *src) msg->channel_id = src[i++]; - msg->stream_id = src[i++]; - msg->stream_id |= (((u64)src[i++]) << 32); + msg->dst_handle = src[i++]; + msg->dst_handle |= (((u64)src[i++]) << 32); msg->user_param = src[i++]; msg->user_param |= (((u64)src[i++]) << 32); msg->src_handle = src[i++]; diff --git a/drivers/staging/media/allegro-dvt/allegro-mail.h b/drivers/media/platform/allegro-dvt/allegro-mail.h index 486ecb12b098..2c7bc509eac3 100644 --- a/drivers/staging/media/allegro-dvt/allegro-mail.h +++ b/drivers/media/platform/allegro-dvt/allegro-mail.h @@ -65,6 +65,7 @@ struct create_channel_param { u32 temporal_mvp_enable; u32 enable_reordering; u32 dbf_ovr_en; + u32 override_lf; u32 num_ref_idx_l0; u32 num_ref_idx_l1; u32 custom_lda; @@ -191,7 +192,7 @@ struct mcu_msg_put_stream_buffer { u32 mcu_addr; u32 size; u32 offset; - u64 stream_id; + u64 dst_handle; }; struct mcu_msg_encode_frame { @@ -233,7 +234,7 @@ struct mcu_msg_encode_frame { struct mcu_msg_encode_frame_response { struct mcu_msg_header header; u32 channel_id; - u64 stream_id; /* see mcu_msg_put_stream_buffer */ + u64 dst_handle; /* see mcu_msg_put_stream_buffer */ u64 user_param; /* see mcu_msg_encode_frame */ u64 src_handle; /* see mcu_msg_encode_frame */ u16 skip; diff --git a/drivers/staging/media/allegro-dvt/nal-h264.c b/drivers/media/platform/allegro-dvt/nal-h264.c index bd48b8883572..94dd9266d850 100644 --- a/drivers/staging/media/allegro-dvt/nal-h264.c +++ b/drivers/media/platform/allegro-dvt/nal-h264.c @@ -22,6 +22,7 @@ #include <linux/log2.h> #include "nal-h264.h" +#include "nal-rbsp.h" /* * See Rec. ITU-T H.264 (04/2017) Table 7-1 – NAL unit type codes, syntax @@ -33,54 +34,6 @@ enum nal_unit_type { FILLER_DATA = 12, }; -struct rbsp; - -struct nal_h264_ops { - int (*rbsp_bit)(struct rbsp *rbsp, int *val); - int (*rbsp_bits)(struct rbsp *rbsp, int n, unsigned int *val); - int (*rbsp_uev)(struct rbsp *rbsp, unsigned int *val); - int (*rbsp_sev)(struct rbsp *rbsp, int *val); -}; - -/** - * struct rbsp - State object for handling a raw byte sequence payload - * @data: pointer to the data of the rbsp - * @size: maximum size of the data of the rbsp - * @pos: current bit position inside the rbsp - * @num_consecutive_zeros: number of zeros before @pos - * @ops: per datatype functions for interacting with the rbsp - * @error: an error occurred while handling the rbsp - * - * This struct is passed around the various parsing functions and tracks the - * current position within the raw byte sequence payload. - * - * The @ops field allows to separate the operation, i.e., reading/writing a - * value from/to that rbsp, from the structure of the NAL unit. This allows to - * have a single function for iterating the NAL unit, while @ops has function - * pointers for handling each type in the rbsp. - */ -struct rbsp { - u8 *data; - size_t size; - unsigned int pos; - unsigned int num_consecutive_zeros; - struct nal_h264_ops *ops; - int error; -}; - -static void rbsp_init(struct rbsp *rbsp, void *addr, size_t size, - struct nal_h264_ops *ops) -{ - if (!rbsp) - return; - - rbsp->data = addr; - rbsp->size = size; - rbsp->pos = 0; - rbsp->ops = ops; - rbsp->error = 0; -} - /** * nal_h264_profile_from_v4l2() - Get profile_idc for v4l2 h264 profile * @profile: the profile as &enum v4l2_mpeg_video_h264_profile @@ -155,281 +108,6 @@ int nal_h264_level_from_v4l2(enum v4l2_mpeg_video_h264_level level) } } -static int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value); -static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value); - -/* - * When reading or writing, the emulation_prevention_three_byte is detected - * only when the 2 one bits need to be inserted. Therefore, we are not - * actually adding the 0x3 byte, but the 2 one bits and the six 0 bits of the - * next byte. - */ -#define EMULATION_PREVENTION_THREE_BYTE (0x3 << 6) - -static int add_emulation_prevention_three_byte(struct rbsp *rbsp) -{ - rbsp->num_consecutive_zeros = 0; - rbsp_write_bits(rbsp, 8, EMULATION_PREVENTION_THREE_BYTE); - - return 0; -} - -static int discard_emulation_prevention_three_byte(struct rbsp *rbsp) -{ - unsigned int tmp = 0; - - rbsp->num_consecutive_zeros = 0; - rbsp_read_bits(rbsp, 8, &tmp); - if (tmp != EMULATION_PREVENTION_THREE_BYTE) - return -EINVAL; - - return 0; -} - -static inline int rbsp_read_bit(struct rbsp *rbsp) -{ - int shift; - int ofs; - int bit; - int err; - - if (rbsp->num_consecutive_zeros == 22) { - err = discard_emulation_prevention_three_byte(rbsp); - if (err) - return err; - } - - shift = 7 - (rbsp->pos % 8); - ofs = rbsp->pos / 8; - if (ofs >= rbsp->size) - return -EINVAL; - - bit = (rbsp->data[ofs] >> shift) & 1; - - rbsp->pos++; - - if (bit == 1 || - (rbsp->num_consecutive_zeros < 7 && (rbsp->pos % 8 == 0))) - rbsp->num_consecutive_zeros = 0; - else - rbsp->num_consecutive_zeros++; - - return bit; -} - -static inline int rbsp_write_bit(struct rbsp *rbsp, bool value) -{ - int shift; - int ofs; - - if (rbsp->num_consecutive_zeros == 22) - add_emulation_prevention_three_byte(rbsp); - - shift = 7 - (rbsp->pos % 8); - ofs = rbsp->pos / 8; - if (ofs >= rbsp->size) - return -EINVAL; - - rbsp->data[ofs] &= ~(1 << shift); - rbsp->data[ofs] |= value << shift; - - rbsp->pos++; - - if (value || - (rbsp->num_consecutive_zeros < 7 && (rbsp->pos % 8 == 0))) { - rbsp->num_consecutive_zeros = 0; - } else { - rbsp->num_consecutive_zeros++; - } - - return 0; -} - -static inline int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value) -{ - int i; - int bit; - unsigned int tmp = 0; - - if (n > 8 * sizeof(*value)) - return -EINVAL; - - for (i = n; i > 0; i--) { - bit = rbsp_read_bit(rbsp); - if (bit < 0) - return bit; - tmp |= bit << (i - 1); - } - - if (value) - *value = tmp; - - return 0; -} - -static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value) -{ - int ret; - - if (n > 8 * sizeof(value)) - return -EINVAL; - - while (n--) { - ret = rbsp_write_bit(rbsp, (value >> n) & 1); - if (ret) - return ret; - } - - return 0; -} - -static int rbsp_read_uev(struct rbsp *rbsp, unsigned int *value) -{ - int leading_zero_bits = 0; - unsigned int tmp = 0; - int ret; - - while ((ret = rbsp_read_bit(rbsp)) == 0) - leading_zero_bits++; - if (ret < 0) - return ret; - - if (leading_zero_bits > 0) { - ret = rbsp_read_bits(rbsp, leading_zero_bits, &tmp); - if (ret) - return ret; - } - - if (value) - *value = (1 << leading_zero_bits) - 1 + tmp; - - return 0; -} - -static int rbsp_write_uev(struct rbsp *rbsp, unsigned int *value) -{ - int ret; - int leading_zero_bits; - - if (!value) - return -EINVAL; - - leading_zero_bits = ilog2(*value + 1); - - ret = rbsp_write_bits(rbsp, leading_zero_bits, 0); - if (ret) - return ret; - - return rbsp_write_bits(rbsp, leading_zero_bits + 1, *value + 1); -} - -static int rbsp_read_sev(struct rbsp *rbsp, int *value) -{ - int ret; - unsigned int tmp; - - ret = rbsp_read_uev(rbsp, &tmp); - if (ret) - return ret; - - if (value) { - if (tmp & 1) - *value = (tmp + 1) / 2; - else - *value = -(tmp / 2); - } - - return 0; -} - -static int rbsp_write_sev(struct rbsp *rbsp, int *value) -{ - unsigned int tmp; - - if (!value) - return -EINVAL; - - if (*value > 0) - tmp = (2 * (*value)) | 1; - else - tmp = -2 * (*value); - - return rbsp_write_uev(rbsp, &tmp); -} - -static int __rbsp_write_bit(struct rbsp *rbsp, int *value) -{ - return rbsp_write_bit(rbsp, *value); -} - -static int __rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int *value) -{ - return rbsp_write_bits(rbsp, n, *value); -} - -static struct nal_h264_ops write = { - .rbsp_bit = __rbsp_write_bit, - .rbsp_bits = __rbsp_write_bits, - .rbsp_uev = rbsp_write_uev, - .rbsp_sev = rbsp_write_sev, -}; - -static int __rbsp_read_bit(struct rbsp *rbsp, int *value) -{ - int tmp = rbsp_read_bit(rbsp); - - if (tmp < 0) - return tmp; - *value = tmp; - - return 0; -} - -static struct nal_h264_ops read = { - .rbsp_bit = __rbsp_read_bit, - .rbsp_bits = rbsp_read_bits, - .rbsp_uev = rbsp_read_uev, - .rbsp_sev = rbsp_read_sev, -}; - -static inline void rbsp_bit(struct rbsp *rbsp, int *value) -{ - if (rbsp->error) - return; - rbsp->error = rbsp->ops->rbsp_bit(rbsp, value); -} - -static inline void rbsp_bits(struct rbsp *rbsp, int n, int *value) -{ - if (rbsp->error) - return; - rbsp->error = rbsp->ops->rbsp_bits(rbsp, n, value); -} - -static inline void rbsp_uev(struct rbsp *rbsp, unsigned int *value) -{ - if (rbsp->error) - return; - rbsp->error = rbsp->ops->rbsp_uev(rbsp, value); -} - -static inline void rbsp_sev(struct rbsp *rbsp, int *value) -{ - if (rbsp->error) - return; - rbsp->error = rbsp->ops->rbsp_sev(rbsp, value); -} - -static void nal_h264_rbsp_trailing_bits(struct rbsp *rbsp) -{ - unsigned int rbsp_stop_one_bit = 1; - unsigned int rbsp_alignment_zero_bit = 0; - - rbsp_bit(rbsp, &rbsp_stop_one_bit); - rbsp_bits(rbsp, round_up(rbsp->pos, 8) - rbsp->pos, - &rbsp_alignment_zero_bit); -} - static void nal_h264_write_start_code_prefix(struct rbsp *rbsp) { u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); @@ -767,7 +445,7 @@ ssize_t nal_h264_write_sps(const struct device *dev, nal_h264_rbsp_sps(&rbsp, sps); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); if (rbsp.error) return rbsp.error; @@ -814,7 +492,7 @@ ssize_t nal_h264_read_sps(const struct device *dev, nal_h264_rbsp_sps(&rbsp, sps); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); if (rbsp.error) return rbsp.error; @@ -859,7 +537,7 @@ ssize_t nal_h264_write_pps(const struct device *dev, nal_h264_rbsp_pps(&rbsp, pps); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); if (rbsp.error) return rbsp.error; @@ -896,7 +574,7 @@ ssize_t nal_h264_read_pps(const struct device *dev, nal_h264_rbsp_pps(&rbsp, pps); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); if (rbsp.error) return rbsp.error; @@ -942,7 +620,7 @@ ssize_t nal_h264_write_filler(const struct device *dev, void *dest, size_t n) nal_h264_write_filler_data(&rbsp); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); return DIV_ROUND_UP(rbsp.pos, 8); } @@ -991,7 +669,7 @@ ssize_t nal_h264_read_filler(const struct device *dev, void *src, size_t n) return -EINVAL; nal_h264_read_filler_data(&rbsp); - nal_h264_rbsp_trailing_bits(&rbsp); + rbsp_trailing_bits(&rbsp); if (rbsp.error) return rbsp.error; diff --git a/drivers/staging/media/allegro-dvt/nal-h264.h b/drivers/media/platform/allegro-dvt/nal-h264.h index 2ba7cbced7a5..2ba7cbced7a5 100644 --- a/drivers/staging/media/allegro-dvt/nal-h264.h +++ b/drivers/media/platform/allegro-dvt/nal-h264.h diff --git a/drivers/media/platform/allegro-dvt/nal-hevc.c b/drivers/media/platform/allegro-dvt/nal-hevc.c new file mode 100644 index 000000000000..5db540c69bfe --- /dev/null +++ b/drivers/media/platform/allegro-dvt/nal-hevc.c @@ -0,0 +1,824 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2020 Pengutronix, Michael Tretter <kernel@pengutronix.de> + * + * Convert NAL units between raw byte sequence payloads (RBSP) and C structs. + * + * The conversion is defined in "ITU-T Rec. H.265 (02/2018) high efficiency + * video coding". Decoder drivers may use the parser to parse RBSP from + * encoded streams and configure the hardware, if the hardware is not able to + * parse RBSP itself. Encoder drivers may use the generator to generate the + * RBSP for VPS/SPS/PPS nal units and add them to the encoded stream if the + * hardware does not generate the units. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/v4l2-controls.h> + +#include <linux/device.h> +#include <linux/export.h> +#include <linux/log2.h> + +#include "nal-hevc.h" +#include "nal-rbsp.h" + +/* + * See Rec. ITU-T H.265 (02/2018) Table 7-1 – NAL unit type codes and NAL unit + * type classes + */ +enum nal_unit_type { + VPS_NUT = 32, + SPS_NUT = 33, + PPS_NUT = 34, + FD_NUT = 38, +}; + +int nal_hevc_profile_from_v4l2(enum v4l2_mpeg_video_hevc_profile profile) +{ + switch (profile) { + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: + return 1; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: + return 2; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: + return 3; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(nal_hevc_profile_from_v4l2); + +int nal_hevc_tier_from_v4l2(enum v4l2_mpeg_video_hevc_tier tier) +{ + switch (tier) { + case V4L2_MPEG_VIDEO_HEVC_TIER_MAIN: + return 0; + case V4L2_MPEG_VIDEO_HEVC_TIER_HIGH: + return 1; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(nal_hevc_tier_from_v4l2); + +int nal_hevc_level_from_v4l2(enum v4l2_mpeg_video_hevc_level level) +{ + /* + * T-Rec-H.265 p. 280: general_level_idc and sub_layer_level_idc[ i ] + * shall be set equal to a value of 30 times the level number + * specified in Table A.6. + */ + int factor = 30 / 10; + + switch (level) { + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: + return factor * 10; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: + return factor * 20; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: + return factor * 21; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: + return factor * 30; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: + return factor * 31; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: + return factor * 40; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: + return factor * 41; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: + return factor * 50; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: + return factor * 51; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: + return factor * 52; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_6: + return factor * 60; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1: + return factor * 61; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2: + return factor * 62; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(nal_hevc_level_from_v4l2); + +static void nal_hevc_write_start_code_prefix(struct rbsp *rbsp) +{ + u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); + int i = 4; + + if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { + rbsp->error = -EINVAL; + return; + } + + p[0] = 0x00; + p[1] = 0x00; + p[2] = 0x00; + p[3] = 0x01; + + rbsp->pos += i * 8; +} + +static void nal_hevc_read_start_code_prefix(struct rbsp *rbsp) +{ + u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); + int i = 4; + + if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) { + rbsp->error = -EINVAL; + return; + } + + if (p[0] != 0x00 || p[1] != 0x00 || p[2] != 0x00 || p[3] != 0x01) { + rbsp->error = -EINVAL; + return; + } + + rbsp->pos += i * 8; +} + +static void nal_hevc_write_filler_data(struct rbsp *rbsp) +{ + u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); + int i; + + /* Keep 1 byte extra for terminating the NAL unit */ + i = rbsp->size - DIV_ROUND_UP(rbsp->pos, 8) - 1; + memset(p, 0xff, i); + rbsp->pos += i * 8; +} + +static void nal_hevc_read_filler_data(struct rbsp *rbsp) +{ + u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8); + + while (*p == 0xff) { + if (DIV_ROUND_UP(rbsp->pos, 8) > rbsp->size) { + rbsp->error = -EINVAL; + return; + } + + p++; + rbsp->pos += 8; + } +} + +static void nal_hevc_rbsp_profile_tier_level(struct rbsp *rbsp, + struct nal_hevc_profile_tier_level *ptl) +{ + unsigned int i; + unsigned int max_num_sub_layers_minus_1 = 0; + + rbsp_bits(rbsp, 2, &ptl->general_profile_space); + rbsp_bit(rbsp, &ptl->general_tier_flag); + rbsp_bits(rbsp, 5, &ptl->general_profile_idc); + for (i = 0; i < 32; i++) + rbsp_bit(rbsp, &ptl->general_profile_compatibility_flag[i]); + rbsp_bit(rbsp, &ptl->general_progressive_source_flag); + rbsp_bit(rbsp, &ptl->general_interlaced_source_flag); + rbsp_bit(rbsp, &ptl->general_non_packed_constraint_flag); + rbsp_bit(rbsp, &ptl->general_frame_only_constraint_flag); + if (ptl->general_profile_idc == 4 || + ptl->general_profile_compatibility_flag[4] || + ptl->general_profile_idc == 5 || + ptl->general_profile_compatibility_flag[5] || + ptl->general_profile_idc == 6 || + ptl->general_profile_compatibility_flag[6] || + ptl->general_profile_idc == 7 || + ptl->general_profile_compatibility_flag[7] || + ptl->general_profile_idc == 8 || + ptl->general_profile_compatibility_flag[8] || + ptl->general_profile_idc == 9 || + ptl->general_profile_compatibility_flag[9] || + ptl->general_profile_idc == 10 || + ptl->general_profile_compatibility_flag[10]) { + rbsp_bit(rbsp, &ptl->general_max_12bit_constraint_flag); + rbsp_bit(rbsp, &ptl->general_max_10bit_constraint_flag); + rbsp_bit(rbsp, &ptl->general_max_8bit_constraint_flag); + rbsp_bit(rbsp, &ptl->general_max_422chroma_constraint_flag); + rbsp_bit(rbsp, &ptl->general_max_420chroma_constraint_flag); + rbsp_bit(rbsp, &ptl->general_max_monochrome_constraint_flag); + rbsp_bit(rbsp, &ptl->general_intra_constraint_flag); + rbsp_bit(rbsp, &ptl->general_one_picture_only_constraint_flag); + rbsp_bit(rbsp, &ptl->general_lower_bit_rate_constraint_flag); + if (ptl->general_profile_idc == 5 || + ptl->general_profile_compatibility_flag[5] || + ptl->general_profile_idc == 9 || + ptl->general_profile_compatibility_flag[9] || + ptl->general_profile_idc == 10 || + ptl->general_profile_compatibility_flag[10]) { + rbsp_bit(rbsp, &ptl->general_max_14bit_constraint_flag); + rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_33bits); + rbsp_bits(rbsp, 33 - 32, &ptl->general_reserved_zero_33bits); + } else { + rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_34bits); + rbsp_bits(rbsp, 34 - 2, &ptl->general_reserved_zero_34bits); + } + } else if (ptl->general_profile_idc == 2 || + ptl->general_profile_compatibility_flag[2]) { + rbsp_bits(rbsp, 7, &ptl->general_reserved_zero_7bits); + rbsp_bit(rbsp, &ptl->general_one_picture_only_constraint_flag); + rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_35bits); + rbsp_bits(rbsp, 35 - 32, &ptl->general_reserved_zero_35bits); + } else { + rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_43bits); + rbsp_bits(rbsp, 43 - 32, &ptl->general_reserved_zero_43bits); + } + if ((ptl->general_profile_idc >= 1 && ptl->general_profile_idc <= 5) || + ptl->general_profile_idc == 9 || + ptl->general_profile_compatibility_flag[1] || + ptl->general_profile_compatibility_flag[2] || + ptl->general_profile_compatibility_flag[3] || + ptl->general_profile_compatibility_flag[4] || + ptl->general_profile_compatibility_flag[5] || + ptl->general_profile_compatibility_flag[9]) + rbsp_bit(rbsp, &ptl->general_inbld_flag); + else + rbsp_bit(rbsp, &ptl->general_reserved_zero_bit); + rbsp_bits(rbsp, 8, &ptl->general_level_idc); + if (max_num_sub_layers_minus_1 > 0) + rbsp_unsupported(rbsp); +} + +static void nal_hevc_rbsp_vps(struct rbsp *rbsp, struct nal_hevc_vps *vps) +{ + unsigned int i, j; + unsigned int reserved_0xffff_16bits = 0xffff; + + rbsp_bits(rbsp, 4, &vps->video_parameter_set_id); + rbsp_bit(rbsp, &vps->base_layer_internal_flag); + rbsp_bit(rbsp, &vps->base_layer_available_flag); + rbsp_bits(rbsp, 6, &vps->max_layers_minus1); + rbsp_bits(rbsp, 3, &vps->max_sub_layers_minus1); + rbsp_bits(rbsp, 1, &vps->temporal_id_nesting_flag); + rbsp_bits(rbsp, 16, &reserved_0xffff_16bits); + nal_hevc_rbsp_profile_tier_level(rbsp, &vps->profile_tier_level); + rbsp_bit(rbsp, &vps->sub_layer_ordering_info_present_flag); + for (i = vps->sub_layer_ordering_info_present_flag ? 0 : vps->max_sub_layers_minus1; + i <= vps->max_sub_layers_minus1; i++) { + rbsp_uev(rbsp, &vps->max_dec_pic_buffering_minus1[i]); + rbsp_uev(rbsp, &vps->max_num_reorder_pics[i]); + rbsp_uev(rbsp, &vps->max_latency_increase_plus1[i]); + } + rbsp_bits(rbsp, 6, &vps->max_layer_id); + rbsp_uev(rbsp, &vps->num_layer_sets_minus1); + for (i = 0; i <= vps->num_layer_sets_minus1; i++) + for (j = 0; j <= vps->max_layer_id; j++) + rbsp_bit(rbsp, &vps->layer_id_included_flag[i][j]); + rbsp_bit(rbsp, &vps->timing_info_present_flag); + if (vps->timing_info_present_flag) + rbsp_unsupported(rbsp); + rbsp_bit(rbsp, &vps->extension_flag); + if (vps->extension_flag) + rbsp_unsupported(rbsp); +} + +static void nal_hevc_rbsp_sps(struct rbsp *rbsp, struct nal_hevc_sps *sps) +{ + unsigned int i; + + rbsp_bits(rbsp, 4, &sps->video_parameter_set_id); + rbsp_bits(rbsp, 3, &sps->max_sub_layers_minus1); + rbsp_bit(rbsp, &sps->temporal_id_nesting_flag); + nal_hevc_rbsp_profile_tier_level(rbsp, &sps->profile_tier_level); + rbsp_uev(rbsp, &sps->seq_parameter_set_id); + + rbsp_uev(rbsp, &sps->chroma_format_idc); + if (sps->chroma_format_idc == 3) + rbsp_bit(rbsp, &sps->separate_colour_plane_flag); + rbsp_uev(rbsp, &sps->pic_width_in_luma_samples); + rbsp_uev(rbsp, &sps->pic_height_in_luma_samples); + rbsp_bit(rbsp, &sps->conformance_window_flag); + if (sps->conformance_window_flag) { + rbsp_uev(rbsp, &sps->conf_win_left_offset); + rbsp_uev(rbsp, &sps->conf_win_right_offset); + rbsp_uev(rbsp, &sps->conf_win_top_offset); + rbsp_uev(rbsp, &sps->conf_win_bottom_offset); + } + rbsp_uev(rbsp, &sps->bit_depth_luma_minus8); + rbsp_uev(rbsp, &sps->bit_depth_chroma_minus8); + + rbsp_uev(rbsp, &sps->log2_max_pic_order_cnt_lsb_minus4); + + rbsp_bit(rbsp, &sps->sub_layer_ordering_info_present_flag); + for (i = (sps->sub_layer_ordering_info_present_flag ? 0 : sps->max_sub_layers_minus1); + i <= sps->max_sub_layers_minus1; i++) { + rbsp_uev(rbsp, &sps->max_dec_pic_buffering_minus1[i]); + rbsp_uev(rbsp, &sps->max_num_reorder_pics[i]); + rbsp_uev(rbsp, &sps->max_latency_increase_plus1[i]); + } + rbsp_uev(rbsp, &sps->log2_min_luma_coding_block_size_minus3); + rbsp_uev(rbsp, &sps->log2_diff_max_min_luma_coding_block_size); + rbsp_uev(rbsp, &sps->log2_min_luma_transform_block_size_minus2); + rbsp_uev(rbsp, &sps->log2_diff_max_min_luma_transform_block_size); + rbsp_uev(rbsp, &sps->max_transform_hierarchy_depth_inter); + rbsp_uev(rbsp, &sps->max_transform_hierarchy_depth_intra); + + rbsp_bit(rbsp, &sps->scaling_list_enabled_flag); + if (sps->scaling_list_enabled_flag) + rbsp_unsupported(rbsp); + + rbsp_bit(rbsp, &sps->amp_enabled_flag); + rbsp_bit(rbsp, &sps->sample_adaptive_offset_enabled_flag); + rbsp_bit(rbsp, &sps->pcm_enabled_flag); + if (sps->pcm_enabled_flag) { + rbsp_bits(rbsp, 4, &sps->pcm_sample_bit_depth_luma_minus1); + rbsp_bits(rbsp, 4, &sps->pcm_sample_bit_depth_chroma_minus1); + rbsp_uev(rbsp, &sps->log2_min_pcm_luma_coding_block_size_minus3); + rbsp_uev(rbsp, &sps->log2_diff_max_min_pcm_luma_coding_block_size); + rbsp_bit(rbsp, &sps->pcm_loop_filter_disabled_flag); + } + + rbsp_uev(rbsp, &sps->num_short_term_ref_pic_sets); + if (sps->num_short_term_ref_pic_sets > 0) + rbsp_unsupported(rbsp); + + rbsp_bit(rbsp, &sps->long_term_ref_pics_present_flag); + if (sps->long_term_ref_pics_present_flag) + rbsp_unsupported(rbsp); + + rbsp_bit(rbsp, &sps->sps_temporal_mvp_enabled_flag); + rbsp_bit(rbsp, &sps->strong_intra_smoothing_enabled_flag); + rbsp_bit(rbsp, &sps->vui_parameters_present_flag); + if (sps->vui_parameters_present_flag) + rbsp_unsupported(rbsp); + + rbsp_bit(rbsp, &sps->extension_present_flag); + if (sps->extension_present_flag) { + rbsp_bit(rbsp, &sps->sps_range_extension_flag); + rbsp_bit(rbsp, &sps->sps_multilayer_extension_flag); + rbsp_bit(rbsp, &sps->sps_3d_extension_flag); + rbsp_bit(rbsp, &sps->sps_scc_extension_flag); + rbsp_bits(rbsp, 5, &sps->sps_extension_4bits); + } + if (sps->sps_range_extension_flag) + rbsp_unsupported(rbsp); + if (sps->sps_multilayer_extension_flag) + rbsp_unsupported(rbsp); + if (sps->sps_3d_extension_flag) + rbsp_unsupported(rbsp); + if (sps->sps_scc_extension_flag) + rbsp_unsupported(rbsp); + if (sps->sps_extension_4bits) + rbsp_unsupported(rbsp); +} + +static void nal_hevc_rbsp_pps(struct rbsp *rbsp, struct nal_hevc_pps *pps) +{ + unsigned int i; + + rbsp_uev(rbsp, &pps->pps_pic_parameter_set_id); + rbsp_uev(rbsp, &pps->pps_seq_parameter_set_id); + rbsp_bit(rbsp, &pps->dependent_slice_segments_enabled_flag); + rbsp_bit(rbsp, &pps->output_flag_present_flag); + rbsp_bits(rbsp, 3, &pps->num_extra_slice_header_bits); + rbsp_bit(rbsp, &pps->sign_data_hiding_enabled_flag); + rbsp_bit(rbsp, &pps->cabac_init_present_flag); + rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1); + rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1); + rbsp_sev(rbsp, &pps->init_qp_minus26); + rbsp_bit(rbsp, &pps->constrained_intra_pred_flag); + rbsp_bit(rbsp, &pps->transform_skip_enabled_flag); + rbsp_bit(rbsp, &pps->cu_qp_delta_enabled_flag); + if (pps->cu_qp_delta_enabled_flag) + rbsp_uev(rbsp, &pps->diff_cu_qp_delta_depth); + rbsp_sev(rbsp, &pps->pps_cb_qp_offset); + rbsp_sev(rbsp, &pps->pps_cr_qp_offset); + rbsp_bit(rbsp, &pps->pps_slice_chroma_qp_offsets_present_flag); + rbsp_bit(rbsp, &pps->weighted_pred_flag); + rbsp_bit(rbsp, &pps->weighted_bipred_flag); + rbsp_bit(rbsp, &pps->transquant_bypass_enabled_flag); + rbsp_bit(rbsp, &pps->tiles_enabled_flag); + rbsp_bit(rbsp, &pps->entropy_coding_sync_enabled_flag); + if (pps->tiles_enabled_flag) { + rbsp_uev(rbsp, &pps->num_tile_columns_minus1); + rbsp_uev(rbsp, &pps->num_tile_rows_minus1); + rbsp_bit(rbsp, &pps->uniform_spacing_flag); + if (!pps->uniform_spacing_flag) { + for (i = 0; i < pps->num_tile_columns_minus1; i++) + rbsp_uev(rbsp, &pps->column_width_minus1[i]); + for (i = 0; i < pps->num_tile_rows_minus1; i++) + rbsp_uev(rbsp, &pps->row_height_minus1[i]); + } + rbsp_bit(rbsp, &pps->loop_filter_across_tiles_enabled_flag); + } + rbsp_bit(rbsp, &pps->pps_loop_filter_across_slices_enabled_flag); + rbsp_bit(rbsp, &pps->deblocking_filter_control_present_flag); + if (pps->deblocking_filter_control_present_flag) { + rbsp_bit(rbsp, &pps->deblocking_filter_override_enabled_flag); + rbsp_bit(rbsp, &pps->pps_deblocking_filter_disabled_flag); + if (!pps->pps_deblocking_filter_disabled_flag) { + rbsp_sev(rbsp, &pps->pps_beta_offset_div2); + rbsp_sev(rbsp, &pps->pps_tc_offset_div2); + } + } + rbsp_bit(rbsp, &pps->pps_scaling_list_data_present_flag); + if (pps->pps_scaling_list_data_present_flag) + rbsp_unsupported(rbsp); + rbsp_bit(rbsp, &pps->lists_modification_present_flag); + rbsp_uev(rbsp, &pps->log2_parallel_merge_level_minus2); + rbsp_bit(rbsp, &pps->slice_segment_header_extension_present_flag); + rbsp_bit(rbsp, &pps->pps_extension_present_flag); + if (pps->pps_extension_present_flag) { + rbsp_bit(rbsp, &pps->pps_range_extension_flag); + rbsp_bit(rbsp, &pps->pps_multilayer_extension_flag); + rbsp_bit(rbsp, &pps->pps_3d_extension_flag); + rbsp_bit(rbsp, &pps->pps_scc_extension_flag); + rbsp_bits(rbsp, 4, &pps->pps_extension_4bits); + } + if (pps->pps_range_extension_flag) + rbsp_unsupported(rbsp); + if (pps->pps_multilayer_extension_flag) + rbsp_unsupported(rbsp); + if (pps->pps_3d_extension_flag) + rbsp_unsupported(rbsp); + if (pps->pps_scc_extension_flag) + rbsp_unsupported(rbsp); + if (pps->pps_extension_4bits) + rbsp_unsupported(rbsp); +} + +/** + * nal_hevc_write_vps() - Write PPS NAL unit into RBSP format + * @dev: device pointer + * @dest: the buffer that is filled with RBSP data + * @n: maximum size of @dest in bytes + * @vps: &struct nal_hevc_vps to convert to RBSP + * + * Convert @vps to RBSP data and write it into @dest. + * + * The size of the VPS NAL unit is not known in advance and this function will + * fail, if @dest does not hold sufficient space for the VPS NAL unit. + * + * Return: number of bytes written to @dest or negative error code + */ +ssize_t nal_hevc_write_vps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_vps *vps) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit = 0; + unsigned int nal_unit_type = VPS_NUT; + unsigned int nuh_layer_id = 0; + unsigned int nuh_temporal_id_plus1 = 1; + + if (!dest) + return -EINVAL; + + rbsp_init(&rbsp, dest, n, &write); + + nal_hevc_write_start_code_prefix(&rbsp); + + /* NAL unit header */ + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + nal_hevc_rbsp_vps(&rbsp, vps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_write_vps); + +/** + * nal_hevc_read_vps() - Read VPS NAL unit from RBSP format + * @dev: device pointer + * @vps: the &struct nal_hevc_vps to fill from the RBSP data + * @src: the buffer that contains the RBSP data + * @n: size of @src in bytes + * + * Read RBSP data from @src and use it to fill @vps. + * + * Return: number of bytes read from @src or negative error code + */ +ssize_t nal_hevc_read_vps(const struct device *dev, + struct nal_hevc_vps *vps, void *src, size_t n) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit; + unsigned int nal_unit_type; + unsigned int nuh_layer_id; + unsigned int nuh_temporal_id_plus1; + + if (!src) + return -EINVAL; + + rbsp_init(&rbsp, src, n, &read); + + nal_hevc_read_start_code_prefix(&rbsp); + + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + if (rbsp.error || + forbidden_zero_bit != 0 || + nal_unit_type != VPS_NUT) + return -EINVAL; + + nal_hevc_rbsp_vps(&rbsp, vps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_read_vps); + +/** + * nal_hevc_write_sps() - Write SPS NAL unit into RBSP format + * @dev: device pointer + * @dest: the buffer that is filled with RBSP data + * @n: maximum size of @dest in bytes + * @sps: &struct nal_hevc_sps to convert to RBSP + * + * Convert @sps to RBSP data and write it into @dest. + * + * The size of the SPS NAL unit is not known in advance and this function will + * fail, if @dest does not hold sufficient space for the SPS NAL unit. + * + * Return: number of bytes written to @dest or negative error code + */ +ssize_t nal_hevc_write_sps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_sps *sps) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit = 0; + unsigned int nal_unit_type = SPS_NUT; + unsigned int nuh_layer_id = 0; + unsigned int nuh_temporal_id_plus1 = 1; + + if (!dest) + return -EINVAL; + + rbsp_init(&rbsp, dest, n, &write); + + nal_hevc_write_start_code_prefix(&rbsp); + + /* NAL unit header */ + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + nal_hevc_rbsp_sps(&rbsp, sps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_write_sps); + +/** + * nal_hevc_read_sps() - Read SPS NAL unit from RBSP format + * @dev: device pointer + * @sps: the &struct nal_hevc_sps to fill from the RBSP data + * @src: the buffer that contains the RBSP data + * @n: size of @src in bytes + * + * Read RBSP data from @src and use it to fill @sps. + * + * Return: number of bytes read from @src or negative error code + */ +ssize_t nal_hevc_read_sps(const struct device *dev, + struct nal_hevc_sps *sps, void *src, size_t n) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit; + unsigned int nal_unit_type; + unsigned int nuh_layer_id; + unsigned int nuh_temporal_id_plus1; + + if (!src) + return -EINVAL; + + rbsp_init(&rbsp, src, n, &read); + + nal_hevc_read_start_code_prefix(&rbsp); + + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + if (rbsp.error || + forbidden_zero_bit != 0 || + nal_unit_type != SPS_NUT) + return -EINVAL; + + nal_hevc_rbsp_sps(&rbsp, sps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_read_sps); + +/** + * nal_hevc_write_pps() - Write PPS NAL unit into RBSP format + * @dev: device pointer + * @dest: the buffer that is filled with RBSP data + * @n: maximum size of @dest in bytes + * @pps: &struct nal_hevc_pps to convert to RBSP + * + * Convert @pps to RBSP data and write it into @dest. + * + * The size of the PPS NAL unit is not known in advance and this function will + * fail, if @dest does not hold sufficient space for the PPS NAL unit. + * + * Return: number of bytes written to @dest or negative error code + */ +ssize_t nal_hevc_write_pps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_pps *pps) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit = 0; + unsigned int nal_unit_type = PPS_NUT; + unsigned int nuh_layer_id = 0; + unsigned int nuh_temporal_id_plus1 = 1; + + if (!dest) + return -EINVAL; + + rbsp_init(&rbsp, dest, n, &write); + + nal_hevc_write_start_code_prefix(&rbsp); + + /* NAL unit header */ + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + nal_hevc_rbsp_pps(&rbsp, pps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_write_pps); + +/** + * nal_hevc_read_pps() - Read PPS NAL unit from RBSP format + * @dev: device pointer + * @pps: the &struct nal_hevc_pps to fill from the RBSP data + * @src: the buffer that contains the RBSP data + * @n: size of @src in bytes + * + * Read RBSP data from @src and use it to fill @pps. + * + * Return: number of bytes read from @src or negative error code + */ +ssize_t nal_hevc_read_pps(const struct device *dev, + struct nal_hevc_pps *pps, void *src, size_t n) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit; + unsigned int nal_unit_type; + unsigned int nuh_layer_id; + unsigned int nuh_temporal_id_plus1; + + if (!src) + return -EINVAL; + + rbsp_init(&rbsp, src, n, &read); + + nal_hevc_read_start_code_prefix(&rbsp); + + /* NAL unit header */ + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + nal_hevc_rbsp_pps(&rbsp, pps); + + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_read_pps); + +/** + * nal_hevc_write_filler() - Write filler data RBSP + * @dev: device pointer + * @dest: buffer to fill with filler data + * @n: size of the buffer to fill with filler data + * + * Write a filler data RBSP to @dest with a size of @n bytes and return the + * number of written filler data bytes. + * + * Use this function to generate dummy data in an RBSP data stream that can be + * safely ignored by hevc decoders. + * + * The RBSP format of the filler data is specified in Rec. ITU-T H.265 + * (02/2018) 7.3.2.8 Filler data RBSP syntax. + * + * Return: number of filler data bytes (including marker) or negative error + */ +ssize_t nal_hevc_write_filler(const struct device *dev, void *dest, size_t n) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit = 0; + unsigned int nal_unit_type = FD_NUT; + unsigned int nuh_layer_id = 0; + unsigned int nuh_temporal_id_plus1 = 1; + + if (!dest) + return -EINVAL; + + rbsp_init(&rbsp, dest, n, &write); + + nal_hevc_write_start_code_prefix(&rbsp); + + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + nal_hevc_write_filler_data(&rbsp); + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_write_filler); + +/** + * nal_hevc_read_filler() - Read filler data RBSP + * @dev: device pointer + * @src: buffer with RBSP data that is read + * @n: maximum size of src that shall be read + * + * Read a filler data RBSP from @src up to a maximum size of @n bytes and + * return the size of the filler data in bytes including the marker. + * + * This function is used to parse filler data and skip the respective bytes in + * the RBSP data. + * + * The RBSP format of the filler data is specified in Rec. ITU-T H.265 + * (02/2018) 7.3.2.8 Filler data RBSP syntax. + * + * Return: number of filler data bytes (including marker) or negative error + */ +ssize_t nal_hevc_read_filler(const struct device *dev, void *src, size_t n) +{ + struct rbsp rbsp; + unsigned int forbidden_zero_bit; + unsigned int nal_unit_type; + unsigned int nuh_layer_id; + unsigned int nuh_temporal_id_plus1; + + if (!src) + return -EINVAL; + + rbsp_init(&rbsp, src, n, &read); + + nal_hevc_read_start_code_prefix(&rbsp); + + rbsp_bit(&rbsp, &forbidden_zero_bit); + rbsp_bits(&rbsp, 6, &nal_unit_type); + rbsp_bits(&rbsp, 6, &nuh_layer_id); + rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1); + + if (rbsp.error) + return rbsp.error; + if (forbidden_zero_bit != 0 || + nal_unit_type != FD_NUT) + return -EINVAL; + + nal_hevc_read_filler_data(&rbsp); + rbsp_trailing_bits(&rbsp); + + if (rbsp.error) + return rbsp.error; + + return DIV_ROUND_UP(rbsp.pos, 8); +} +EXPORT_SYMBOL_GPL(nal_hevc_read_filler); diff --git a/drivers/media/platform/allegro-dvt/nal-hevc.h b/drivers/media/platform/allegro-dvt/nal-hevc.h new file mode 100644 index 000000000000..fc994d4242d8 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/nal-hevc.h @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de> + * + * Convert NAL units between raw byte sequence payloads (RBSP) and C structs. + */ + +#ifndef __NAL_HEVC_H__ +#define __NAL_HEVC_H__ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <media/v4l2-ctrls.h> + +struct nal_hevc_profile_tier_level { + unsigned int general_profile_space; + unsigned int general_tier_flag; + unsigned int general_profile_idc; + unsigned int general_profile_compatibility_flag[32]; + unsigned int general_progressive_source_flag; + unsigned int general_interlaced_source_flag; + unsigned int general_non_packed_constraint_flag; + unsigned int general_frame_only_constraint_flag; + union { + struct { + unsigned int general_max_12bit_constraint_flag; + unsigned int general_max_10bit_constraint_flag; + unsigned int general_max_8bit_constraint_flag; + unsigned int general_max_422chroma_constraint_flag; + unsigned int general_max_420chroma_constraint_flag; + unsigned int general_max_monochrome_constraint_flag; + unsigned int general_intra_constraint_flag; + unsigned int general_one_picture_only_constraint_flag; + unsigned int general_lower_bit_rate_constraint_flag; + union { + struct { + unsigned int general_max_14bit_constraint_flag; + unsigned int general_reserved_zero_33bits; + }; + unsigned int general_reserved_zero_34bits; + }; + }; + struct { + unsigned int general_reserved_zero_7bits; + /* unsigned int general_one_picture_only_constraint_flag; */ + unsigned int general_reserved_zero_35bits; + }; + unsigned int general_reserved_zero_43bits; + }; + union { + unsigned int general_inbld_flag; + unsigned int general_reserved_zero_bit; + }; + unsigned int general_level_idc; +}; + +/** + * struct nal_hevc_vps - Video parameter set + * + * C struct representation of the video parameter set NAL unit as defined by + * Rec. ITU-T H.265 (02/2018) 7.3.2.1 Video parameter set RBSP syntax + */ +struct nal_hevc_vps { + unsigned int video_parameter_set_id; + unsigned int base_layer_internal_flag; + unsigned int base_layer_available_flag; + unsigned int max_layers_minus1; + unsigned int max_sub_layers_minus1; + unsigned int temporal_id_nesting_flag; + struct nal_hevc_profile_tier_level profile_tier_level; + unsigned int sub_layer_ordering_info_present_flag; + struct { + unsigned int max_dec_pic_buffering_minus1[7]; + unsigned int max_num_reorder_pics[7]; + unsigned int max_latency_increase_plus1[7]; + }; + unsigned int max_layer_id; + unsigned int num_layer_sets_minus1; + unsigned int layer_id_included_flag[1024][64]; + unsigned int timing_info_present_flag; + struct { + unsigned int num_units_in_tick; + unsigned int time_scale; + unsigned int poc_proportional_to_timing_flag; + unsigned int num_ticks_poc_diff_one_minus1; + unsigned int num_hrd_parameters; + struct { + unsigned int hrd_layer_set_idx[0]; + unsigned int cprms_present_flag[0]; + }; + /* hrd_parameters( cprms_present_flag[ i ], max_sub_layers_minus1 ) */ + }; + unsigned int extension_flag; + unsigned int extension_data_flag; +}; + +struct nal_hevc_sub_layer_hrd_parameters { + unsigned int bit_rate_value_minus1[1]; + unsigned int cpb_size_value_minus1[1]; + unsigned int cbr_flag[1]; +}; + +struct nal_hevc_hrd_parameters { + unsigned int nal_hrd_parameters_present_flag; + unsigned int vcl_hrd_parameters_present_flag; + struct { + unsigned int sub_pic_hrd_params_present_flag; + struct { + unsigned int tick_divisor_minus2; + unsigned int du_cpb_removal_delay_increment_length_minus1; + unsigned int sub_pic_cpb_params_in_pic_timing_sei_flag; + unsigned int dpb_output_delay_du_length_minus1; + }; + unsigned int bit_rate_scale; + unsigned int cpb_size_scale; + unsigned int cpb_size_du_scale; + unsigned int initial_cpb_removal_delay_length_minus1; + unsigned int au_cpb_removal_delay_length_minus1; + unsigned int dpb_output_delay_length_minus1; + }; + struct { + unsigned int fixed_pic_rate_general_flag[1]; + unsigned int fixed_pic_rate_within_cvs_flag[1]; + unsigned int elemental_duration_in_tc_minus1[1]; + unsigned int low_delay_hrd_flag[1]; + unsigned int cpb_cnt_minus1[1]; + struct nal_hevc_sub_layer_hrd_parameters nal_hrd[1]; + struct nal_hevc_sub_layer_hrd_parameters vcl_hrd[1]; + }; +}; + +/** + * struct nal_hevc_vui_parameters - VUI parameters + * + * C struct representation of the VUI parameters as defined by Rec. ITU-T + * H.265 (02/2018) E.2.1 VUI parameters syntax. + */ +struct nal_hevc_vui_parameters { + unsigned int aspect_ratio_info_present_flag; + struct { + unsigned int aspect_ratio_idc; + unsigned int sar_width; + unsigned int sar_height; + }; + unsigned int overscan_info_present_flag; + unsigned int overscan_appropriate_flag; + unsigned int video_signal_type_present_flag; + struct { + unsigned int video_format; + unsigned int video_full_range_flag; + unsigned int colour_description_present_flag; + struct { + unsigned int colour_primaries; + unsigned int transfer_characteristics; + unsigned int matrix_coeffs; + }; + }; + unsigned int chroma_loc_info_present_flag; + struct { + unsigned int chroma_sample_loc_type_top_field; + unsigned int chroma_sample_loc_type_bottom_field; + }; + unsigned int neutral_chroma_indication_flag; + unsigned int field_seq_flag; + unsigned int frame_field_info_present_flag; + unsigned int default_display_window_flag; + struct { + unsigned int def_disp_win_left_offset; + unsigned int def_disp_win_right_offset; + unsigned int def_disp_win_top_offset; + unsigned int def_disp_win_bottom_offset; + }; + unsigned int vui_timing_info_present_flag; + struct { + unsigned int vui_num_units_in_tick; + unsigned int vui_time_scale; + unsigned int vui_poc_proportional_to_timing_flag; + unsigned int vui_num_ticks_poc_diff_one_minus1; + unsigned int vui_hrd_parameters_present_flag; + struct nal_hevc_hrd_parameters nal_hrd_parameters; + }; + unsigned int bitstream_restriction_flag; + struct { + unsigned int tiles_fixed_structure_flag; + unsigned int motion_vectors_over_pic_boundaries_flag; + unsigned int restricted_ref_pic_lists_flag; + unsigned int min_spatial_segmentation_idc; + unsigned int max_bytes_per_pic_denom; + unsigned int max_bits_per_min_cu_denom; + unsigned int log2_max_mv_length_horizontal; + unsigned int log2_max_mv_length_vertical; + }; +}; + +/** + * struct nal_hevc_sps - Sequence parameter set + * + * C struct representation of the video parameter set NAL unit as defined by + * Rec. ITU-T H.265 (02/2018) 7.3.2.2 Sequence parameter set RBSP syntax + */ +struct nal_hevc_sps { + unsigned int video_parameter_set_id; + unsigned int max_sub_layers_minus1; + unsigned int temporal_id_nesting_flag; + struct nal_hevc_profile_tier_level profile_tier_level; + unsigned int seq_parameter_set_id; + unsigned int chroma_format_idc; + unsigned int separate_colour_plane_flag; + unsigned int pic_width_in_luma_samples; + unsigned int pic_height_in_luma_samples; + unsigned int conformance_window_flag; + struct { + unsigned int conf_win_left_offset; + unsigned int conf_win_right_offset; + unsigned int conf_win_top_offset; + unsigned int conf_win_bottom_offset; + }; + + unsigned int bit_depth_luma_minus8; + unsigned int bit_depth_chroma_minus8; + unsigned int log2_max_pic_order_cnt_lsb_minus4; + unsigned int sub_layer_ordering_info_present_flag; + struct { + unsigned int max_dec_pic_buffering_minus1[7]; + unsigned int max_num_reorder_pics[7]; + unsigned int max_latency_increase_plus1[7]; + }; + unsigned int log2_min_luma_coding_block_size_minus3; + unsigned int log2_diff_max_min_luma_coding_block_size; + unsigned int log2_min_luma_transform_block_size_minus2; + unsigned int log2_diff_max_min_luma_transform_block_size; + unsigned int max_transform_hierarchy_depth_inter; + unsigned int max_transform_hierarchy_depth_intra; + + unsigned int scaling_list_enabled_flag; + unsigned int scaling_list_data_present_flag; + unsigned int amp_enabled_flag; + unsigned int sample_adaptive_offset_enabled_flag; + unsigned int pcm_enabled_flag; + struct { + unsigned int pcm_sample_bit_depth_luma_minus1; + unsigned int pcm_sample_bit_depth_chroma_minus1; + unsigned int log2_min_pcm_luma_coding_block_size_minus3; + unsigned int log2_diff_max_min_pcm_luma_coding_block_size; + unsigned int pcm_loop_filter_disabled_flag; + }; + + unsigned int num_short_term_ref_pic_sets; + unsigned int long_term_ref_pics_present_flag; + unsigned int sps_temporal_mvp_enabled_flag; + unsigned int strong_intra_smoothing_enabled_flag; + unsigned int vui_parameters_present_flag; + struct nal_hevc_vui_parameters vui; + unsigned int extension_present_flag; + struct { + unsigned int sps_range_extension_flag; + unsigned int sps_multilayer_extension_flag; + unsigned int sps_3d_extension_flag; + unsigned int sps_scc_extension_flag; + unsigned int sps_extension_4bits; + }; +}; + +struct nal_hevc_pps { + unsigned int pps_pic_parameter_set_id; + unsigned int pps_seq_parameter_set_id; + unsigned int dependent_slice_segments_enabled_flag; + unsigned int output_flag_present_flag; + unsigned int num_extra_slice_header_bits; + unsigned int sign_data_hiding_enabled_flag; + unsigned int cabac_init_present_flag; + unsigned int num_ref_idx_l0_default_active_minus1; + unsigned int num_ref_idx_l1_default_active_minus1; + int init_qp_minus26; + unsigned int constrained_intra_pred_flag; + unsigned int transform_skip_enabled_flag; + unsigned int cu_qp_delta_enabled_flag; + unsigned int diff_cu_qp_delta_depth; + int pps_cb_qp_offset; + int pps_cr_qp_offset; + unsigned int pps_slice_chroma_qp_offsets_present_flag; + unsigned int weighted_pred_flag; + unsigned int weighted_bipred_flag; + unsigned int transquant_bypass_enabled_flag; + unsigned int tiles_enabled_flag; + unsigned int entropy_coding_sync_enabled_flag; + struct { + unsigned int num_tile_columns_minus1; + unsigned int num_tile_rows_minus1; + unsigned int uniform_spacing_flag; + struct { + unsigned int column_width_minus1[1]; + unsigned int row_height_minus1[1]; + }; + unsigned int loop_filter_across_tiles_enabled_flag; + }; + unsigned int pps_loop_filter_across_slices_enabled_flag; + unsigned int deblocking_filter_control_present_flag; + struct { + unsigned int deblocking_filter_override_enabled_flag; + unsigned int pps_deblocking_filter_disabled_flag; + struct { + int pps_beta_offset_div2; + int pps_tc_offset_div2; + }; + }; + unsigned int pps_scaling_list_data_present_flag; + unsigned int lists_modification_present_flag; + unsigned int log2_parallel_merge_level_minus2; + unsigned int slice_segment_header_extension_present_flag; + unsigned int pps_extension_present_flag; + struct { + unsigned int pps_range_extension_flag; + unsigned int pps_multilayer_extension_flag; + unsigned int pps_3d_extension_flag; + unsigned int pps_scc_extension_flag; + unsigned int pps_extension_4bits; + }; +}; + +int nal_hevc_profile_from_v4l2(enum v4l2_mpeg_video_hevc_profile profile); +int nal_hevc_tier_from_v4l2(enum v4l2_mpeg_video_hevc_tier tier); +int nal_hevc_level_from_v4l2(enum v4l2_mpeg_video_hevc_level level); + +int nal_range_from_v4l2(enum v4l2_quantization quantization); +int nal_color_primaries_from_v4l2(enum v4l2_colorspace colorspace); +int nal_transfer_characteristics_from_v4l2(enum v4l2_colorspace colorspace, + enum v4l2_xfer_func xfer_func); +int nal_matrix_coeffs_from_v4l2(enum v4l2_colorspace colorspace, + enum v4l2_ycbcr_encoding ycbcr_encoding); + +ssize_t nal_hevc_write_vps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_vps *vps); +ssize_t nal_hevc_read_vps(const struct device *dev, + struct nal_hevc_vps *vps, void *src, size_t n); + +ssize_t nal_hevc_write_sps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_sps *sps); +ssize_t nal_hevc_read_sps(const struct device *dev, + struct nal_hevc_sps *sps, void *src, size_t n); + +ssize_t nal_hevc_write_pps(const struct device *dev, + void *dest, size_t n, struct nal_hevc_pps *pps); +ssize_t nal_hevc_read_pps(const struct device *dev, + struct nal_hevc_pps *pps, void *src, size_t n); + +ssize_t nal_hevc_write_filler(const struct device *dev, void *dest, size_t n); +ssize_t nal_hevc_read_filler(const struct device *dev, void *src, size_t n); + +#endif /* __NAL_HEVC_H__ */ diff --git a/drivers/media/platform/allegro-dvt/nal-rbsp.c b/drivers/media/platform/allegro-dvt/nal-rbsp.c new file mode 100644 index 000000000000..d911322d0efa --- /dev/null +++ b/drivers/media/platform/allegro-dvt/nal-rbsp.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2020 Pengutronix, Michael Tretter <kernel@pengutronix.de> + * + * Helper functions to generate a raw byte sequence payload from values. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/string.h> +#include <linux/v4l2-controls.h> + +#include <linux/device.h> +#include <linux/export.h> +#include <linux/log2.h> + +#include "nal-rbsp.h" + +void rbsp_init(struct rbsp *rbsp, void *addr, size_t size, + struct nal_rbsp_ops *ops) +{ + if (!rbsp) + return; + + rbsp->data = addr; + rbsp->size = size; + rbsp->pos = 0; + rbsp->ops = ops; + rbsp->error = 0; +} + +void rbsp_unsupported(struct rbsp *rbsp) +{ + rbsp->error = -EINVAL; +} + +static int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value); +static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value); + +/* + * When reading or writing, the emulation_prevention_three_byte is detected + * only when the 2 one bits need to be inserted. Therefore, we are not + * actually adding the 0x3 byte, but the 2 one bits and the six 0 bits of the + * next byte. + */ +#define EMULATION_PREVENTION_THREE_BYTE (0x3 << 6) + +static int add_emulation_prevention_three_byte(struct rbsp *rbsp) +{ + rbsp->num_consecutive_zeros = 0; + rbsp_write_bits(rbsp, 8, EMULATION_PREVENTION_THREE_BYTE); + + return 0; +} + +static int discard_emulation_prevention_three_byte(struct rbsp *rbsp) +{ + unsigned int tmp = 0; + + rbsp->num_consecutive_zeros = 0; + rbsp_read_bits(rbsp, 8, &tmp); + if (tmp != EMULATION_PREVENTION_THREE_BYTE) + return -EINVAL; + + return 0; +} + +static inline int rbsp_read_bit(struct rbsp *rbsp) +{ + int shift; + int ofs; + int bit; + int err; + + if (rbsp->num_consecutive_zeros == 22) { + err = discard_emulation_prevention_three_byte(rbsp); + if (err) + return err; + } + + shift = 7 - (rbsp->pos % 8); + ofs = rbsp->pos / 8; + if (ofs >= rbsp->size) + return -EINVAL; + + bit = (rbsp->data[ofs] >> shift) & 1; + + rbsp->pos++; + + if (bit == 1 || + (rbsp->num_consecutive_zeros < 7 && (rbsp->pos % 8 == 0))) + rbsp->num_consecutive_zeros = 0; + else + rbsp->num_consecutive_zeros++; + + return bit; +} + +static inline int rbsp_write_bit(struct rbsp *rbsp, bool value) +{ + int shift; + int ofs; + + if (rbsp->num_consecutive_zeros == 22) + add_emulation_prevention_three_byte(rbsp); + + shift = 7 - (rbsp->pos % 8); + ofs = rbsp->pos / 8; + if (ofs >= rbsp->size) + return -EINVAL; + + rbsp->data[ofs] &= ~(1 << shift); + rbsp->data[ofs] |= value << shift; + + rbsp->pos++; + + if (value || + (rbsp->num_consecutive_zeros < 7 && (rbsp->pos % 8 == 0))) { + rbsp->num_consecutive_zeros = 0; + } else { + rbsp->num_consecutive_zeros++; + } + + return 0; +} + +static inline int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value) +{ + int i; + int bit; + unsigned int tmp = 0; + + if (n > 8 * sizeof(*value)) + return -EINVAL; + + for (i = n; i > 0; i--) { + bit = rbsp_read_bit(rbsp); + if (bit < 0) + return bit; + tmp |= bit << (i - 1); + } + + if (value) + *value = tmp; + + return 0; +} + +static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value) +{ + int ret; + + if (n > 8 * sizeof(value)) + return -EINVAL; + + while (n--) { + ret = rbsp_write_bit(rbsp, (value >> n) & 1); + if (ret) + return ret; + } + + return 0; +} + +static int rbsp_read_uev(struct rbsp *rbsp, unsigned int *value) +{ + int leading_zero_bits = 0; + unsigned int tmp = 0; + int ret; + + while ((ret = rbsp_read_bit(rbsp)) == 0) + leading_zero_bits++; + if (ret < 0) + return ret; + + if (leading_zero_bits > 0) { + ret = rbsp_read_bits(rbsp, leading_zero_bits, &tmp); + if (ret) + return ret; + } + + if (value) + *value = (1 << leading_zero_bits) - 1 + tmp; + + return 0; +} + +static int rbsp_write_uev(struct rbsp *rbsp, unsigned int *value) +{ + int ret; + int leading_zero_bits; + + if (!value) + return -EINVAL; + + leading_zero_bits = ilog2(*value + 1); + + ret = rbsp_write_bits(rbsp, leading_zero_bits, 0); + if (ret) + return ret; + + return rbsp_write_bits(rbsp, leading_zero_bits + 1, *value + 1); +} + +static int rbsp_read_sev(struct rbsp *rbsp, int *value) +{ + int ret; + unsigned int tmp; + + ret = rbsp_read_uev(rbsp, &tmp); + if (ret) + return ret; + + if (value) { + if (tmp & 1) + *value = (tmp + 1) / 2; + else + *value = -(tmp / 2); + } + + return 0; +} + +static int rbsp_write_sev(struct rbsp *rbsp, int *value) +{ + unsigned int tmp; + + if (!value) + return -EINVAL; + + if (*value > 0) + tmp = (2 * (*value)) | 1; + else + tmp = -2 * (*value); + + return rbsp_write_uev(rbsp, &tmp); +} + +static int __rbsp_write_bit(struct rbsp *rbsp, int *value) +{ + return rbsp_write_bit(rbsp, *value); +} + +static int __rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int *value) +{ + return rbsp_write_bits(rbsp, n, *value); +} + +struct nal_rbsp_ops write = { + .rbsp_bit = __rbsp_write_bit, + .rbsp_bits = __rbsp_write_bits, + .rbsp_uev = rbsp_write_uev, + .rbsp_sev = rbsp_write_sev, +}; + +static int __rbsp_read_bit(struct rbsp *rbsp, int *value) +{ + int tmp = rbsp_read_bit(rbsp); + + if (tmp < 0) + return tmp; + *value = tmp; + + return 0; +} + +struct nal_rbsp_ops read = { + .rbsp_bit = __rbsp_read_bit, + .rbsp_bits = rbsp_read_bits, + .rbsp_uev = rbsp_read_uev, + .rbsp_sev = rbsp_read_sev, +}; + +void rbsp_bit(struct rbsp *rbsp, int *value) +{ + if (rbsp->error) + return; + rbsp->error = rbsp->ops->rbsp_bit(rbsp, value); +} + +void rbsp_bits(struct rbsp *rbsp, int n, int *value) +{ + if (rbsp->error) + return; + rbsp->error = rbsp->ops->rbsp_bits(rbsp, n, value); +} + +void rbsp_uev(struct rbsp *rbsp, unsigned int *value) +{ + if (rbsp->error) + return; + rbsp->error = rbsp->ops->rbsp_uev(rbsp, value); +} + +void rbsp_sev(struct rbsp *rbsp, int *value) +{ + if (rbsp->error) + return; + rbsp->error = rbsp->ops->rbsp_sev(rbsp, value); +} + +void rbsp_trailing_bits(struct rbsp *rbsp) +{ + unsigned int rbsp_stop_one_bit = 1; + unsigned int rbsp_alignment_zero_bit = 0; + + rbsp_bit(rbsp, &rbsp_stop_one_bit); + rbsp_bits(rbsp, round_up(rbsp->pos, 8) - rbsp->pos, + &rbsp_alignment_zero_bit); +} diff --git a/drivers/media/platform/allegro-dvt/nal-rbsp.h b/drivers/media/platform/allegro-dvt/nal-rbsp.h new file mode 100644 index 000000000000..c72f49fed8d3 --- /dev/null +++ b/drivers/media/platform/allegro-dvt/nal-rbsp.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019-2020 Pengutronix, Michael Tretter <kernel@pengutronix.de> + */ + +#ifndef __NAL_RBSP_H__ +#define __NAL_RBSP_H__ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct rbsp; + +struct nal_rbsp_ops { + int (*rbsp_bit)(struct rbsp *rbsp, int *val); + int (*rbsp_bits)(struct rbsp *rbsp, int n, unsigned int *val); + int (*rbsp_uev)(struct rbsp *rbsp, unsigned int *val); + int (*rbsp_sev)(struct rbsp *rbsp, int *val); +}; + +/** + * struct rbsp - State object for handling a raw byte sequence payload + * @data: pointer to the data of the rbsp + * @size: maximum size of the data of the rbsp + * @pos: current bit position inside the rbsp + * @num_consecutive_zeros: number of zeros before @pos + * @ops: per datatype functions for interacting with the rbsp + * @error: an error occurred while handling the rbsp + * + * This struct is passed around the various parsing functions and tracks the + * current position within the raw byte sequence payload. + * + * The @ops field allows to separate the operation, i.e., reading/writing a + * value from/to that rbsp, from the structure of the NAL unit. This allows to + * have a single function for iterating the NAL unit, while @ops has function + * pointers for handling each type in the rbsp. + */ +struct rbsp { + u8 *data; + size_t size; + unsigned int pos; + unsigned int num_consecutive_zeros; + struct nal_rbsp_ops *ops; + int error; +}; + +extern struct nal_rbsp_ops write; +extern struct nal_rbsp_ops read; + +void rbsp_init(struct rbsp *rbsp, void *addr, size_t size, + struct nal_rbsp_ops *ops); +void rbsp_unsupported(struct rbsp *rbsp); + +void rbsp_bit(struct rbsp *rbsp, int *value); +void rbsp_bits(struct rbsp *rbsp, int n, int *value); +void rbsp_uev(struct rbsp *rbsp, unsigned int *value); +void rbsp_sev(struct rbsp *rbsp, int *value); + +void rbsp_trailing_bits(struct rbsp *rbsp); + +#endif /* __NAL_RBSP_H__ */ diff --git a/drivers/media/platform/am437x/am437x-vpfe.c b/drivers/media/platform/am437x/am437x-vpfe.c index 0fb9f9ba1219..6cdc77dda0e4 100644 --- a/drivers/media/platform/am437x/am437x-vpfe.c +++ b/drivers/media/platform/am437x/am437x-vpfe.c @@ -2365,7 +2365,7 @@ vpfe_get_pdata(struct vpfe_device *vpfe) pdata->asd[i] = v4l2_async_notifier_add_fwnode_subdev( &vpfe->notifier, of_fwnode_handle(rem), - sizeof(struct v4l2_async_subdev)); + struct v4l2_async_subdev); of_node_put(rem); if (IS_ERR(pdata->asd[i])) goto cleanup; diff --git a/drivers/media/platform/aspeed-video.c b/drivers/media/platform/aspeed-video.c index c46a79eace98..f2c4dadd6a0e 100644 --- a/drivers/media/platform/aspeed-video.c +++ b/drivers/media/platform/aspeed-video.c @@ -1551,12 +1551,12 @@ static int aspeed_video_setup_video(struct aspeed_video *video) V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask, V4L2_JPEG_CHROMA_SUBSAMPLING_444); - if (video->ctrl_handler.error) { + rc = video->ctrl_handler.error; + if (rc) { v4l2_ctrl_handler_free(&video->ctrl_handler); v4l2_device_unregister(v4l2_dev); - dev_err(video->dev, "Failed to init controls: %d\n", - video->ctrl_handler.error); + dev_err(video->dev, "Failed to init controls: %d\n", rc); return rc; } diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 24b784b893d6..fab8eca58d93 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -41,6 +41,7 @@ struct isc_buffer { struct isc_subdev_entity { struct v4l2_subdev *sd; struct v4l2_async_subdev *asd; + struct device_node *epn; struct v4l2_async_notifier notifier; u32 pfe_cfg0; diff --git a/drivers/media/platform/atmel/atmel-isi.c b/drivers/media/platform/atmel/atmel-isi.c index d74aa73f26be..0514be6153df 100644 --- a/drivers/media/platform/atmel/atmel-isi.c +++ b/drivers/media/platform/atmel/atmel-isi.c @@ -70,7 +70,6 @@ struct frame_buffer { struct isi_graph_entity { struct device_node *node; - struct v4l2_async_subdev asd; struct v4l2_subdev *subdev; }; @@ -1136,45 +1135,26 @@ static const struct v4l2_async_notifier_operations isi_graph_notify_ops = { .complete = isi_graph_notify_complete, }; -static int isi_graph_parse(struct atmel_isi *isi, struct device_node *node) -{ - struct device_node *ep = NULL; - struct device_node *remote; - - ep = of_graph_get_next_endpoint(node, ep); - if (!ep) - return -EINVAL; - - remote = of_graph_get_remote_port_parent(ep); - of_node_put(ep); - if (!remote) - return -EINVAL; - - /* Remote node to connect */ - isi->entity.node = remote; - isi->entity.asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - isi->entity.asd.match.fwnode = of_fwnode_handle(remote); - return 0; -} - static int isi_graph_init(struct atmel_isi *isi) { + struct v4l2_async_subdev *asd; + struct device_node *ep; int ret; - /* Parse the graph to extract a list of subdevice DT nodes. */ - ret = isi_graph_parse(isi, isi->dev->of_node); - if (ret < 0) { - dev_err(isi->dev, "Graph parsing failed\n"); - return ret; - } + ep = of_graph_get_next_endpoint(isi->dev->of_node, NULL); + if (!ep) + return -EINVAL; v4l2_async_notifier_init(&isi->notifier); - ret = v4l2_async_notifier_add_subdev(&isi->notifier, &isi->entity.asd); - if (ret) { - of_node_put(isi->entity.node); - return ret; - } + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &isi->notifier, + of_fwnode_handle(ep), + struct v4l2_async_subdev); + of_node_put(ep); + + if (IS_ERR(asd)) + return PTR_ERR(asd); isi->notifier.ops = &isi_graph_notify_ops; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index a3304f49e499..0b78fecfd2a8 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -57,7 +57,7 @@ static int isc_parse_dt(struct device *dev, struct isc_device *isc) { struct device_node *np = dev->of_node; - struct device_node *epn = NULL, *rem; + struct device_node *epn = NULL; struct isc_subdev_entity *subdev_entity; unsigned int flags; int ret; @@ -71,17 +71,9 @@ static int isc_parse_dt(struct device *dev, struct isc_device *isc) if (!epn) return 0; - rem = of_graph_get_remote_port_parent(epn); - if (!rem) { - dev_notice(dev, "Remote device at %pOF not found\n", - epn); - continue; - } - ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), &v4l2_epn); if (ret) { - of_node_put(rem); ret = -EINVAL; dev_err(dev, "Could not parse the endpoint\n"); break; @@ -90,21 +82,10 @@ static int isc_parse_dt(struct device *dev, struct isc_device *isc) subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), GFP_KERNEL); if (!subdev_entity) { - of_node_put(rem); - ret = -ENOMEM; - break; - } - - /* asd will be freed by the subsystem once it's added to the - * notifier list - */ - subdev_entity->asd = kzalloc(sizeof(*subdev_entity->asd), - GFP_KERNEL); - if (!subdev_entity->asd) { - of_node_put(rem); ret = -ENOMEM; break; } + subdev_entity->epn = epn; flags = v4l2_epn.bus.parallel.flags; @@ -121,12 +102,10 @@ static int isc_parse_dt(struct device *dev, struct isc_device *isc) subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | ISC_PFE_CFG0_CCIR656; - subdev_entity->asd->match_type = V4L2_ASYNC_MATCH_FWNODE; - subdev_entity->asd->match.fwnode = of_fwnode_handle(rem); list_add_tail(&subdev_entity->list, &isc->subdev_entities); } - of_node_put(epn); + return ret; } @@ -228,13 +207,20 @@ static int atmel_isc_probe(struct platform_device *pdev) } list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { + struct v4l2_async_subdev *asd; + v4l2_async_notifier_init(&subdev_entity->notifier); - ret = v4l2_async_notifier_add_subdev(&subdev_entity->notifier, - subdev_entity->asd); - if (ret) { - fwnode_handle_put(subdev_entity->asd->match.fwnode); - kfree(subdev_entity->asd); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &subdev_entity->notifier, + of_fwnode_handle(subdev_entity->epn), + struct v4l2_async_subdev); + + of_node_put(subdev_entity->epn); + subdev_entity->epn = NULL; + + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); goto cleanup_subdev; } diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index be9ec59774d6..c68a3eac62cd 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -81,7 +81,6 @@ struct csi2rx_priv { struct media_pad pads[CSI2RX_PAD_MAX]; /* Remote source */ - struct v4l2_async_subdev asd; struct v4l2_subdev *source_subdev; int source_pad; }; @@ -362,6 +361,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx) { struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; + struct v4l2_async_subdev *asd; struct fwnode_handle *fwh; struct device_node *ep; int ret; @@ -395,17 +395,14 @@ static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx) return -EINVAL; } - csi2rx->asd.match.fwnode = fwnode_graph_get_remote_port_parent(fwh); - csi2rx->asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - of_node_put(ep); - v4l2_async_notifier_init(&csi2rx->notifier); - ret = v4l2_async_notifier_add_subdev(&csi2rx->notifier, &csi2rx->asd); - if (ret) { - fwnode_handle_put(csi2rx->asd.match.fwnode); - return ret; - } + asd = v4l2_async_notifier_add_fwnode_remote_subdev(&csi2rx->notifier, + fwh, + struct v4l2_async_subdev); + of_node_put(ep); + if (IS_ERR(asd)) + return PTR_ERR(asd); csi2rx->notifier.ops = &csi2rx_notifier_ops; diff --git a/drivers/media/platform/davinci/vpbe.c b/drivers/media/platform/davinci/vpbe.c index fe9468b180e6..5f0aeb744e81 100644 --- a/drivers/media/platform/davinci/vpbe.c +++ b/drivers/media/platform/davinci/vpbe.c @@ -628,7 +628,7 @@ static int vpbe_initialize(struct device *dev, struct vpbe_device *vpbe_dev) if (err) { v4l2_err(&vpbe_dev->v4l2_dev, "unable to initialize the OSD device"); - err = -ENOMEM; + ret = -ENOMEM; goto fail_dev_unregister; } } diff --git a/drivers/media/platform/davinci/vpif.c b/drivers/media/platform/davinci/vpif.c index 5e67994e62cc..f1ce10828b8e 100644 --- a/drivers/media/platform/davinci/vpif.c +++ b/drivers/media/platform/davinci/vpif.c @@ -41,7 +41,7 @@ MODULE_ALIAS("platform:" VPIF_DRIVER_NAME); #define VPIF_CH2_MAX_MODES 15 #define VPIF_CH3_MAX_MODES 2 -spinlock_t vpif_lock; +DEFINE_SPINLOCK(vpif_lock); EXPORT_SYMBOL_GPL(vpif_lock); void __iomem *vpif_base; @@ -437,7 +437,6 @@ static int vpif_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); pm_runtime_get(&pdev->dev); - spin_lock_init(&vpif_lock); dev_info(&pdev->dev, "vpif probe success\n"); /* diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index 72a0e94e2e21..8d2e165bf7de 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -1584,7 +1584,7 @@ vpif_capture_get_pdata(struct platform_device *pdev) pdata->asd[i] = v4l2_async_notifier_add_fwnode_subdev( &vpif_obj.notifier, of_fwnode_handle(rem), - sizeof(struct v4l2_async_subdev)); + struct v4l2_async_subdev); if (IS_ERR(pdata->asd[i])) goto err_cleanup; diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index 46afc029138f..e5f61d9b221d 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -1117,23 +1117,6 @@ static void free_vpif_objs(void) kfree(vpif_obj.dev[i]); } -static int vpif_async_bound(struct v4l2_async_notifier *notifier, - struct v4l2_subdev *subdev, - struct v4l2_async_subdev *asd) -{ - int i; - - for (i = 0; i < vpif_obj.config->subdev_count; i++) - if (!strcmp(vpif_obj.config->subdevinfo[i].name, - subdev->name)) { - vpif_obj.sd[i] = subdev; - vpif_obj.sd[i]->grp_id = 1 << i; - return 0; - } - - return -EINVAL; -} - static int vpif_probe_complete(void) { struct common_obj *common; @@ -1230,16 +1213,6 @@ probe_out: return err; } -static int vpif_async_complete(struct v4l2_async_notifier *notifier) -{ - return vpif_probe_complete(); -} - -static const struct v4l2_async_notifier_operations vpif_async_ops = { - .bound = vpif_async_bound, - .complete = vpif_async_complete, -}; - /* * vpif_probe: This function creates device entries by register itself to the * V4L2 driver and initializes fields of each channel objects @@ -1294,52 +1267,28 @@ static __init int vpif_probe(struct platform_device *pdev) goto vpif_unregister; } - v4l2_async_notifier_init(&vpif_obj.notifier); - - if (!vpif_obj.config->asd_sizes) { - i2c_adap = i2c_get_adapter(vpif_obj.config->i2c_adapter_id); - for (i = 0; i < subdev_count; i++) { - vpif_obj.sd[i] = - v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev, - i2c_adap, - &subdevdata[i]. - board_info, - NULL); - if (!vpif_obj.sd[i]) { - vpif_err("Error registering v4l2 subdevice\n"); - err = -ENODEV; - goto probe_subdev_out; - } - - if (vpif_obj.sd[i]) - vpif_obj.sd[i]->grp_id = 1 << i; - } - err = vpif_probe_complete(); - if (err) { + i2c_adap = i2c_get_adapter(vpif_obj.config->i2c_adapter_id); + for (i = 0; i < subdev_count; i++) { + vpif_obj.sd[i] = + v4l2_i2c_new_subdev_board(&vpif_obj.v4l2_dev, + i2c_adap, + &subdevdata[i].board_info, + NULL); + if (!vpif_obj.sd[i]) { + vpif_err("Error registering v4l2 subdevice\n"); + err = -ENODEV; goto probe_subdev_out; } - } else { - for (i = 0; i < vpif_obj.config->asd_sizes[0]; i++) { - err = v4l2_async_notifier_add_subdev( - &vpif_obj.notifier, vpif_obj.config->asd[i]); - if (err) - goto probe_cleanup; - } - vpif_obj.notifier.ops = &vpif_async_ops; - err = v4l2_async_notifier_register(&vpif_obj.v4l2_dev, - &vpif_obj.notifier); - if (err) { - vpif_err("Error registering async notifier\n"); - err = -EINVAL; - goto probe_cleanup; - } + if (vpif_obj.sd[i]) + vpif_obj.sd[i]->grp_id = 1 << i; } + err = vpif_probe_complete(); + if (err) + goto probe_subdev_out; return 0; -probe_cleanup: - v4l2_async_notifier_cleanup(&vpif_obj.notifier); probe_subdev_out: kfree(vpif_obj.sd); vpif_unregister: @@ -1358,11 +1307,6 @@ static int vpif_remove(struct platform_device *device) struct channel_obj *ch; int i; - if (vpif_obj.config->asd_sizes) { - v4l2_async_notifier_unregister(&vpif_obj.notifier); - v4l2_async_notifier_cleanup(&vpif_obj.notifier); - } - v4l2_device_unregister(&vpif_obj.v4l2_dev); kfree(vpif_obj.sd); diff --git a/drivers/media/platform/davinci/vpif_display.h b/drivers/media/platform/davinci/vpif_display.h index f731a65eefd6..f98062e79167 100644 --- a/drivers/media/platform/davinci/vpif_display.h +++ b/drivers/media/platform/davinci/vpif_display.h @@ -118,7 +118,6 @@ struct vpif_device { struct v4l2_device v4l2_dev; struct channel_obj *dev[VPIF_DISPLAY_NUM_CHANNELS]; struct v4l2_subdev **sd; - struct v4l2_async_notifier notifier; struct vpif_display_config *config; }; diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index e636c33e847b..8e1e892085ec 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -401,6 +401,7 @@ static int fimc_md_parse_one_endpoint(struct fimc_md *fmd, int index = fmd->num_sensors; struct fimc_source_info *pd = &fmd->sensor[index].pdata; struct device_node *rem, *np; + struct v4l2_async_subdev *asd; struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 }; int ret; @@ -418,10 +419,10 @@ static int fimc_md_parse_one_endpoint(struct fimc_md *fmd, pd->mux_id = (endpoint.base.port - 1) & 0x1; rem = of_graph_get_remote_port_parent(ep); - of_node_put(ep); if (rem == NULL) { v4l2_info(&fmd->v4l2_dev, "Remote device at %pOF not found\n", ep); + of_node_put(ep); return 0; } @@ -450,6 +451,7 @@ static int fimc_md_parse_one_endpoint(struct fimc_md *fmd, * checking parent's node name. */ np = of_get_parent(rem); + of_node_put(rem); if (of_node_name_eq(np, "i2c-isp")) pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK; @@ -458,20 +460,20 @@ static int fimc_md_parse_one_endpoint(struct fimc_md *fmd, of_node_put(np); if (WARN_ON(index >= ARRAY_SIZE(fmd->sensor))) { - of_node_put(rem); + of_node_put(ep); return -EINVAL; } - fmd->sensor[index].asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - fmd->sensor[index].asd.match.fwnode = of_fwnode_handle(rem); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &fmd->subdev_notifier, of_fwnode_handle(ep), + struct v4l2_async_subdev); - ret = v4l2_async_notifier_add_subdev(&fmd->subdev_notifier, - &fmd->sensor[index].asd); - if (ret) { - of_node_put(rem); - return ret; - } + of_node_put(ep); + + if (IS_ERR(asd)) + return PTR_ERR(asd); + fmd->sensor[index].asd = asd; fmd->num_sensors++; return 0; @@ -1381,7 +1383,8 @@ static int subdev_notifier_bound(struct v4l2_async_notifier *notifier, /* Find platform data for this sensor subdev */ for (i = 0; i < ARRAY_SIZE(fmd->sensor); i++) - if (fmd->sensor[i].asd.match.fwnode == + if (fmd->sensor[i].asd && + fmd->sensor[i].asd->match.fwnode == of_fwnode_handle(subdev->dev->of_node)) si = &fmd->sensor[i]; diff --git a/drivers/media/platform/exynos4-is/media-dev.h b/drivers/media/platform/exynos4-is/media-dev.h index 9447fafe23c6..a3876d668ea6 100644 --- a/drivers/media/platform/exynos4-is/media-dev.h +++ b/drivers/media/platform/exynos4-is/media-dev.h @@ -83,7 +83,7 @@ struct fimc_camclk_info { */ struct fimc_sensor_info { struct fimc_source_info pdata; - struct v4l2_async_subdev asd; + struct v4l2_async_subdev *asd; struct v4l2_subdev *subdev; struct fimc_dev *host; }; diff --git a/drivers/media/platform/marvell-ccic/cafe-driver.c b/drivers/media/platform/marvell-ccic/cafe-driver.c index 00f623d62c96..9c94a8b58b7c 100644 --- a/drivers/media/platform/marvell-ccic/cafe-driver.c +++ b/drivers/media/platform/marvell-ccic/cafe-driver.c @@ -489,6 +489,7 @@ static int cafe_pci_probe(struct pci_dev *pdev, int ret; struct cafe_camera *cam; struct mcam_camera *mcam; + struct v4l2_async_subdev *asd; /* * Start putting together one of our big camera structures. @@ -546,9 +547,16 @@ static int cafe_pci_probe(struct pci_dev *pdev, if (ret) goto out_pdown; - mcam->asd.match_type = V4L2_ASYNC_MATCH_I2C; - mcam->asd.match.i2c.adapter_id = i2c_adapter_id(cam->i2c_adapter); - mcam->asd.match.i2c.address = ov7670_info.addr; + v4l2_async_notifier_init(&mcam->notifier); + + asd = v4l2_async_notifier_add_i2c_subdev(&mcam->notifier, + i2c_adapter_id(cam->i2c_adapter), + ov7670_info.addr, + struct v4l2_async_subdev); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + goto out_smbus_shutdown; + } ret = mccic_register(mcam); if (ret) diff --git a/drivers/media/platform/marvell-ccic/mcam-core.c b/drivers/media/platform/marvell-ccic/mcam-core.c index c012fd2e1d29..141bf5d97a04 100644 --- a/drivers/media/platform/marvell-ccic/mcam-core.c +++ b/drivers/media/platform/marvell-ccic/mcam-core.c @@ -931,6 +931,7 @@ static int mclk_enable(struct clk_hw *hw) mclk_div = 2; } + pm_runtime_get_sync(cam->dev); clk_enable(cam->clk[0]); mcam_reg_write(cam, REG_CLKCTRL, (mclk_src << 29) | mclk_div); mcam_ctlr_power_up(cam); @@ -944,6 +945,7 @@ static void mclk_disable(struct clk_hw *hw) mcam_ctlr_power_down(cam); clk_disable(cam->clk[0]); + pm_runtime_put(cam->dev); } static unsigned long mclk_recalc_rate(struct clk_hw *hw, @@ -1866,16 +1868,6 @@ int mccic_register(struct mcam_camera *cam) cam->pix_format = mcam_def_pix_format; cam->mbus_code = mcam_def_mbus_code; - /* - * Register sensor notifier. - */ - v4l2_async_notifier_init(&cam->notifier); - ret = v4l2_async_notifier_add_subdev(&cam->notifier, &cam->asd); - if (ret) { - cam_warn(cam, "failed to add subdev to a notifier"); - goto out; - } - cam->notifier.ops = &mccic_notify_ops; ret = v4l2_async_notifier_register(&cam->v4l2_dev, &cam->notifier); if (ret < 0) { diff --git a/drivers/media/platform/marvell-ccic/mcam-core.h b/drivers/media/platform/marvell-ccic/mcam-core.h index b55545822fd2..f324d808d737 100644 --- a/drivers/media/platform/marvell-ccic/mcam-core.h +++ b/drivers/media/platform/marvell-ccic/mcam-core.h @@ -151,7 +151,6 @@ struct mcam_camera { */ struct video_device vdev; struct v4l2_async_notifier notifier; - struct v4l2_async_subdev asd; struct v4l2_subdev *sensor; /* Videobuf2 stuff */ diff --git a/drivers/media/platform/marvell-ccic/mmp-driver.c b/drivers/media/platform/marvell-ccic/mmp-driver.c index 032fdddbbecc..f2f09cea751d 100644 --- a/drivers/media/platform/marvell-ccic/mmp-driver.c +++ b/drivers/media/platform/marvell-ccic/mmp-driver.c @@ -180,6 +180,7 @@ static int mmpcam_probe(struct platform_device *pdev) struct resource *res; struct fwnode_handle *ep; struct mmp_camera_platform_data *pdata; + struct v4l2_async_subdev *asd; int ret; cam = devm_kzalloc(&pdev->dev, sizeof(*cam), GFP_KERNEL); @@ -238,10 +239,15 @@ static int mmpcam_probe(struct platform_device *pdev) if (!ep) return -ENODEV; - mcam->asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - mcam->asd.match.fwnode = fwnode_graph_get_remote_port_parent(ep); + v4l2_async_notifier_init(&mcam->notifier); + asd = v4l2_async_notifier_add_fwnode_remote_subdev(&mcam->notifier, ep, + struct v4l2_async_subdev); fwnode_handle_put(ep); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); + goto out; + } /* * Register the device with the core. @@ -278,7 +284,6 @@ static int mmpcam_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); return 0; out: - fwnode_handle_put(mcam->asd.match.fwnode); mccic_shutdown(mcam); return ret; diff --git a/drivers/media/platform/meson/ge2d/ge2d.c b/drivers/media/platform/meson/ge2d/ge2d.c index f526501bd473..153612ca96fc 100644 --- a/drivers/media/platform/meson/ge2d/ge2d.c +++ b/drivers/media/platform/meson/ge2d/ge2d.c @@ -988,6 +988,7 @@ static int ge2d_probe(struct platform_device *pdev) vfd = video_device_alloc(); if (!vfd) { v4l2_err(&ge2d->v4l2_dev, "Failed to allocate video device\n"); + ret = -ENOMEM; goto unreg_v4l2_dev; } diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c index 724c7333b6e5..ace4528cdc5e 100644 --- a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c +++ b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c @@ -199,7 +199,6 @@ static const struct mtk_mdp_fmt *mtk_mdp_try_fmt_mplane(struct mtk_mdp_ctx *ctx, pix_mp->ycbcr_enc = ctx->ycbcr_enc; pix_mp->quantization = ctx->quant; } - memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved)); max_w = variant->pix_max->target_rot_dis_w; max_h = variant->pix_max->target_rot_dis_h; @@ -247,8 +246,6 @@ static const struct mtk_mdp_fmt *mtk_mdp_try_fmt_mplane(struct mtk_mdp_ctx *ctx, pix_mp->plane_fmt[i].bytesperline = bpl; if (pix_mp->plane_fmt[i].sizeimage < sizeimage) pix_mp->plane_fmt[i].sizeimage = sizeimage; - memset(pix_mp->plane_fmt[i].reserved, 0, - sizeof(pix_mp->plane_fmt[i].reserved)); mtk_mdp_dbg(2, "[%d] p%d, bpl:%d, sizeimage:%u (%u)", ctx->id, i, bpl, pix_mp->plane_fmt[i].sizeimage, sizeimage); } diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c index c768a587a944..56d86e59421e 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_dec.c @@ -657,7 +657,6 @@ static int vidioc_try_fmt(struct v4l2_format *f, const struct mtk_video_fmt *fmt) { struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - int i; pix_fmt_mp->field = V4L2_FIELD_NONE; @@ -715,12 +714,7 @@ static int vidioc_try_fmt(struct v4l2_format *f, } } - for (i = 0; i < pix_fmt_mp->num_planes; i++) - memset(&(pix_fmt_mp->plane_fmt[i].reserved[0]), 0x0, - sizeof(pix_fmt_mp->plane_fmt[0].reserved)); - pix_fmt_mp->flags = 0; - memset(&pix_fmt_mp->reserved, 0x0, sizeof(pix_fmt_mp->reserved)); return 0; } diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c index 21de1431cfcb..8c917969c2f1 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c @@ -121,7 +121,6 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, return -EINVAL; f->pixelformat = formats[f->index].fourcc; - memset(f->reserved, 0, sizeof(f->reserved)); return 0; } @@ -252,7 +251,6 @@ static int vidioc_try_fmt(struct v4l2_format *f, const struct mtk_video_fmt *fmt) { struct v4l2_pix_format_mplane *pix_fmt_mp = &f->fmt.pix_mp; - int i; pix_fmt_mp->field = V4L2_FIELD_NONE; @@ -320,13 +318,7 @@ static int vidioc_try_fmt(struct v4l2_format *f, } } - for (i = 0; i < pix_fmt_mp->num_planes; i++) - memset(&(pix_fmt_mp->plane_fmt[i].reserved[0]), 0x0, - sizeof(pix_fmt_mp->plane_fmt[0].reserved)); - pix_fmt_mp->flags = 0; - memset(&pix_fmt_mp->reserved, 0x0, - sizeof(pix_fmt_mp->reserved)); return 0; } @@ -532,8 +524,6 @@ static int vidioc_venc_g_fmt(struct file *file, void *priv, for (i = 0; i < pix->num_planes; i++) { pix->plane_fmt[i].bytesperline = q_data->bytesperline[i]; pix->plane_fmt[i].sizeimage = q_data->sizeimage[i]; - memset(&(pix->plane_fmt[i].reserved[0]), 0x0, - sizeof(pix->plane_fmt[i].reserved)); } pix->flags = 0; diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c index dfb42e19bf81..be3842e6ca47 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c @@ -303,7 +303,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) ret = PTR_ERR((__force void *)dev->reg_base[VENC_SYS]); goto err_res; } - mtk_v4l2_debug(2, "reg[%d] base=0x%p", i, dev->reg_base[VENC_SYS]); + mtk_v4l2_debug(2, "reg[%d] base=0x%p", VENC_SYS, dev->reg_base[VENC_SYS]); res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (res == NULL) { @@ -332,7 +332,7 @@ static int mtk_vcodec_probe(struct platform_device *pdev) ret = PTR_ERR((__force void *)dev->reg_base[VENC_LT_SYS]); goto err_res; } - mtk_v4l2_debug(2, "reg[%d] base=0x%p", i, dev->reg_base[VENC_LT_SYS]); + mtk_v4l2_debug(2, "reg[%d] base=0x%p", VENC_LT_SYS, dev->reg_base[VENC_LT_SYS]); dev->enc_lt_irq = platform_get_irq(pdev, 1); irq_set_status_flags(dev->enc_lt_irq, IRQ_NOAUTOEN); diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_intr.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_intr.c index a3c7a380c930..70580c2525ba 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_intr.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_intr.c @@ -27,13 +27,13 @@ int mtk_vcodec_wait_for_done_ctx(struct mtk_vcodec_ctx *ctx, int command, if (!ret) { status = -1; /* timeout */ - mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, wait_event_interruptible_timeout time=%ums out %d %d!", - ctx->id, ctx->type, command, timeout_ms, - ctx->int_cond, ctx->int_type); + mtk_v4l2_err("[%d] ctx->type=%d, cmd=%d, wait_event_interruptible_timeout time=%ums out %d %d!", + ctx->id, ctx->type, command, timeout_ms, + ctx->int_cond, ctx->int_type); } else if (-ERESTARTSYS == ret) { - mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, wait_event_interruptible_timeout interrupted by a signal %d %d", - ctx->id, ctx->type, command, ctx->int_cond, - ctx->int_type); + mtk_v4l2_err("[%d] ctx->type=%d, cmd=%d, wait_event_interruptible_timeout interrupted by a signal %d %d", + ctx->id, ctx->type, command, ctx->int_cond, + ctx->int_type); status = -1; } diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c index 5ea153a68522..d9880210b2ab 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c @@ -890,7 +890,8 @@ static int vdec_vp9_decode(void *h_vdec, struct mtk_vcodec_mem *bs, memset(inst->seg_id_buf.va, 0, inst->seg_id_buf.size); if (vsi->show_frame & BIT(2)) { - if (vpu_dec_start(&inst->vpu, NULL, 0)) { + ret = vpu_dec_start(&inst->vpu, NULL, 0); + if (ret) { mtk_vcodec_err(inst, "vpu trig decoder failed"); goto DECODE_ERROR; } diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index b1fc4518e275..a6bb7d9bf75f 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -2126,21 +2126,6 @@ static void isp_parse_of_csi1_endpoint(struct device *dev, buscfg->bus.ccp2.crc = 1; } -static int isp_alloc_isd(struct isp_async_subdev **isd, - struct isp_bus_cfg **buscfg) -{ - struct isp_async_subdev *__isd; - - __isd = kzalloc(sizeof(*__isd), GFP_KERNEL); - if (!__isd) - return -ENOMEM; - - *isd = __isd; - *buscfg = &__isd->bus; - - return 0; -} - static struct { u32 phy; u32 csi2_if; @@ -2156,7 +2141,6 @@ static int isp_parse_of_endpoints(struct isp_device *isp) { struct fwnode_handle *ep; struct isp_async_subdev *isd = NULL; - struct isp_bus_cfg *buscfg; unsigned int i; ep = fwnode_graph_get_endpoint_by_id( @@ -2174,20 +2158,13 @@ static int isp_parse_of_endpoints(struct isp_device *isp) ret = v4l2_fwnode_endpoint_parse(ep, &vep); if (!ret) { - ret = isp_alloc_isd(&isd, &buscfg); - if (ret) - return ret; - } - - if (!ret) { - isp_parse_of_parallel_endpoint(isp->dev, &vep, buscfg); - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &isp->notifier, ep, &isd->asd); + isd = v4l2_async_notifier_add_fwnode_remote_subdev( + &isp->notifier, ep, struct isp_async_subdev); + if (!IS_ERR(isd)) + isp_parse_of_parallel_endpoint(isp->dev, &vep, &isd->bus); } fwnode_handle_put(ep); - if (ret) - kfree(isd); } for (i = 0; i < ARRAY_SIZE(isp_bus_interfaces); i++) { @@ -2206,15 +2183,8 @@ static int isp_parse_of_endpoints(struct isp_device *isp) dev_dbg(isp->dev, "parsing serial interface %u, node %pOF\n", i, to_of_node(ep)); - ret = isp_alloc_isd(&isd, &buscfg); - if (ret) - return ret; - ret = v4l2_fwnode_endpoint_parse(ep, &vep); - if (!ret) { - buscfg->interface = isp_bus_interfaces[i].csi2_if; - isp_parse_of_csi2_endpoint(isp->dev, &vep, buscfg); - } else if (ret == -ENXIO) { + if (ret == -ENXIO) { vep = (struct v4l2_fwnode_endpoint) { .bus_type = V4L2_MBUS_CSI1 }; ret = v4l2_fwnode_endpoint_parse(ep, &vep); @@ -2224,21 +2194,33 @@ static int isp_parse_of_endpoints(struct isp_device *isp) { .bus_type = V4L2_MBUS_CCP2 }; ret = v4l2_fwnode_endpoint_parse(ep, &vep); } - if (!ret) { - buscfg->interface = - isp_bus_interfaces[i].csi1_if; - isp_parse_of_csi1_endpoint(isp->dev, &vep, - buscfg); - } } - if (!ret) - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &isp->notifier, ep, &isd->asd); + if (!ret) { + isd = v4l2_async_notifier_add_fwnode_remote_subdev( + &isp->notifier, ep, struct isp_async_subdev); + + if (!IS_ERR(isd)) { + switch (vep.bus_type) { + case V4L2_MBUS_CSI2_DPHY: + isd->bus.interface = + isp_bus_interfaces[i].csi2_if; + isp_parse_of_csi2_endpoint(isp->dev, &vep, &isd->bus); + break; + case V4L2_MBUS_CSI1: + case V4L2_MBUS_CCP2: + isd->bus.interface = + isp_bus_interfaces[i].csi1_if; + isp_parse_of_csi1_endpoint(isp->dev, &vep, + &isd->bus); + break; + default: + break; + } + } + } fwnode_handle_put(ep); - if (ret) - kfree(isd); } return 0; diff --git a/drivers/media/platform/pxa_camera.c b/drivers/media/platform/pxa_camera.c index b664ce7558a1..14077797f5e1 100644 --- a/drivers/media/platform/pxa_camera.c +++ b/drivers/media/platform/pxa_camera.c @@ -31,7 +31,6 @@ #include <linux/dma/pxa-dma.h> #include <media/v4l2-async.h> -#include <media/v4l2-clk.h> #include <media/v4l2-common.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> @@ -656,8 +655,6 @@ struct pxa_camera_dev { const struct pxa_camera_format_xlate *current_fmt; struct v4l2_pix_format current_pix; - struct v4l2_async_subdev asd; - /* * PXA27x is only supposed to handle one camera on its Quick Capture * interface. If anyone ever builds hardware to enable more than @@ -677,7 +674,6 @@ struct pxa_camera_dev { unsigned long ciclk; unsigned long mclk; u32 mclk_divisor; - struct v4l2_clk *mclk_clk; u16 width_flags; /* max 10 bits */ struct list_head capture; @@ -1386,6 +1382,9 @@ static int pxac_vb2_prepare(struct vb2_buffer *vb) struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue); struct pxa_buffer *buf = vb2_to_pxa_buffer(vb); int ret = 0; +#ifdef DEBUG + int i; +#endif switch (pcdev->channels) { case 1: @@ -2030,9 +2029,6 @@ static const struct v4l2_ioctl_ops pxa_camera_ioctl_ops = { .vidioc_unsubscribe_event = v4l2_event_unsubscribe, }; -static const struct v4l2_clk_ops pxa_camera_mclk_ops = { -}; - static const struct video_device pxa_camera_videodev_template = { .name = "pxa-camera", .minor = -1, @@ -2140,11 +2136,6 @@ static void pxa_camera_sensor_unbind(struct v4l2_async_notifier *notifier, pxa_camera_destroy_formats(pcdev); - if (pcdev->mclk_clk) { - v4l2_clk_unregister(pcdev->mclk_clk); - pcdev->mclk_clk = NULL; - } - video_unregister_device(&pcdev->vdev); pcdev->sensor = NULL; @@ -2199,11 +2190,11 @@ static int pxa_camera_resume(struct device *dev) } static int pxa_camera_pdata_from_dt(struct device *dev, - struct pxa_camera_dev *pcdev, - struct v4l2_async_subdev *asd) + struct pxa_camera_dev *pcdev) { u32 mclk_rate; - struct device_node *remote, *np = dev->of_node; + struct v4l2_async_subdev *asd; + struct device_node *np = dev->of_node; struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; int err = of_property_read_u32(np, "clock-frequency", &mclk_rate); @@ -2255,13 +2246,12 @@ static int pxa_camera_pdata_from_dt(struct device *dev, if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) pcdev->platform_flags |= PXA_CAMERA_PCLK_EN; - asd->match_type = V4L2_ASYNC_MATCH_FWNODE; - remote = of_graph_get_remote_port_parent(np); - if (remote) - asd->match.fwnode = of_fwnode_handle(remote); - else - dev_notice(dev, "no remote for %pOF\n", np); - + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &pcdev->notifier, + of_fwnode_handle(np), + struct v4l2_async_subdev); + if (IS_ERR(asd)) + err = PTR_ERR(asd); out: of_node_put(np); @@ -2278,7 +2268,6 @@ static int pxa_camera_probe(struct platform_device *pdev) .src_maxburst = 8, .direction = DMA_DEV_TO_MEM, }; - char clk_name[V4L2_CLK_NAME_SIZE]; int irq; int err = 0, i; @@ -2297,18 +2286,23 @@ static int pxa_camera_probe(struct platform_device *pdev) if (IS_ERR(pcdev->clk)) return PTR_ERR(pcdev->clk); + v4l2_async_notifier_init(&pcdev->notifier); pcdev->res = res; - pcdev->pdata = pdev->dev.platform_data; if (pcdev->pdata) { + struct v4l2_async_subdev *asd; + pcdev->platform_flags = pcdev->pdata->flags; pcdev->mclk = pcdev->pdata->mclk_10khz * 10000; - pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C; - pcdev->asd.match.i2c.adapter_id = - pcdev->pdata->sensor_i2c_adapter_id; - pcdev->asd.match.i2c.address = pcdev->pdata->sensor_i2c_address; + asd = v4l2_async_notifier_add_i2c_subdev( + &pcdev->notifier, + pcdev->pdata->sensor_i2c_adapter_id, + pcdev->pdata->sensor_i2c_address, + struct v4l2_async_subdev); + if (IS_ERR(asd)) + err = PTR_ERR(asd); } else if (pdev->dev.of_node) { - err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev, &pcdev->asd); + err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev); } else { return -ENODEV; } @@ -2400,43 +2394,18 @@ static int pxa_camera_probe(struct platform_device *pdev) if (err) goto exit_deactivate; - v4l2_async_notifier_init(&pcdev->notifier); - - err = v4l2_async_notifier_add_subdev(&pcdev->notifier, &pcdev->asd); - if (err) { - fwnode_handle_put(pcdev->asd.match.fwnode); - goto exit_free_v4l2dev; - } - - pcdev->notifier.ops = &pxa_camera_sensor_ops; - - if (!of_have_populated_dt()) - pcdev->asd.match_type = V4L2_ASYNC_MATCH_I2C; - err = pxa_camera_init_videobuf2(pcdev); if (err) goto exit_notifier_cleanup; - v4l2_clk_name_i2c(clk_name, sizeof(clk_name), - pcdev->asd.match.i2c.adapter_id, - pcdev->asd.match.i2c.address); - - pcdev->mclk_clk = v4l2_clk_register(&pxa_camera_mclk_ops, clk_name, NULL); - if (IS_ERR(pcdev->mclk_clk)) { - err = PTR_ERR(pcdev->mclk_clk); - goto exit_notifier_cleanup; - } - + pcdev->notifier.ops = &pxa_camera_sensor_ops; err = v4l2_async_notifier_register(&pcdev->v4l2_dev, &pcdev->notifier); if (err) - goto exit_free_clk; + goto exit_notifier_cleanup; return 0; -exit_free_clk: - v4l2_clk_unregister(pcdev->mclk_clk); exit_notifier_cleanup: v4l2_async_notifier_cleanup(&pcdev->notifier); -exit_free_v4l2dev: v4l2_device_unregister(&pcdev->v4l2_dev); exit_deactivate: pxa_camera_deactivate(pcdev); @@ -2463,11 +2432,6 @@ static int pxa_camera_remove(struct platform_device *pdev) v4l2_async_notifier_unregister(&pcdev->notifier); v4l2_async_notifier_cleanup(&pcdev->notifier); - if (pcdev->mclk_clk) { - v4l2_clk_unregister(pcdev->mclk_clk); - pcdev->mclk_clk = NULL; - } - v4l2_device_unregister(&pcdev->v4l2_dev); dev_info(&pdev->dev, "PXA Camera driver unloaded\n"); diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c index bd9334af1c73..97cea7c4d769 100644 --- a/drivers/media/platform/qcom/camss/camss-video.c +++ b/drivers/media/platform/qcom/camss/camss-video.c @@ -579,7 +579,7 @@ static int video_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f) break; } - if (k < f->index) + if (k == -1 || k < f->index) /* * All the unique pixel formats matching the arguments * have been enumerated (k >= 0 and f->index > 0), or @@ -961,6 +961,7 @@ int msm_video_register(struct camss_video *video, struct v4l2_device *v4l2_dev, video->nformats = ARRAY_SIZE(formats_rdi_8x96); } } else { + ret = -EINVAL; goto error_video_register; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 8fefce57bc49..7c0f669f8aa6 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -655,7 +655,6 @@ static int camss_of_parse_ports(struct camss *camss) for_each_endpoint_of_node(dev->of_node, node) { struct camss_async_subdev *csd; - struct v4l2_async_subdev *asd; if (!of_device_is_available(node)) continue; @@ -667,17 +666,15 @@ static int camss_of_parse_ports(struct camss *camss) goto err_cleanup; } - asd = v4l2_async_notifier_add_fwnode_subdev( + csd = v4l2_async_notifier_add_fwnode_subdev( &camss->notifier, of_fwnode_handle(remote), - sizeof(*csd)); + struct camss_async_subdev); of_node_put(remote); - if (IS_ERR(asd)) { - ret = PTR_ERR(asd); + if (IS_ERR(csd)) { + ret = PTR_ERR(csd); goto err_cleanup; } - csd = container_of(asd, struct camss_async_subdev, asd); - ret = camss_of_parse_endpoint_node(dev, node, csd); if (ret < 0) goto err_cleanup; diff --git a/drivers/media/platform/qcom/venus/Makefile b/drivers/media/platform/qcom/venus/Makefile index dfc636865709..91ee6be10292 100644 --- a/drivers/media/platform/qcom/venus/Makefile +++ b/drivers/media/platform/qcom/venus/Makefile @@ -3,7 +3,9 @@ venus-core-objs += core.o helpers.o firmware.o \ hfi_venus.o hfi_msgs.o hfi_cmds.o hfi.o \ - hfi_parser.o pm_helpers.o dbgfs.o + hfi_parser.o pm_helpers.o dbgfs.o \ + hfi_platform.o hfi_platform_v4.o \ + hfi_platform_v6.o hfi_plat_bufs_v6.o \ venus-dec-objs += vdec.o vdec_ctrls.o venus-enc-objs += venc.o venc_ctrls.o diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 7233a7311757..f9896c121fd8 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -7,6 +7,7 @@ #include <linux/interconnect.h> #include <linux/ioctl.h> #include <linux/delay.h> +#include <linux/devcoredump.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of_device.h> @@ -22,6 +23,33 @@ #include "firmware.h" #include "pm_helpers.h" +static void venus_coredump(struct venus_core *core) +{ + struct device *dev; + phys_addr_t mem_phys; + size_t mem_size; + void *mem_va; + void *data; + + dev = core->dev; + mem_phys = core->fw.mem_phys; + mem_size = core->fw.mem_size; + + mem_va = memremap(mem_phys, mem_size, MEMREMAP_WC); + if (!mem_va) + return; + + data = vmalloc(mem_size); + if (!data) { + memunmap(mem_va); + return; + } + + memcpy(data, mem_va, mem_size); + memunmap(mem_va); + dev_coredumpv(dev, data, mem_size, GFP_KERNEL); +} + static void venus_event_notify(struct venus_core *core, u32 event) { struct venus_inst *inst; @@ -67,6 +95,8 @@ static void venus_sys_error_handler(struct work_struct *work) venus_shutdown(core); + venus_coredump(core); + pm_runtime_put_sync(core->dev); while (core->pmdomains[0] && pm_runtime_active(core->pmdomains[0])) @@ -488,17 +518,6 @@ static const struct freq_tbl sdm845_freq_table[] = { { 244800, 100000000 }, /* 1920x1080@30 */ }; -static const struct codec_freq_data sdm845_codec_freq_data[] = { - { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_ENC, 675, 10 }, - { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_ENC, 675, 10 }, - { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_ENC, 675, 10 }, - { V4L2_PIX_FMT_MPEG2, VIDC_SESSION_TYPE_DEC, 200, 10 }, - { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_DEC, 200, 10 }, - { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_DEC, 200, 10 }, - { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_DEC, 200, 10 }, - { V4L2_PIX_FMT_VP9, VIDC_SESSION_TYPE_DEC, 200, 10 }, -}; - static const struct bw_tbl sdm845_bw_table_enc[] = { { 1944000, 1612000, 0, 2416000, 0 }, /* 3840x2160@60 */ { 972000, 951000, 0, 1434000, 0 }, /* 3840x2160@30 */ @@ -520,8 +539,6 @@ static const struct venus_resources sdm845_res = { .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), .bw_tbl_dec = sdm845_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), - .codec_freq_data = sdm845_codec_freq_data, - .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), .clks = {"core", "iface", "bus" }, .clks_num = 3, .vcodec0_clks = { "core", "bus" }, @@ -543,8 +560,6 @@ static const struct venus_resources sdm845_res_v2 = { .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), .bw_tbl_dec = sdm845_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), - .codec_freq_data = sdm845_codec_freq_data, - .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), .clks = {"core", "iface", "bus" }, .clks_num = 3, .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, @@ -594,8 +609,6 @@ static const struct venus_resources sc7180_res = { .bw_tbl_enc_size = ARRAY_SIZE(sc7180_bw_table_enc), .bw_tbl_dec = sc7180_bw_table_dec, .bw_tbl_dec_size = ARRAY_SIZE(sc7180_bw_table_dec), - .codec_freq_data = sdm845_codec_freq_data, - .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), .clks = {"core", "iface", "bus" }, .clks_num = 3, .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index f03ed427accd..a252ed32cc14 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -14,6 +14,7 @@ #include "dbgfs.h" #include "hfi.h" +#include "hfi_platform.h" #define VDBGL "VenusLow : " #define VDBGM "VenusMed : " @@ -36,13 +37,6 @@ struct reg_val { u32 value; }; -struct codec_freq_data { - u32 pixfmt; - u32 session_type; - unsigned long vpp_freq; - unsigned long vsp_freq; -}; - struct bw_tbl { u32 mbs_per_sec; u32 avg; @@ -61,8 +55,6 @@ struct venus_resources { unsigned int bw_tbl_dec_size; const struct reg_val *reg_tbl; unsigned int reg_tbl_size; - const struct codec_freq_data *codec_freq_data; - unsigned int codec_freq_data_size; const char * const clks[VIDC_CLKS_NUM_MAX]; unsigned int clks_num; const char * const vcodec0_clks[VIDC_VCODEC_CLKS_NUM_MAX]; @@ -91,30 +83,6 @@ struct venus_format { u32 flags; }; -#define MAX_PLANES 4 -#define MAX_FMT_ENTRIES 32 -#define MAX_CAP_ENTRIES 32 -#define MAX_ALLOC_MODE_ENTRIES 16 -#define MAX_CODEC_NUM 32 - -struct raw_formats { - u32 buftype; - u32 fmt; -}; - -struct venus_caps { - u32 codec; - u32 domain; - bool cap_bufs_mode_dynamic; - unsigned int num_caps; - struct hfi_capability caps[MAX_CAP_ENTRIES]; - unsigned int num_pl; - struct hfi_profile_level pl[HFI_MAX_PROFILE_COUNT]; - unsigned int num_fmts; - struct raw_formats fmts[MAX_FMT_ENTRIES]; - bool valid; /* used only for Venus v1xx */ -}; - /** * struct venus_core - holds core parameters valid for all instances * @@ -123,7 +91,6 @@ struct venus_caps { * @clks: an array of struct clk pointers * @vcodec0_clks: an array of vcodec0 struct clk pointers * @vcodec1_clks: an array of vcodec1 struct clk pointers - * @pd_dl_venus: pmdomain device-link for venus domain * @pmdomains: an array of pmdomains struct device pointers * @vdev_dec: a reference to video device structure for decoder instances * @vdev_enc: a reference to video device structure for encoder instances @@ -145,7 +112,6 @@ struct venus_caps { * @enc_codecs: encoders supported by this core * @dec_codecs: decoders supported by this core * @max_sessions_supported: holds the maximum number of sessions - * @core_caps: core capabilities * @priv: a private filed for HFI operations * @ops: the core HFI operations * @work: a delayed work for handling system fatal error @@ -161,7 +127,6 @@ struct venus_core { struct icc_path *cpucfg_path; struct opp_table *opp_table; bool has_opp_table; - struct device_link *pd_dl_venus; struct device *pmdomains[VIDC_PMDOMAINS_NUM_MAX]; struct device_link *opp_dl_venus; struct device *opp_pmdomain; @@ -177,6 +142,8 @@ struct venus_core { struct device *dev; struct iommu_domain *iommu_domain; size_t mapped_mem_size; + phys_addr_t mem_phys; + size_t mem_size; } fw; struct mutex lock; struct list_head instances; @@ -191,15 +158,10 @@ struct venus_core { unsigned long enc_codecs; unsigned long dec_codecs; unsigned int max_sessions_supported; -#define ENC_ROTATION_CAPABILITY 0x1 -#define ENC_SCALING_CAPABILITY 0x2 -#define ENC_DEINTERLACE_CAPABILITY 0x4 -#define DEC_MULTI_STREAM_CAPABILITY 0x8 - unsigned int core_caps; void *priv; const struct hfi_ops *ops; struct delayed_work work; - struct venus_caps caps[MAX_CODEC_NUM]; + struct hfi_plat_caps caps[MAX_CODEC_NUM]; unsigned int codecs_count; unsigned int core0_usage_count; unsigned int core1_usage_count; @@ -230,10 +192,28 @@ struct venc_controls { u32 h264_b_qp; u32 h264_min_qp; u32 h264_max_qp; + u32 h264_i_min_qp; + u32 h264_i_max_qp; + u32 h264_p_min_qp; + u32 h264_p_max_qp; + u32 h264_b_min_qp; + u32 h264_b_max_qp; u32 h264_loop_filter_mode; s32 h264_loop_filter_alpha; s32 h264_loop_filter_beta; + u32 hevc_i_qp; + u32 hevc_p_qp; + u32 hevc_b_qp; + u32 hevc_min_qp; + u32 hevc_max_qp; + u32 hevc_i_min_qp; + u32 hevc_i_max_qp; + u32 hevc_p_min_qp; + u32 hevc_p_max_qp; + u32 hevc_b_min_qp; + u32 hevc_b_max_qp; + u32 vp8_min_qp; u32 vp8_max_qp; @@ -256,6 +236,8 @@ struct venc_controls { u32 hevc; u32 vp9; } level; + + u32 base_priority_id; }; struct venus_buffer { @@ -271,7 +253,8 @@ struct venus_buffer { struct clock_data { u32 core_id; unsigned long freq; - const struct codec_freq_data *codec_freq_data; + unsigned long vpp_freq; + unsigned long vsp_freq; }; #define to_venus_buffer(ptr) container_of(ptr, struct venus_buffer, vb) @@ -285,7 +268,6 @@ enum venus_dec_state { VENUS_DEC_STATE_DRAIN = 5, VENUS_DEC_STATE_DECODING = 6, VENUS_DEC_STATE_DRC = 7, - VENUS_DEC_STATE_DRC_FLUSH_DONE = 8, }; struct venus_ts_metadata { @@ -350,7 +332,7 @@ struct venus_ts_metadata { * @priv: a private for HFI operations callbacks * @session_type: the type of the session (decoder or encoder) * @hprop: a union used as a holder by get property - * @last_buf: last capture buffer for dynamic-resoluton-change + * @next_buf_last: a flag to mark next queued capture buffer as last */ struct venus_inst { struct list_head list; @@ -413,7 +395,9 @@ struct venus_inst { union hfi_get_property hprop; unsigned int core_acquired: 1; unsigned int bit_depth; - struct vb2_buffer *last_buf; + unsigned int pic_struct; + bool next_buf_last; + bool drain_active; }; #define IS_V1(core) ((core)->res->hfi_version == HFI_VERSION_1XX) @@ -433,7 +417,7 @@ static inline void *to_hfi_priv(struct venus_core *core) return core->priv; } -static inline struct venus_caps * +static inline struct hfi_plat_caps * venus_caps_by_codec(struct venus_core *core, u32 codec, u32 domain) { unsigned int c; diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index d03e2dd5808c..89defc21ea81 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -201,6 +201,9 @@ int venus_boot(struct venus_core *core) return -EINVAL; } + core->fw.mem_size = mem_size; + core->fw.mem_phys = mem_phys; + if (core->use_tz) ret = qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); else diff --git a/drivers/media/platform/qcom/venus/helpers.c b/drivers/media/platform/qcom/venus/helpers.c index 50439eb1ffea..76ece2ff8d39 100644 --- a/drivers/media/platform/qcom/venus/helpers.c +++ b/drivers/media/platform/qcom/venus/helpers.c @@ -7,7 +7,7 @@ #include <linux/mutex.h> #include <linux/slab.h> #include <linux/kernel.h> -#include <media/videobuf2-dma-sg.h> +#include <media/videobuf2-dma-contig.h> #include <media/v4l2-mem2mem.h> #include <asm/div64.h> @@ -15,6 +15,8 @@ #include "helpers.h" #include "hfi_helper.h" #include "pm_helpers.h" +#include "hfi_platform.h" +#include "hfi_parser.h" struct intbuf { struct list_head list; @@ -480,7 +482,7 @@ session_process_buf(struct venus_inst *inst, struct vb2_v4l2_buffer *vbuf) static bool is_dynamic_bufmode(struct venus_inst *inst) { struct venus_core *core = inst->core; - struct venus_caps *caps; + struct hfi_plat_caps *caps; /* * v4 doesn't send BUFFER_ALLOC_MODE_SUPPORTED property and supports @@ -552,6 +554,51 @@ static u32 to_hfi_raw_fmt(u32 v4l2_fmt) return 0; } +static int platform_get_bufreq(struct venus_inst *inst, u32 buftype, + struct hfi_buffer_requirements *req) +{ + enum hfi_version version = inst->core->res->hfi_version; + const struct hfi_platform *hfi_plat; + struct hfi_plat_buffers_params params; + bool is_dec = inst->session_type == VIDC_SESSION_TYPE_DEC; + struct venc_controls *enc_ctr = &inst->controls.enc; + + hfi_plat = hfi_platform_get(version); + + if (!hfi_plat || !hfi_plat->bufreq) + return -EINVAL; + + params.version = version; + params.num_vpp_pipes = hfi_platform_num_vpp_pipes(version); + + if (is_dec) { + params.width = inst->width; + params.height = inst->height; + params.codec = inst->fmt_out->pixfmt; + params.hfi_color_fmt = to_hfi_raw_fmt(inst->fmt_cap->pixfmt); + params.dec.max_mbs_per_frame = mbs_per_frame_max(inst); + params.dec.buffer_size_limit = 0; + params.dec.is_secondary_output = + inst->opb_buftype == HFI_BUFFER_OUTPUT2; + params.dec.is_interlaced = + inst->pic_struct != HFI_INTERLACE_FRAME_PROGRESSIVE ? + true : false; + } else { + params.width = inst->out_width; + params.height = inst->out_height; + params.codec = inst->fmt_cap->pixfmt; + params.hfi_color_fmt = to_hfi_raw_fmt(inst->fmt_out->pixfmt); + params.enc.work_mode = VIDC_WORK_MODE_2; + params.enc.rc_type = HFI_RATE_CONTROL_OFF; + if (enc_ctr->bitrate_mode == V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) + params.enc.rc_type = HFI_RATE_CONTROL_CQ; + params.enc.num_b_frames = enc_ctr->num_b_frames; + params.enc.is_tenbit = inst->bit_depth == VIDC_BITDEPTH_10; + } + + return hfi_plat->bufreq(¶ms, inst->session_type, buftype, req); +} + int venus_helper_get_bufreq(struct venus_inst *inst, u32 type, struct hfi_buffer_requirements *req) { @@ -563,6 +610,10 @@ int venus_helper_get_bufreq(struct venus_inst *inst, u32 type, if (req) memset(req, 0, sizeof(*req)); + ret = platform_get_bufreq(inst, type, req); + if (!ret) + return 0; + ret = hfi_session_get_property(inst, ptype, &hprop); if (ret) return ret; @@ -986,6 +1037,8 @@ u32 venus_helper_get_framesz(u32 v4l2_fmt, u32 width, u32 height) if (compressed) { sz = ALIGN(height, 32) * ALIGN(width, 32) * 3 / 2 / 2; + if (width < 1280 || height < 720) + sz *= 8; return ALIGN(sz, SZ_4K); } @@ -1040,36 +1093,6 @@ int venus_helper_set_work_mode(struct venus_inst *inst, u32 mode) } EXPORT_SYMBOL_GPL(venus_helper_set_work_mode); -int venus_helper_init_codec_freq_data(struct venus_inst *inst) -{ - const struct codec_freq_data *data; - unsigned int i, data_size; - u32 pixfmt; - int ret = 0; - - if (!IS_V4(inst->core)) - return 0; - - data = inst->core->res->codec_freq_data; - data_size = inst->core->res->codec_freq_data_size; - pixfmt = inst->session_type == VIDC_SESSION_TYPE_DEC ? - inst->fmt_out->pixfmt : inst->fmt_cap->pixfmt; - - for (i = 0; i < data_size; i++) { - if (data[i].pixfmt == pixfmt && - data[i].session_type == inst->session_type) { - inst->clk_data.codec_freq_data = &data[i]; - break; - } - } - - if (!inst->clk_data.codec_freq_data) - ret = -EINVAL; - - return ret; -} -EXPORT_SYMBOL_GPL(venus_helper_init_codec_freq_data); - int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int input_bufs, unsigned int output_bufs, unsigned int output2_bufs) @@ -1284,14 +1307,9 @@ int venus_helper_vb2_buf_init(struct vb2_buffer *vb) struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue); struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); struct venus_buffer *buf = to_venus_buffer(vbuf); - struct sg_table *sgt; - - sgt = vb2_dma_sg_plane_desc(vb, 0); - if (!sgt) - return -EFAULT; buf->size = vb2_plane_size(vb, 0); - buf->dma_addr = sg_dma_address(sgt->sgl); + buf->dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) list_add_tail(&buf->reg_list, &inst->registeredbufs); @@ -1343,28 +1361,29 @@ void venus_helper_vb2_buf_queue(struct vb2_buffer *vb) struct v4l2_m2m_ctx *m2m_ctx = inst->m2m_ctx; int ret; - mutex_lock(&inst->lock); - v4l2_m2m_buf_queue(m2m_ctx, vbuf); + /* Skip processing queued capture buffers after LAST flag */ + if (inst->session_type == VIDC_SESSION_TYPE_DEC && + V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type) && + inst->codec_state == VENUS_DEC_STATE_DRC) + return; + cache_payload(inst, vb); if (inst->session_type == VIDC_SESSION_TYPE_ENC && !(inst->streamon_out && inst->streamon_cap)) - goto unlock; + return; if (vb2_start_streaming_called(vb->vb2_queue)) { ret = is_buf_refed(inst, vbuf); if (ret) - goto unlock; + return; ret = session_process_buf(inst, vbuf); if (ret) return_buf_error(inst, vbuf); } - -unlock: - mutex_unlock(&inst->lock); } EXPORT_SYMBOL_GPL(venus_helper_vb2_buf_queue); @@ -1529,6 +1548,29 @@ void venus_helper_m2m_job_abort(void *priv) } EXPORT_SYMBOL_GPL(venus_helper_m2m_job_abort); +int venus_helper_session_init(struct venus_inst *inst) +{ + enum hfi_version version = inst->core->res->hfi_version; + u32 session_type = inst->session_type; + u32 codec; + int ret; + + codec = inst->session_type == VIDC_SESSION_TYPE_DEC ? + inst->fmt_out->pixfmt : inst->fmt_cap->pixfmt; + + ret = hfi_session_init(inst, codec); + if (ret) + return ret; + + inst->clk_data.vpp_freq = hfi_platform_get_codec_vpp_freq(version, codec, + session_type); + inst->clk_data.vsp_freq = hfi_platform_get_codec_vsp_freq(version, codec, + session_type); + + return 0; +} +EXPORT_SYMBOL_GPL(venus_helper_session_init); + void venus_helper_init_instance(struct venus_inst *inst) { if (inst->session_type == VIDC_SESSION_TYPE_DEC) { @@ -1539,7 +1581,7 @@ void venus_helper_init_instance(struct venus_inst *inst) } EXPORT_SYMBOL_GPL(venus_helper_init_instance); -static bool find_fmt_from_caps(struct venus_caps *caps, u32 buftype, u32 fmt) +static bool find_fmt_from_caps(struct hfi_plat_caps *caps, u32 buftype, u32 fmt) { unsigned int i; @@ -1556,7 +1598,7 @@ int venus_helper_get_out_fmts(struct venus_inst *inst, u32 v4l2_fmt, u32 *out_fmt, u32 *out2_fmt, bool ubwc) { struct venus_core *core = inst->core; - struct venus_caps *caps; + struct hfi_plat_caps *caps; u32 ubwc_fmt, fmt = to_hfi_raw_fmt(v4l2_fmt); bool found, found_ubwc; @@ -1620,3 +1662,21 @@ int venus_helper_get_out_fmts(struct venus_inst *inst, u32 v4l2_fmt, return -EINVAL; } EXPORT_SYMBOL_GPL(venus_helper_get_out_fmts); + +int venus_helper_set_stride(struct venus_inst *inst, + unsigned int width, unsigned int height) +{ + const u32 ptype = HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO; + + struct hfi_uncompressed_plane_actual_info plane_actual_info; + + plane_actual_info.buffer_type = HFI_BUFFER_INPUT; + plane_actual_info.num_planes = 2; + plane_actual_info.plane_format[0].actual_stride = width; + plane_actual_info.plane_format[0].actual_plane_buffer_height = height; + plane_actual_info.plane_format[1].actual_stride = width; + plane_actual_info.plane_format[1].actual_plane_buffer_height = height / 2; + + return hfi_session_set_property(inst, ptype, &plane_actual_info); +} +EXPORT_SYMBOL_GPL(venus_helper_set_stride); diff --git a/drivers/media/platform/qcom/venus/helpers.h b/drivers/media/platform/qcom/venus/helpers.h index a4a0562bc83f..351093845499 100644 --- a/drivers/media/platform/qcom/venus/helpers.h +++ b/drivers/media/platform/qcom/venus/helpers.h @@ -33,7 +33,6 @@ int venus_helper_set_output_resolution(struct venus_inst *inst, unsigned int width, unsigned int height, u32 buftype); int venus_helper_set_work_mode(struct venus_inst *inst, u32 mode); -int venus_helper_init_codec_freq_data(struct venus_inst *inst); int venus_helper_set_num_bufs(struct venus_inst *inst, unsigned int input_bufs, unsigned int output_bufs, unsigned int output2_bufs); @@ -48,6 +47,7 @@ unsigned int venus_helper_get_opb_size(struct venus_inst *inst); void venus_helper_acquire_buf_ref(struct vb2_v4l2_buffer *vbuf); void venus_helper_release_buf_ref(struct venus_inst *inst, unsigned int idx); void venus_helper_init_instance(struct venus_inst *inst); +int venus_helper_session_init(struct venus_inst *inst); int venus_helper_get_out_fmts(struct venus_inst *inst, u32 fmt, u32 *out_fmt, u32 *out2_fmt, bool ubwc); int venus_helper_alloc_dpb_bufs(struct venus_inst *inst); @@ -63,4 +63,6 @@ void venus_helper_get_ts_metadata(struct venus_inst *inst, u64 timestamp_us, struct vb2_v4l2_buffer *vbuf); int venus_helper_get_profile_level(struct venus_inst *inst, u32 *profile, u32 *level); int venus_helper_set_profile_level(struct venus_inst *inst, u32 profile, u32 level); +int venus_helper_set_stride(struct venus_inst *inst, unsigned int aligned_width, + unsigned int aligned_height); #endif diff --git a/drivers/media/platform/qcom/venus/hfi.c b/drivers/media/platform/qcom/venus/hfi.c index 638ed5cfe05e..0f2482367e06 100644 --- a/drivers/media/platform/qcom/venus/hfi.c +++ b/drivers/media/platform/qcom/venus/hfi.c @@ -175,6 +175,8 @@ static int wait_session_msg(struct venus_inst *inst) int hfi_session_create(struct venus_inst *inst, const struct hfi_inst_ops *ops) { struct venus_core *core = inst->core; + bool max; + int ret; if (!ops) return -EINVAL; @@ -184,11 +186,19 @@ int hfi_session_create(struct venus_inst *inst, const struct hfi_inst_ops *ops) inst->ops = ops; mutex_lock(&core->lock); - list_add_tail(&inst->list, &core->instances); - atomic_inc(&core->insts_count); + + max = atomic_add_unless(&core->insts_count, 1, + core->max_sessions_supported); + if (!max) { + ret = -EAGAIN; + } else { + list_add_tail(&inst->list, &core->instances); + ret = 0; + } + mutex_unlock(&core->lock); - return 0; + return ret; } EXPORT_SYMBOL_GPL(hfi_session_create); @@ -211,7 +221,7 @@ int hfi_session_init(struct venus_inst *inst, u32 pixfmt) mutex_unlock(&core->lock); if (inst->state != INST_UNINIT) - return -EINVAL; + return -EALREADY; inst->hfi_codec = to_codec_type(pixfmt); reinit_completion(&inst->done); diff --git a/drivers/media/platform/qcom/venus/hfi_cmds.c b/drivers/media/platform/qcom/venus/hfi_cmds.c index 7022368c1e63..4f7565834469 100644 --- a/drivers/media/platform/qcom/venus/hfi_cmds.c +++ b/drivers/media/platform/qcom/venus/hfi_cmds.c @@ -1205,6 +1205,18 @@ pkt_session_set_property_4xx(struct hfi_session_set_property_pkt *pkt, pkt->shdr.hdr.size += sizeof(u32) + sizeof(*cu); break; } + case HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO: { + struct hfi_uncompressed_plane_actual_info *in = pdata; + struct hfi_uncompressed_plane_actual_info *info = prop_data; + + info->buffer_type = in->buffer_type; + info->num_planes = in->num_planes; + info->plane_format[0] = in->plane_format[0]; + if (in->num_planes > 1) + info->plane_format[1] = in->plane_format[1]; + pkt->shdr.hdr.size += sizeof(u32) + sizeof(*info); + break; + } case HFI_PROPERTY_CONFIG_VENC_MAX_BITRATE: case HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER: case HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE: diff --git a/drivers/media/platform/qcom/venus/hfi_helper.h b/drivers/media/platform/qcom/venus/hfi_helper.h index 60ee2479f7a6..6b524c7cde5f 100644 --- a/drivers/media/platform/qcom/venus/hfi_helper.h +++ b/drivers/media/platform/qcom/venus/hfi_helper.h @@ -364,6 +364,13 @@ #define HFI_HEVC_TIER_MAIN 0x1 #define HFI_HEVC_TIER_HIGH0 0x2 +#define HFI_VPX_PROFILE_MAIN 0x00000001 + +#define HFI_VPX_LEVEL_VERSION_0 0x00000001 +#define HFI_VPX_LEVEL_VERSION_1 0x00000002 +#define HFI_VPX_LEVEL_VERSION_2 0x00000004 +#define HFI_VPX_LEVEL_VERSION_3 0x00000008 + /* VP9 Profile 0, 8-bit */ #define HFI_VP9_PROFILE_P0 0x00000001 /* VP9 Profile 2, 10-bit */ @@ -571,7 +578,18 @@ struct hfi_bitrate { #define HFI_CAPABILITY_LCU_SIZE 0x14 #define HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS 0x15 #define HFI_CAPABILITY_MBS_PER_SECOND_POWERSAVE 0x16 +#define HFI_CAPABILITY_I_FRAME_QP 0x20 +#define HFI_CAPABILITY_P_FRAME_QP 0x21 +#define HFI_CAPABILITY_B_FRAME_QP 0x22 +#define HFI_CAPABILITY_RATE_CONTROL_MODES 0x23 +#define HFI_CAPABILITY_BLUR_WIDTH 0x24 +#define HFI_CAPABILITY_BLUR_HEIGHT 0x25 +#define HFI_CAPABILITY_SLICE_BYTE 0x27 +#define HFI_CAPABILITY_SLICE_MB 0x28 #define HFI_CAPABILITY_MAX_VIDEOCORES 0x2b +#define HFI_CAPABILITY_MAX_WORKMODES 0x2c +#define HFI_CAPABILITY_ROTATION 0x2f +#define HFI_CAPABILITY_COLOR_SPACE_CONVERSION 0x30 struct hfi_capability { u32 capability_type; @@ -908,13 +926,13 @@ struct hfi_uncompressed_plane_actual { struct hfi_uncompressed_plane_actual_info { u32 buffer_type; u32 num_planes; - struct hfi_uncompressed_plane_actual plane_format[1]; + struct hfi_uncompressed_plane_actual plane_format[2]; }; struct hfi_uncompressed_plane_actual_constraints_info { u32 buffer_type; u32 num_planes; - struct hfi_uncompressed_plane_constraints plane_format[1]; + struct hfi_uncompressed_plane_constraints plane_format[2]; }; struct hfi_codec_supported { diff --git a/drivers/media/platform/qcom/venus/hfi_parser.c b/drivers/media/platform/qcom/venus/hfi_parser.c index 363ee2a65453..7263c0c32695 100644 --- a/drivers/media/platform/qcom/venus/hfi_parser.c +++ b/drivers/media/platform/qcom/venus/hfi_parser.c @@ -11,12 +11,12 @@ #include "hfi_helper.h" #include "hfi_parser.h" -typedef void (*func)(struct venus_caps *cap, const void *data, +typedef void (*func)(struct hfi_plat_caps *cap, const void *data, unsigned int size); static void init_codecs(struct venus_core *core) { - struct venus_caps *caps = core->caps, *cap; + struct hfi_plat_caps *caps = core->caps, *cap; unsigned long bit; for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { @@ -34,11 +34,11 @@ static void init_codecs(struct venus_core *core) } } -static void for_each_codec(struct venus_caps *caps, unsigned int caps_num, +static void for_each_codec(struct hfi_plat_caps *caps, unsigned int caps_num, u32 codecs, u32 domain, func cb, void *data, unsigned int size) { - struct venus_caps *cap; + struct hfi_plat_caps *cap; unsigned int i; for (i = 0; i < caps_num; i++) { @@ -51,7 +51,7 @@ static void for_each_codec(struct venus_caps *caps, unsigned int caps_num, } static void -fill_buf_mode(struct venus_caps *cap, const void *data, unsigned int num) +fill_buf_mode(struct hfi_plat_caps *cap, const void *data, unsigned int num) { const u32 *type = data; @@ -81,7 +81,7 @@ parse_alloc_mode(struct venus_core *core, u32 codecs, u32 domain, void *data) } } -static void fill_profile_level(struct venus_caps *cap, const void *data, +static void fill_profile_level(struct hfi_plat_caps *cap, const void *data, unsigned int num) { const struct hfi_profile_level *pl = data; @@ -107,7 +107,7 @@ parse_profile_level(struct venus_core *core, u32 codecs, u32 domain, void *data) } static void -fill_caps(struct venus_caps *cap, const void *data, unsigned int num) +fill_caps(struct hfi_plat_caps *cap, const void *data, unsigned int num) { const struct hfi_capability *caps = data; @@ -132,7 +132,7 @@ parse_caps(struct venus_core *core, u32 codecs, u32 domain, void *data) fill_caps, caps_arr, num_caps); } -static void fill_raw_fmts(struct venus_caps *cap, const void *fmts, +static void fill_raw_fmts(struct hfi_plat_caps *cap, const void *fmts, unsigned int num_fmts) { const struct raw_formats *formats = fmts; @@ -211,7 +211,7 @@ static void parser_init(struct venus_inst *inst, u32 *codecs, u32 *domain) static void parser_fini(struct venus_inst *inst, u32 codecs, u32 domain) { - struct venus_caps *caps, *cap; + struct hfi_plat_caps *caps, *cap; unsigned int i; u32 dom; @@ -228,11 +228,49 @@ static void parser_fini(struct venus_inst *inst, u32 codecs, u32 domain) } } +static int hfi_platform_parser(struct venus_core *core, struct venus_inst *inst) +{ + const struct hfi_platform *plat; + const struct hfi_plat_caps *caps = NULL; + u32 enc_codecs, dec_codecs, count = 0; + unsigned int entries; + + if (inst) + return 0; + + plat = hfi_platform_get(core->res->hfi_version); + if (!plat) + return -EINVAL; + + if (plat->codecs) + plat->codecs(&enc_codecs, &dec_codecs, &count); + + if (plat->capabilities) + caps = plat->capabilities(&entries); + + if (!caps || !entries || !count) + return -EINVAL; + + core->enc_codecs = enc_codecs; + core->dec_codecs = dec_codecs; + core->codecs_count = count; + core->max_sessions_supported = MAX_SESSIONS; + memset(core->caps, 0, sizeof(*caps) * MAX_CODEC_NUM); + memcpy(core->caps, caps, sizeof(*caps) * entries); + + return 0; +} + u32 hfi_parser(struct venus_core *core, struct venus_inst *inst, void *buf, u32 size) { unsigned int words_count = size >> 2; u32 *word = buf, *data, codecs = 0, domain = 0; + int ret; + + ret = hfi_platform_parser(core, inst); + if (!ret) + return HFI_ERR_NONE; if (size % 4) return HFI_ERR_SYS_INSUFFICIENT_RESOURCES; @@ -276,6 +314,9 @@ u32 hfi_parser(struct venus_core *core, struct venus_inst *inst, void *buf, words_count--; } + if (!core->max_sessions_supported) + core->max_sessions_supported = MAX_SESSIONS; + parser_fini(inst, codecs, domain); return HFI_ERR_NONE; diff --git a/drivers/media/platform/qcom/venus/hfi_parser.h b/drivers/media/platform/qcom/venus/hfi_parser.h index 264e6dd2415f..5751d0140700 100644 --- a/drivers/media/platform/qcom/venus/hfi_parser.h +++ b/drivers/media/platform/qcom/venus/hfi_parser.h @@ -16,7 +16,7 @@ static inline u32 get_cap(struct venus_inst *inst, u32 type, u32 which) { struct venus_core *core = inst->core; struct hfi_capability *cap = NULL; - struct venus_caps *caps; + struct hfi_plat_caps *caps; unsigned int i; caps = venus_caps_by_codec(core, inst->hfi_codec, inst->session_type); @@ -112,4 +112,9 @@ static inline u32 core_num_max(struct venus_inst *inst) return cap_max(inst, HFI_CAPABILITY_MAX_VIDEOCORES); } +static inline u32 mbs_per_frame_max(struct venus_inst *inst) +{ + return cap_max(inst, HFI_CAPABILITY_MBS_PER_FRAME); +} + #endif diff --git a/drivers/media/platform/qcom/venus/hfi_plat_bufs.h b/drivers/media/platform/qcom/venus/hfi_plat_bufs.h new file mode 100644 index 000000000000..52a51a3b964a --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_plat_bufs.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __HFI_PLATFORM_BUFFERS_H__ +#define __HFI_PLATFORM_BUFFERS_H__ + +#include <linux/types.h> +#include "hfi_helper.h" + +struct hfi_plat_buffers_params { + u32 width; + u32 height; + u32 codec; + u32 hfi_color_fmt; + enum hfi_version version; + u32 num_vpp_pipes; + union { + struct { + u32 max_mbs_per_frame; + u32 buffer_size_limit; + bool is_secondary_output; + bool is_interlaced; + } dec; + struct { + u32 work_mode; + u32 rc_type; + u32 num_b_frames; + bool is_tenbit; + } enc; + }; +}; + +int hfi_plat_bufreq_v6(struct hfi_plat_buffers_params *params, u32 session_type, + u32 buftype, struct hfi_buffer_requirements *bufreq); + +#endif diff --git a/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c b/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c new file mode 100644 index 000000000000..d43d1a53e72d --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_plat_bufs_v6.c @@ -0,0 +1,1317 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include <linux/kernel.h> +#include <linux/sizes.h> +#include <linux/videodev2.h> + +#include "hfi.h" +#include "hfi_plat_bufs.h" +#include "helpers.h" + +#define MIN_INPUT_BUFFERS 4 +#define MIN_ENC_OUTPUT_BUFFERS 4 + +#define NV12_UBWC_Y_TILE_WIDTH 32 +#define NV12_UBWC_Y_TILE_HEIGHT 8 +#define NV12_UBWC_UV_TILE_WIDTH 16 +#define NV12_UBWC_UV_TILE_HEIGHT 8 +#define TP10_UBWC_Y_TILE_WIDTH 48 +#define TP10_UBWC_Y_TILE_HEIGHT 4 +#define METADATA_STRIDE_MULTIPLE 64 +#define METADATA_HEIGHT_MULTIPLE 16 +#define HFI_DMA_ALIGNMENT 256 + +#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64 +#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64 +#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64 +#define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 +#define MAX_FE_NBR_DATA_CB_LINE_BUFFER_SIZE 320 +#define MAX_FE_NBR_DATA_CR_LINE_BUFFER_SIZE 320 + +#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE (128 / 8) +#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8) +#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8) + +#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE (64 * 2 * 3) +#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE (32 * 2 * 3) +#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE (16 * 2 * 3) + +#define MAX_TILE_COLUMNS 32 /* 8K/256 */ + +#define NUM_HW_PIC_BUF 10 +#define BIN_BUFFER_THRESHOLD (1280 * 736) +#define H264D_MAX_SLICE 1800 +/* sizeof(h264d_buftab_t) aligned to 256 */ +#define SIZE_H264D_BUFTAB_T 256 +/* sizeof(h264d_hw_pic_t) aligned to 32 */ +#define SIZE_H264D_HW_PIC_T BIT(11) +#define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4) +#define SIZE_H264D_VPP_CMD_PER_BUF 512 + +/* Line Buffer definitions, One for Luma and 1/2 for each Chroma */ +#define SIZE_H264D_LB_FE_TOP_DATA(width, height) \ + (MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN((width), 16) * 3) + +#define SIZE_H264D_LB_FE_TOP_CTRL(width, height) \ + (MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * (((width) + 15) >> 4)) + +#define SIZE_H264D_LB_FE_LEFT_CTRL(width, height) \ + (MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * (((height) + 15) >> 4)) + +#define SIZE_H264D_LB_SE_TOP_CTRL(width, height) \ + (MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * (((width) + 15) >> 4)) + +#define SIZE_H264D_LB_SE_LEFT_CTRL(width, height) \ + (MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * (((height) + 15) >> 4)) + +#define SIZE_H264D_LB_PE_TOP_DATA(width, height) \ + (MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * (((width) + 15) >> 4)) + +#define SIZE_H264D_LB_VSP_TOP(width, height) (((((width) + 15) >> 4) << 7)) + +#define SIZE_H264D_LB_RECON_DMA_METADATA_WR(width, height) \ + (ALIGN((height), 16) * 32) + +#define SIZE_H264D_QP(width, height) \ + ((((width) + 63) >> 6) * (((height) + 63) >> 6) * 128) + +#define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf)) + +#define H264_CABAC_HDR_RATIO_HD_TOT 1 +#define H264_CABAC_RES_RATIO_HD_TOT 3 + +/* + * Some content need more bin buffer, but limit buffer + * size for high resolution + */ +#define NUM_SLIST_BUF_H264 (256 + 32) +#define SIZE_SLIST_BUF_H264 512 +#define LCU_MAX_SIZE_PELS 64 +#define LCU_MIN_SIZE_PELS 16 + +#define H265D_MAX_SLICE 600 +#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T +#define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32)) +#define SIZE_H265D_VPP_CMD_PER_BUF 256 + +#define SIZE_H265D_LB_FE_TOP_DATA(width, height) \ + (MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * (ALIGN(width, 64) + 8) * 2) + +#define SIZE_H265D_LB_FE_TOP_CTRL(width, height) \ + (MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * \ + (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) + +#define SIZE_H265D_LB_FE_LEFT_CTRL(width, height) \ + (MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * \ + (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS)) + +#define SIZE_H265D_LB_SE_TOP_CTRL(width, height) \ + ((LCU_MAX_SIZE_PELS / 8 * (128 / 8)) * (((width) + 15) >> 4)) + +static inline u32 size_h265d_lb_se_left_ctrl(u32 width, u32 height) +{ + u32 x, y, z; + + x = ((height + 16 - 1) / 8) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; + y = ((height + 32 - 1) / 8) * MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE; + z = ((height + 64 - 1) / 8) * MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE; + + return max3(x, y, z); +} + +#define SIZE_H265D_LB_PE_TOP_DATA(width, height) \ + (MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * \ + (ALIGN(width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS)) + +#define SIZE_H265D_LB_VSP_TOP(width, height) ((((width) + 63) >> 6) * 128) + +#define SIZE_H265D_LB_VSP_LEFT(width, height) ((((height) + 63) >> 6) * 128) + +#define SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height) \ + SIZE_H264D_LB_RECON_DMA_METADATA_WR(width, height) + +#define SIZE_H265D_QP(width, height) SIZE_H264D_QP(width, height) + +#define H265_CABAC_HDR_RATIO_HD_TOT 2 +#define H265_CABAC_RES_RATIO_HD_TOT 2 + +/* + * Some content need more bin buffer, but limit buffer size + * for high resolution + */ +#define SIZE_SLIST_BUF_H265 BIT(10) +#define NUM_SLIST_BUF_H265 (80 + 20) +#define H265_NUM_TILE_COL 32 +#define H265_NUM_TILE_ROW 128 +#define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1) + +static inline u32 size_vpxd_lb_fe_left_ctrl(u32 width, u32 height) +{ + u32 x, y, z; + + x = ((height + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; + y = ((height + 31) >> 5) * MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE; + z = ((height + 63) >> 6) * MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE; + + return max3(x, y, z); +} + +#define SIZE_VPXD_LB_FE_TOP_CTRL(width, height) \ + (((ALIGN(width, 64) + 8) * 10 * 2)) /* small line */ +#define SIZE_VPXD_LB_SE_TOP_CTRL(width, height) \ + ((((width) + 15) >> 4) * MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE) + +static inline u32 size_vpxd_lb_se_left_ctrl(u32 width, u32 height) +{ + u32 x, y, z; + + x = ((height + 15) >> 4) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE; + y = ((height + 31) >> 5) * MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE; + z = ((height + 63) >> 6) * MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE; + + return max3(x, y, z); +} + +#define SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height) \ + ALIGN((ALIGN(height, 16) / (4 / 2)) * 64, 32) +#define SIZE_VP8D_LB_FE_TOP_DATA(width, height) \ + ((ALIGN(width, 16) + 8) * 10 * 2) +#define SIZE_VP9D_LB_FE_TOP_DATA(width, height) \ + ((ALIGN(ALIGN(width, 16), 64) + 8) * 10 * 2) +#define SIZE_VP8D_LB_PE_TOP_DATA(width, height) \ + ((ALIGN(width, 16) >> 4) * 64) +#define SIZE_VP9D_LB_PE_TOP_DATA(width, height) \ + ((ALIGN(ALIGN(width, 16), 64) >> 6) * 176) +#define SIZE_VP8D_LB_VSP_TOP(width, height) \ + (((ALIGN(width, 16) >> 4) * 64 / 2) + 256) +#define SIZE_VP9D_LB_VSP_TOP(width, height) \ + (((ALIGN(ALIGN(width, 16), 64) >> 6) * 64 * 8) + 256) + +#define HFI_IRIS2_VP9D_COMV_SIZE \ + ((((8192 + 63) >> 6) * ((4320 + 63) >> 6) * 8 * 8 * 2 * 8)) + +#define VPX_DECODER_FRAME_CONCURENCY_LVL 2 +#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_NUM 1 +#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_DEN 2 +#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_NUM 3 +#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_DEN 2 + +#define VP8_NUM_FRAME_INFO_BUF (5 + 1) +#define VP9_NUM_FRAME_INFO_BUF (8 + 2 + 1 + 8) +#define VP8_NUM_PROBABILITY_TABLE_BUF VP8_NUM_FRAME_INFO_BUF +#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) +#define VP8_PROB_TABLE_SIZE 3840 +#define VP9_PROB_TABLE_SIZE 3840 + +#define VP9_UDC_HEADER_BUF_SIZE (3 * 128) +#define MAX_SUPERFRAME_HEADER_LEN 34 +#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, 32) + +#define QMATRIX_SIZE (sizeof(u32) * 128 + 256) +#define MP2D_QPDUMP_SIZE 115200 +#define HFI_IRIS2_ENC_PERSIST_SIZE 102400 +#define HFI_MAX_COL_FRAME 6 +#define HFI_VENUS_VENC_TRE_WB_BUFF_SIZE (65 << 4) /* in Bytes */ +#define HFI_VENUS_VENC_DB_LINE_BUFF_PER_MB 512 +#define HFI_VENUS_VPPSG_MAX_REGISTERS 2048 +#define HFI_VENUS_WIDTH_ALIGNMENT 128 +#define HFI_VENUS_WIDTH_TEN_BIT_ALIGNMENT 192 +#define HFI_VENUS_HEIGHT_ALIGNMENT 32 + +#define SYSTEM_LAL_TILE10 192 +#define NUM_MBS_720P (((1280 + 15) >> 4) * ((720 + 15) >> 4)) +#define NUM_MBS_4K (((4096 + 15) >> 4) * ((2304 + 15) >> 4)) +#define MB_SIZE_IN_PIXEL (16 * 16) +#define HDR10PLUS_PAYLOAD_SIZE 1024 +#define HDR10_HIST_EXTRADATA_SIZE 4096 + +static u32 size_vpss_lb(u32 width, u32 height, u32 num_vpp_pipes) +{ + u32 vpss_4tap_top_buffer_size, vpss_div2_top_buffer_size; + u32 vpss_4tap_left_buffer_size, vpss_div2_left_buffer_size; + u32 opb_wr_top_line_luma_buf_size, opb_wr_top_line_chroma_buf_size; + u32 opb_lb_wr_llb_y_buffer_size, opb_lb_wr_llb_uv_buffer_size; + u32 macrotiling_size; + u32 size = 0; + + vpss_4tap_top_buffer_size = 0; + vpss_div2_top_buffer_size = 0; + vpss_4tap_left_buffer_size = 0; + vpss_div2_left_buffer_size = 0; + + macrotiling_size = 32; + opb_wr_top_line_luma_buf_size = + ALIGN(width, macrotiling_size) / macrotiling_size * 256; + opb_wr_top_line_luma_buf_size = + ALIGN(opb_wr_top_line_luma_buf_size, HFI_DMA_ALIGNMENT) + + (MAX_TILE_COLUMNS - 1) * 256; + opb_wr_top_line_luma_buf_size = + max(opb_wr_top_line_luma_buf_size, (32 * ALIGN(height, 16))); + opb_wr_top_line_chroma_buf_size = opb_wr_top_line_luma_buf_size; + opb_lb_wr_llb_y_buffer_size = ALIGN((ALIGN(height, 16) / 2) * 64, 32); + opb_lb_wr_llb_uv_buffer_size = opb_lb_wr_llb_y_buffer_size; + size = num_vpp_pipes * + 2 * (vpss_4tap_top_buffer_size + vpss_div2_top_buffer_size) + + 2 * (vpss_4tap_left_buffer_size + vpss_div2_left_buffer_size) + + opb_wr_top_line_luma_buf_size + + opb_wr_top_line_chroma_buf_size + + opb_lb_wr_llb_uv_buffer_size + + opb_lb_wr_llb_y_buffer_size; + + return size; +} + +static u32 size_h264d_hw_bin_buffer(u32 width, u32 height) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + u32 size = 0; + u32 product; + + product = width * height; + size_yuv = (product <= BIN_BUFFER_THRESHOLD) ? + ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); + + size_bin_hdr = size_yuv * H264_CABAC_HDR_RATIO_HD_TOT; + size_bin_res = size_yuv * H264_CABAC_RES_RATIO_HD_TOT; + size_bin_hdr = ALIGN(size_bin_hdr, HFI_DMA_ALIGNMENT); + size_bin_res = ALIGN(size_bin_res, HFI_DMA_ALIGNMENT); + size = size_bin_hdr + size_bin_res; + + return size; +} + +static u32 h264d_scratch_size(u32 width, u32 height, bool is_interlaced) +{ + u32 aligned_width = ALIGN(width, 16); + u32 aligned_height = ALIGN(height, 16); + u32 size = 0; + + if (!is_interlaced) + size = size_h264d_hw_bin_buffer(aligned_width, aligned_height); + + return size; +} + +static u32 size_h265d_hw_bin_buffer(u32 width, u32 height) +{ + u32 size_yuv, size_bin_hdr, size_bin_res; + u32 size = 0; + u32 product; + + product = width * height; + size_yuv = (product <= BIN_BUFFER_THRESHOLD) ? + ((BIN_BUFFER_THRESHOLD * 3) >> 1) : ((product * 3) >> 1); + size_bin_hdr = size_yuv * H265_CABAC_HDR_RATIO_HD_TOT; + size_bin_res = size_yuv * H265_CABAC_RES_RATIO_HD_TOT; + size_bin_hdr = ALIGN(size_bin_hdr, HFI_DMA_ALIGNMENT); + size_bin_res = ALIGN(size_bin_res, HFI_DMA_ALIGNMENT); + size = size_bin_hdr + size_bin_res; + + return size; +} + +static u32 h265d_scratch_size(u32 width, u32 height, bool is_interlaced) +{ + u32 aligned_width = ALIGN(width, 16); + u32 aligned_height = ALIGN(height, 16); + u32 size = 0; + + if (!is_interlaced) + size = size_h265d_hw_bin_buffer(aligned_width, aligned_height); + + return size; +} + +static u32 vpxd_scratch_size(u32 width, u32 height, bool is_interlaced) +{ + u32 aligned_width = ALIGN(width, 16); + u32 aligned_height = ALIGN(height, 16); + u32 size_yuv = aligned_width * aligned_height * 3 / 2; + u32 size = 0; + + if (!is_interlaced) { + u32 binbuffer1_size, binbufer2_size; + + binbuffer1_size = max_t(u32, size_yuv, + ((BIN_BUFFER_THRESHOLD * 3) >> 1)); + binbuffer1_size *= VPX_DECODER_FRAME_CONCURENCY_LVL * + VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_NUM / + VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO_DEN; + binbufer2_size = max_t(u32, size_yuv, + ((BIN_BUFFER_THRESHOLD * 3) >> 1)); + binbufer2_size *= VPX_DECODER_FRAME_CONCURENCY_LVL * + VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_NUM / + VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO_DEN; + size = ALIGN(binbuffer1_size + binbufer2_size, + HFI_DMA_ALIGNMENT); + } + + return size; +} + +static u32 mpeg2d_scratch_size(u32 width, u32 height, bool is_interlaced) +{ + return 0; +} + +static u32 calculate_enc_output_frame_size(u32 width, u32 height, u32 rc_type) +{ + u32 aligned_width, aligned_height; + u32 mbs_per_frame; + u32 frame_size; + + /* + * Encoder output size calculation: 32 Align width/height + * For resolution < 720p : YUVsize * 4 + * For resolution > 720p & <= 4K : YUVsize / 2 + * For resolution > 4k : YUVsize / 4 + * Initially frame_size = YUVsize * 2; + */ + aligned_width = ALIGN(width, 32); + aligned_height = ALIGN(height, 32); + mbs_per_frame = (ALIGN(aligned_height, 16) * + ALIGN(aligned_width, 16)) / 256; + frame_size = width * height * 3; + + if (mbs_per_frame < NUM_MBS_720P) + frame_size = frame_size << 1; + else if (mbs_per_frame <= NUM_MBS_4K) + frame_size = frame_size >> 2; + else + frame_size = frame_size >> 3; + + if (rc_type == HFI_RATE_CONTROL_OFF || rc_type == HFI_RATE_CONTROL_CQ) + frame_size = frame_size << 1; + + /* + * In case of opaque color format bitdepth will be known + * with first ETB, buffers allocated already with 8 bit + * won't be sufficient for 10 bit + * calculate size considering 10-bit by default + * For 10-bit cases size = size * 1.25 + */ + frame_size *= 5; + frame_size /= 4; + + return ALIGN(frame_size, SZ_4K); +} + +static u32 calculate_enc_scratch_size(u32 width, u32 height, u32 work_mode, + u32 lcu_size, u32 num_vpp_pipes, + u32 rc_type) +{ + u32 aligned_width, aligned_height, bitstream_size; + u32 total_bitbin_buffers, size_single_pipe, bitbin_size; + u32 sao_bin_buffer_size, padded_bin_size, size; + + aligned_width = ALIGN(width, lcu_size); + aligned_height = ALIGN(height, lcu_size); + bitstream_size = + calculate_enc_output_frame_size(width, height, rc_type); + + bitstream_size = ALIGN(bitstream_size, HFI_DMA_ALIGNMENT); + + if (work_mode == VIDC_WORK_MODE_2) { + total_bitbin_buffers = 3; + bitbin_size = bitstream_size * 17 / 10; + bitbin_size = ALIGN(bitbin_size, HFI_DMA_ALIGNMENT); + } else { + total_bitbin_buffers = 1; + bitstream_size = aligned_width * aligned_height * 3; + bitbin_size = ALIGN(bitstream_size, HFI_DMA_ALIGNMENT); + } + + if (num_vpp_pipes > 2) + size_single_pipe = bitbin_size / 2; + else + size_single_pipe = bitbin_size; + + size_single_pipe = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT); + sao_bin_buffer_size = + (64 * (((width + 32) * (height + 32)) >> 10)) + 384; + padded_bin_size = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT); + size_single_pipe = sao_bin_buffer_size + padded_bin_size; + size_single_pipe = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT); + bitbin_size = size_single_pipe * num_vpp_pipes; + size = ALIGN(bitbin_size, HFI_DMA_ALIGNMENT) * + total_bitbin_buffers + 512; + + return size; +} + +static u32 h264e_scratch_size(u32 width, u32 height, u32 work_mode, + u32 num_vpp_pipes, u32 rc_type) +{ + return calculate_enc_scratch_size(width, height, work_mode, 16, + num_vpp_pipes, rc_type); +} + +static u32 h265e_scratch_size(u32 width, u32 height, u32 work_mode, + u32 num_vpp_pipes, u32 rc_type) +{ + return calculate_enc_scratch_size(width, height, work_mode, 32, + num_vpp_pipes, rc_type); +} + +static u32 vp8e_scratch_size(u32 width, u32 height, u32 work_mode, + u32 num_vpp_pipes, u32 rc_type) +{ + return calculate_enc_scratch_size(width, height, work_mode, 16, + num_vpp_pipes, rc_type); +} + +static u32 hfi_iris2_h264d_comv_size(u32 width, u32 height, + u32 yuv_buf_min_count) +{ + u32 frame_width_in_mbs = ((width + 15) >> 4); + u32 frame_height_in_mbs = ((height + 15) >> 4); + u32 col_mv_aligned_width = (frame_width_in_mbs << 6); + u32 col_zero_aligned_width = (frame_width_in_mbs << 2); + u32 col_zero_size = 0, size_colloc = 0, comv_size = 0; + + col_mv_aligned_width = ALIGN(col_mv_aligned_width, 16); + col_zero_aligned_width = ALIGN(col_zero_aligned_width, 16); + col_zero_size = + col_zero_aligned_width * ((frame_height_in_mbs + 1) >> 1); + col_zero_size = ALIGN(col_zero_size, 64); + col_zero_size <<= 1; + col_zero_size = ALIGN(col_zero_size, 512); + size_colloc = col_mv_aligned_width * ((frame_height_in_mbs + 1) >> 1); + size_colloc = ALIGN(size_colloc, 64); + size_colloc <<= 1; + size_colloc = ALIGN(size_colloc, 512); + size_colloc += (col_zero_size + SIZE_H264D_BUFTAB_T * 2); + comv_size = size_colloc * yuv_buf_min_count; + comv_size += 512; + + return comv_size; +} + +static u32 size_h264d_bse_cmd_buf(u32 height) +{ + u32 aligned_height = ALIGN(height, 32); + + return min_t(u32, (((aligned_height + 15) >> 4) * 3 * 4), + H264D_MAX_SLICE) * SIZE_H264D_BSE_CMD_PER_BUF; +} + +static u32 size_h264d_vpp_cmd_buf(u32 height) +{ + u32 aligned_height = ALIGN(height, 32); + + return min_t(u32, (((aligned_height + 15) >> 4) * 3 * 4), + H264D_MAX_SLICE) * SIZE_H264D_VPP_CMD_PER_BUF; +} + +static u32 hfi_iris2_h264d_non_comv_size(u32 width, u32 height, + u32 num_vpp_pipes) +{ + u32 size_bse, size_vpp, size; + + size_bse = size_h264d_bse_cmd_buf(height); + size_vpp = size_h264d_vpp_cmd_buf(height); + size = + ALIGN(size_bse, HFI_DMA_ALIGNMENT) + + ALIGN(size_vpp, HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_FE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_FE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_FE_LEFT_CTRL(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_H264D_LB_SE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_SE_LEFT_CTRL(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_H264D_LB_PE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H264D_LB_RECON_DMA_METADATA_WR(width, height), + HFI_DMA_ALIGNMENT) * 2 + + ALIGN(SIZE_H264D_QP(width, height), HFI_DMA_ALIGNMENT); + + return ALIGN(size, HFI_DMA_ALIGNMENT); +} + +static u32 size_h265d_bse_cmd_buf(u32 width, u32 height) +{ + u32 size; + + size = (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + NUM_HW_PIC_BUF; + size = min_t(u32, size, H265D_MAX_SLICE + 1); + size = 2 * size * SIZE_H265D_BSE_CMD_PER_BUF; + + return ALIGN(size, HFI_DMA_ALIGNMENT); +} + +static u32 size_h265d_vpp_cmd_buf(u32 width, u32 height) +{ + u32 size; + + size = (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + NUM_HW_PIC_BUF; + size = min_t(u32, size, H265D_MAX_SLICE + 1); + size = ALIGN(size, 4); + size = 2 * size * SIZE_H265D_VPP_CMD_PER_BUF; + + return ALIGN(size, HFI_DMA_ALIGNMENT); +} + +static u32 hfi_iris2_h265d_comv_size(u32 width, u32 height, + u32 yuv_buf_count_min) +{ + u32 size; + + size = ALIGN(((((width + 15) >> 4) * ((height + 15) >> 4)) << 8), 512); + size *= yuv_buf_count_min; + size += 512; + + return size; +} + +static u32 hfi_iris2_h265d_non_comv_size(u32 width, u32 height, + u32 num_vpp_pipes) +{ + u32 size_bse, size_vpp, size; + + size_bse = size_h265d_bse_cmd_buf(width, height); + size_vpp = size_h265d_vpp_cmd_buf(width, height); + size = + ALIGN(size_bse, HFI_DMA_ALIGNMENT) + + ALIGN(size_vpp, HFI_DMA_ALIGNMENT) + + ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, HFI_DMA_ALIGNMENT) + + ALIGN(2 * sizeof(u16) * + (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) * + (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_FE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_FE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_FE_LEFT_CTRL(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_h265d_lb_se_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_H265D_LB_SE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_PE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_H265D_LB_VSP_LEFT(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height), + HFI_DMA_ALIGNMENT) + * 4 + + ALIGN(SIZE_H265D_QP(width, height), HFI_DMA_ALIGNMENT); + + return ALIGN(size, HFI_DMA_ALIGNMENT); +} + +static u32 hfi_iris2_vp8d_comv_size(u32 width, u32 height, + u32 yuv_min_buf_count) +{ + return (((width + 15) >> 4) * ((height + 15) >> 4) * 8 * 2); +} + +static u32 h264d_scratch1_size(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes) +{ + u32 co_mv_size, nonco_mv_size, vpss_lb_size = 0; + + co_mv_size = hfi_iris2_h264d_comv_size(width, height, min_buf_count); + nonco_mv_size = hfi_iris2_h264d_non_comv_size(width, height, + num_vpp_pipes); + if (split_mode_enabled) + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); + + return co_mv_size + nonco_mv_size + vpss_lb_size; +} + +static u32 h265d_scratch1_size(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes) +{ + u32 co_mv_size, nonco_mv_size, vpss_lb_size = 0; + + co_mv_size = hfi_iris2_h265d_comv_size(width, height, min_buf_count); + nonco_mv_size = hfi_iris2_h265d_non_comv_size(width, height, + num_vpp_pipes); + if (split_mode_enabled) + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); + + return co_mv_size + nonco_mv_size + vpss_lb_size + + HDR10_HIST_EXTRADATA_SIZE; +} + +static u32 vp8d_scratch1_size(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes) +{ + u32 vpss_lb_size = 0, size; + + size = hfi_iris2_vp8d_comv_size(width, height, 0); + size += ALIGN(size_vpxd_lb_fe_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_vpxd_lb_se_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP8D_LB_PE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT); + if (split_mode_enabled) + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); + + size += vpss_lb_size; + + return size; +} + +static u32 vp9d_scratch1_size(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes) +{ + u32 vpss_lb_size = 0; + u32 size; + + size = + ALIGN(size_vpxd_lb_fe_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_vpxd_lb_se_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_VP9D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP9D_LB_PE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP9D_LB_FE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT); + + if (split_mode_enabled) + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); + + size += vpss_lb_size + HDR10_HIST_EXTRADATA_SIZE; + + return size; +} + +static u32 mpeg2d_scratch1_size(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes) +{ + u32 vpss_lb_size = 0; + u32 size; + + size = + ALIGN(size_vpxd_lb_fe_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(size_vpxd_lb_se_left_ctrl(width, height), + HFI_DMA_ALIGNMENT) * num_vpp_pipes + + ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP8D_LB_PE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT) + + ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height), + HFI_DMA_ALIGNMENT); + + if (split_mode_enabled) + vpss_lb_size = size_vpss_lb(width, height, num_vpp_pipes); + + size += vpss_lb_size; + + return size; +} + +static u32 +calculate_enc_scratch1_size(u32 width, u32 height, u32 lcu_size, u32 num_ref, + bool ten_bit, u32 num_vpp_pipes, bool is_h265) +{ + u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size; + u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE; + u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size; + u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size; + u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size; + u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size; + u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize; + u32 h265e_lcubitmap_bufsize, se_stats_bufsize; + u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize; + u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size; + u32 width_lcu_num, height_lcu_num, width_coded, height_coded; + u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao; + u32 size, bit_depth, num_lcu_mb; + u32 vpss_line_buffer_size_1; + + width_lcu_num = (width + lcu_size - 1) / lcu_size; + height_lcu_num = (height + lcu_size - 1) / lcu_size; + frame_num_lcu = width_lcu_num * height_lcu_num; + width_coded = width_lcu_num * lcu_size; + height_coded = height_lcu_num * lcu_size; + num_lcu_mb = (height_coded / lcu_size) * + ((width_coded + lcu_size * 8) / lcu_size); + slice_info_bufsize = 256 + (frame_num_lcu << 4); + slice_info_bufsize = ALIGN(slice_info_bufsize, HFI_DMA_ALIGNMENT); + line_buf_ctrl_size = ALIGN(width_coded, HFI_DMA_ALIGNMENT); + line_buf_ctrl_size_buffid2 = ALIGN(width_coded, HFI_DMA_ALIGNMENT); + + bit_depth = ten_bit ? 10 : 8; + line_buf_data_size = + (((((bit_depth * width_coded + 1024) + + (HFI_DMA_ALIGNMENT - 1)) & (~(HFI_DMA_ALIGNMENT - 1))) * 1) + + (((((bit_depth * width_coded + 1024) >> 1) + + (HFI_DMA_ALIGNMENT - 1)) & (~(HFI_DMA_ALIGNMENT - 1))) * 2)); + + leftline_buf_ctrl_size = is_h265 ? + ((height_coded + 32) / 32 * 4 * 16) : + ((height_coded + 15) / 16 * 5 * 16); + + if (num_vpp_pipes > 1) { + leftline_buf_ctrl_size += 512; + leftline_buf_ctrl_size = + ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes; + } + + leftline_buf_ctrl_size = + ALIGN(leftline_buf_ctrl_size, HFI_DMA_ALIGNMENT); + leftline_buf_recon_pix_size = (((ten_bit + 1) * 2 * + (height_coded) + HFI_DMA_ALIGNMENT) + + (HFI_DMA_ALIGNMENT << (num_vpp_pipes - 1)) - 1) & + (~((HFI_DMA_ALIGNMENT << (num_vpp_pipes - 1)) - 1)) * 1; + + topline_buf_ctrl_size_FE = is_h265 ? (64 * (width_coded >> 5)) : + (HFI_DMA_ALIGNMENT + 16 * (width_coded >> 4)); + topline_buf_ctrl_size_FE = + ALIGN(topline_buf_ctrl_size_FE, HFI_DMA_ALIGNMENT); + leftline_buf_ctrl_size_FE = + (((HFI_DMA_ALIGNMENT + 64 * (height_coded >> 4)) + + (HFI_DMA_ALIGNMENT << (num_vpp_pipes - 1)) - 1) & + (~((HFI_DMA_ALIGNMENT << (num_vpp_pipes - 1)) - 1)) * 1) * + num_vpp_pipes; + leftline_buf_meta_recony = (HFI_DMA_ALIGNMENT + 64 * + ((height_coded) / (8 * (ten_bit ? 4 : 8)))); + leftline_buf_meta_recony = + ALIGN(leftline_buf_meta_recony, HFI_DMA_ALIGNMENT); + leftline_buf_meta_recony = leftline_buf_meta_recony * num_vpp_pipes; + linebuf_meta_recon_uv = (HFI_DMA_ALIGNMENT + 64 * + ((height_coded) / (4 * (ten_bit ? 4 : 8)))); + linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, HFI_DMA_ALIGNMENT); + linebuf_meta_recon_uv = linebuf_meta_recon_uv * num_vpp_pipes; + line_buf_recon_pix_size = ((ten_bit ? 3 : 2) * width_coded); + line_buf_recon_pix_size = + ALIGN(line_buf_recon_pix_size, HFI_DMA_ALIGNMENT); + slice_cmd_buffer_size = ALIGN(20480, HFI_DMA_ALIGNMENT); + sps_pps_slice_hdr = 2048 + 4096; + col_mv_buf_size = is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) : + (3 * 16 * (width_lcu_num * height_lcu_num + 32)); + col_mv_buf_size = + ALIGN(col_mv_buf_size, HFI_DMA_ALIGNMENT) * (num_ref + 1); + h265e_colrcbuf_size = + (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); + if (num_vpp_pipes > 1) + h265e_colrcbuf_size = + ALIGN(h265e_colrcbuf_size, HFI_DMA_ALIGNMENT) * + num_vpp_pipes; + + h265e_colrcbuf_size = ALIGN(h265e_colrcbuf_size, HFI_DMA_ALIGNMENT) * + HFI_MAX_COL_FRAME; + h265e_framerc_bufsize = (is_h265) ? (256 + 16 * + (14 + (((height_coded >> 5) + 7) >> 3))) : + (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3))); + h265e_framerc_bufsize *= 6; /* multiply by max numtilescol */ + if (num_vpp_pipes > 1) + h265e_framerc_bufsize = + ALIGN(h265e_framerc_bufsize, HFI_DMA_ALIGNMENT) * + num_vpp_pipes; + + h265e_framerc_bufsize = ALIGN(h265e_framerc_bufsize, 512) * + HFI_MAX_COL_FRAME; + h265e_lcubitcnt_bufsize = 256 + 4 * frame_num_lcu; + h265e_lcubitcnt_bufsize = + ALIGN(h265e_lcubitcnt_bufsize, HFI_DMA_ALIGNMENT); + h265e_lcubitmap_bufsize = 256 + (frame_num_lcu >> 3); + h265e_lcubitmap_bufsize = + ALIGN(h265e_lcubitmap_bufsize, HFI_DMA_ALIGNMENT); + line_buf_sde_size = 256 + 16 * (width_coded >> 4); + line_buf_sde_size = ALIGN(line_buf_sde_size, HFI_DMA_ALIGNMENT); + if ((width_coded * height_coded) > (4096 * 2160)) + se_stats_bufsize = 0; + else if ((width_coded * height_coded) > (1920 * 1088)) + se_stats_bufsize = (40 * 4 * frame_num_lcu + 256 + 256); + else + se_stats_bufsize = (1024 * frame_num_lcu + 256 + 256); + + se_stats_bufsize = ALIGN(se_stats_bufsize, HFI_DMA_ALIGNMENT) * 2; + bse_slice_cmd_buffer_size = (((8192 << 2) + 7) & (~7)) * 6; + bse_reg_buffer_size = (((512 << 3) + 7) & (~7)) * 4; + vpp_reg_buffer_size = + (((HFI_VENUS_VPPSG_MAX_REGISTERS << 3) + 31) & (~31)) * 10; + lambda_lut_size = 256 * 11; + override_buffer_size = 16 * ((num_lcu_mb + 7) >> 3); + override_buffer_size = + ALIGN(override_buffer_size, HFI_DMA_ALIGNMENT) * 2; + ir_buffer_size = (((frame_num_lcu << 1) + 7) & (~7)) * 3; + vpss_line_buffer_size_1 = (((8192 >> 2) << 5) * num_vpp_pipes) + 64; + vpss_line_buf = + (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) * + 16) + vpss_line_buffer_size_1; + topline_bufsize_fe_1stg_sao = 16 * (width_coded >> 5); + topline_bufsize_fe_1stg_sao = + ALIGN(topline_bufsize_fe_1stg_sao, HFI_DMA_ALIGNMENT); + + size = + line_buf_ctrl_size + line_buf_data_size + + line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size + + vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE + + leftline_buf_ctrl_size_FE + line_buf_recon_pix_size + + leftline_buf_recon_pix_size + + leftline_buf_meta_recony + linebuf_meta_recon_uv + + h265e_colrcbuf_size + h265e_framerc_bufsize + + h265e_lcubitcnt_bufsize + h265e_lcubitmap_bufsize + + line_buf_sde_size + + topline_bufsize_fe_1stg_sao + override_buffer_size + + bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr + + slice_cmd_buffer_size + bse_slice_cmd_buffer_size + + ir_buffer_size + slice_info_bufsize + lambda_lut_size + + se_stats_bufsize + 1024; + + return size; +} + +static u32 h264e_scratch1_size(u32 width, u32 height, u32 num_ref, bool ten_bit, + u32 num_vpp_pipes) +{ + return calculate_enc_scratch1_size(width, height, 16, num_ref, ten_bit, + num_vpp_pipes, false); +} + +static u32 h265e_scratch1_size(u32 width, u32 height, u32 num_ref, bool ten_bit, + u32 num_vpp_pipes) +{ + return calculate_enc_scratch1_size(width, height, 32, num_ref, ten_bit, + num_vpp_pipes, true); +} + +static u32 vp8e_scratch1_size(u32 width, u32 height, u32 num_ref, bool ten_bit, + u32 num_vpp_pipes) +{ + return calculate_enc_scratch1_size(width, height, 16, num_ref, ten_bit, + 1, false); +} + +static u32 ubwc_metadata_plane_stride(u32 width, u32 metadata_stride_multi, + u32 tile_width_pels) +{ + return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels), + metadata_stride_multi); +} + +static u32 ubwc_metadata_plane_bufheight(u32 height, u32 metadata_height_multi, + u32 tile_height_pels) +{ + return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels), + metadata_height_multi); +} + +static u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride, + u32 metadata_buf_height) +{ + return ALIGN(metadata_stride * metadata_buf_height, SZ_4K); +} + +static u32 enc_scratch2_size(u32 width, u32 height, u32 num_ref, bool ten_bit) +{ + u32 aligned_width, aligned_height, chroma_height, ref_buf_height; + u32 luma_size, chroma_size; + u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c; + u32 ref_luma_stride_bytes, ref_chroma_height_bytes; + u32 ref_buf_size, ref_stride; + u32 size; + + if (!ten_bit) { + aligned_height = ALIGN(height, HFI_VENUS_HEIGHT_ALIGNMENT); + chroma_height = height >> 1; + chroma_height = ALIGN(chroma_height, + HFI_VENUS_HEIGHT_ALIGNMENT); + aligned_width = ALIGN(width, HFI_VENUS_WIDTH_ALIGNMENT); + metadata_stride = + ubwc_metadata_plane_stride(width, 64, + NV12_UBWC_Y_TILE_WIDTH); + meta_buf_height = + ubwc_metadata_plane_bufheight(height, 16, + NV12_UBWC_Y_TILE_HEIGHT); + meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + size = (aligned_height + chroma_height) * aligned_width + + meta_size_y + meta_size_c; + size = (size * (num_ref + 3)) + 4096; + } else { + ref_buf_height = (height + (HFI_VENUS_HEIGHT_ALIGNMENT - 1)) + & (~(HFI_VENUS_HEIGHT_ALIGNMENT - 1)); + ref_luma_stride_bytes = + ((width + SYSTEM_LAL_TILE10 - 1) / SYSTEM_LAL_TILE10) * + SYSTEM_LAL_TILE10; + ref_stride = 4 * (ref_luma_stride_bytes / 3); + ref_stride = (ref_stride + (128 - 1)) & (~(128 - 1)); + luma_size = ref_buf_height * ref_stride; + ref_chroma_height_bytes = (((height + 1) >> 1) + + (32 - 1)) & (~(32 - 1)); + chroma_size = ref_stride * ref_chroma_height_bytes; + luma_size = (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); + chroma_size = (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); + ref_buf_size = luma_size + chroma_size; + metadata_stride = + ubwc_metadata_plane_stride(width, + METADATA_STRIDE_MULTIPLE, + TP10_UBWC_Y_TILE_WIDTH); + meta_buf_height = + ubwc_metadata_plane_bufheight(height, + METADATA_HEIGHT_MULTIPLE, + TP10_UBWC_Y_TILE_HEIGHT); + meta_size_y = ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + meta_size_c = ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + size = ref_buf_size + meta_size_y + meta_size_c; + size = (size * (num_ref + 3)) + 4096; + } + + return size; +} + +static u32 enc_persist_size(void) +{ + return HFI_IRIS2_ENC_PERSIST_SIZE; +} + +static u32 h264d_persist1_size(void) +{ + return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264), + HFI_DMA_ALIGNMENT); +} + +static u32 h265d_persist1_size(void) +{ + return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_TILE + * sizeof(u32)), HFI_DMA_ALIGNMENT); +} + +static u32 vp8d_persist1_size(void) +{ + return ALIGN(VP8_NUM_PROBABILITY_TABLE_BUF * VP8_PROB_TABLE_SIZE, + HFI_DMA_ALIGNMENT); +} + +static u32 vp9d_persist1_size(void) +{ + return + ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, + HFI_DMA_ALIGNMENT) + + ALIGN(HFI_IRIS2_VP9D_COMV_SIZE, HFI_DMA_ALIGNMENT) + + ALIGN(MAX_SUPERFRAME_HEADER_LEN, HFI_DMA_ALIGNMENT) + + ALIGN(VP9_UDC_HEADER_BUF_SIZE, HFI_DMA_ALIGNMENT) + + ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE, + HFI_DMA_ALIGNMENT); +} + +static u32 mpeg2d_persist1_size(void) +{ + return QMATRIX_SIZE + MP2D_QPDUMP_SIZE; +} + +struct dec_bufsize_ops { + u32 (*scratch)(u32 width, u32 height, bool is_interlaced); + u32 (*scratch1)(u32 width, u32 height, u32 min_buf_count, + bool split_mode_enabled, u32 num_vpp_pipes); + u32 (*persist1)(void); +}; + +struct enc_bufsize_ops { + u32 (*scratch)(u32 width, u32 height, u32 work_mode, u32 num_vpp_pipes, + u32 rc_type); + u32 (*scratch1)(u32 width, u32 height, u32 num_ref, bool ten_bit, + u32 num_vpp_pipes); + u32 (*scratch2)(u32 width, u32 height, u32 num_ref, bool ten_bit); + u32 (*persist)(void); +}; + +static struct dec_bufsize_ops dec_h264_ops = { + .scratch = h264d_scratch_size, + .scratch1 = h264d_scratch1_size, + .persist1 = h264d_persist1_size, +}; + +static struct dec_bufsize_ops dec_h265_ops = { + .scratch = h265d_scratch_size, + .scratch1 = h265d_scratch1_size, + .persist1 = h265d_persist1_size, +}; + +static struct dec_bufsize_ops dec_vp8_ops = { + .scratch = vpxd_scratch_size, + .scratch1 = vp8d_scratch1_size, + .persist1 = vp8d_persist1_size, +}; + +static struct dec_bufsize_ops dec_vp9_ops = { + .scratch = vpxd_scratch_size, + .scratch1 = vp9d_scratch1_size, + .persist1 = vp9d_persist1_size, +}; + +static struct dec_bufsize_ops dec_mpeg2_ops = { + .scratch = mpeg2d_scratch_size, + .scratch1 = mpeg2d_scratch1_size, + .persist1 = mpeg2d_persist1_size, +}; + +static struct enc_bufsize_ops enc_h264_ops = { + .scratch = h264e_scratch_size, + .scratch1 = h264e_scratch1_size, + .scratch2 = enc_scratch2_size, + .persist = enc_persist_size, +}; + +static struct enc_bufsize_ops enc_h265_ops = { + .scratch = h265e_scratch_size, + .scratch1 = h265e_scratch1_size, + .scratch2 = enc_scratch2_size, + .persist = enc_persist_size, +}; + +static struct enc_bufsize_ops enc_vp8_ops = { + .scratch = vp8e_scratch_size, + .scratch1 = vp8e_scratch1_size, + .scratch2 = enc_scratch2_size, + .persist = enc_persist_size, +}; + +static u32 +calculate_dec_input_frame_size(u32 width, u32 height, u32 codec, + u32 max_mbs_per_frame, u32 buffer_size_limit) +{ + u32 frame_size, num_mbs; + u32 div_factor = 1; + u32 base_res_mbs = NUM_MBS_4K; + + /* + * Decoder input size calculation: + * If clip is 8k buffer size is calculated for 8k : 8k mbs/4 + * For 8k cases we expect width/height to be set always. + * In all other cases size is calculated for 4k: + * 4k mbs for VP8/VP9 and 4k/2 for remaining codecs + */ + num_mbs = (ALIGN(height, 16) * ALIGN(width, 16)) / 256; + if (num_mbs > NUM_MBS_4K) { + div_factor = 4; + base_res_mbs = max_mbs_per_frame; + } else { + base_res_mbs = NUM_MBS_4K; + if (codec == V4L2_PIX_FMT_VP9) + div_factor = 1; + else + div_factor = 2; + } + + frame_size = base_res_mbs * MB_SIZE_IN_PIXEL * 3 / 2 / div_factor; + + /* multiply by 10/8 (1.25) to get size for 10 bit case */ + if (codec == V4L2_PIX_FMT_VP9 || codec == V4L2_PIX_FMT_HEVC) + frame_size = frame_size + (frame_size >> 2); + + if (buffer_size_limit && buffer_size_limit < frame_size) + frame_size = buffer_size_limit; + + return ALIGN(frame_size, SZ_4K); +} + +static int output_buffer_count(u32 session_type, u32 codec) +{ + u32 output_min_count; + + if (session_type == VIDC_SESSION_TYPE_DEC) { + switch (codec) { + case V4L2_PIX_FMT_MPEG2: + case V4L2_PIX_FMT_VP8: + output_min_count = 6; + break; + case V4L2_PIX_FMT_VP9: + output_min_count = 9; + break; + case V4L2_PIX_FMT_H264: + case V4L2_PIX_FMT_HEVC: + default: + output_min_count = 8; + break; + } + } else { + output_min_count = MIN_ENC_OUTPUT_BUFFERS; + } + + return output_min_count; +} + +static int bufreq_dec(struct hfi_plat_buffers_params *params, u32 buftype, + struct hfi_buffer_requirements *bufreq) +{ + enum hfi_version version = params->version; + u32 codec = params->codec; + u32 width = params->width, height = params->height, out_min_count; + struct dec_bufsize_ops *dec_ops; + bool is_secondary_output = params->dec.is_secondary_output; + bool is_interlaced = params->dec.is_interlaced; + u32 max_mbs_per_frame = params->dec.max_mbs_per_frame; + u32 buffer_size_limit = params->dec.buffer_size_limit; + u32 num_vpp_pipes = params->num_vpp_pipes; + + switch (codec) { + case V4L2_PIX_FMT_H264: + dec_ops = &dec_h264_ops; + break; + case V4L2_PIX_FMT_HEVC: + dec_ops = &dec_h265_ops; + break; + case V4L2_PIX_FMT_VP8: + dec_ops = &dec_vp8_ops; + break; + case V4L2_PIX_FMT_VP9: + dec_ops = &dec_vp9_ops; + break; + case V4L2_PIX_FMT_MPEG2: + dec_ops = &dec_mpeg2_ops; + break; + default: + return -EINVAL; + } + + out_min_count = output_buffer_count(VIDC_SESSION_TYPE_DEC, codec); + + bufreq->type = buftype; + bufreq->region_size = 0; + bufreq->count_min = 1; + bufreq->count_actual = 1; + bufreq->hold_count = 1; + bufreq->contiguous = 1; + bufreq->alignment = 256; + + if (buftype == HFI_BUFFER_INPUT) { + bufreq->count_min = MIN_INPUT_BUFFERS; + bufreq->size = + calculate_dec_input_frame_size(width, height, codec, + max_mbs_per_frame, + buffer_size_limit); + } else if (buftype == HFI_BUFFER_OUTPUT || + buftype == HFI_BUFFER_OUTPUT2) { + bufreq->count_min = out_min_count; + bufreq->size = + venus_helper_get_framesz_raw(params->hfi_color_fmt, + width, height); + } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH(version)) { + bufreq->size = dec_ops->scratch(width, height, is_interlaced); + } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH_1(version)) { + bufreq->size = dec_ops->scratch1(width, height, out_min_count, + is_secondary_output, + num_vpp_pipes); + } else if (buftype == HFI_BUFFER_INTERNAL_PERSIST_1) { + bufreq->size = dec_ops->persist1(); + } else { + return -EINVAL; + } + + return 0; +} + +static int bufreq_enc(struct hfi_plat_buffers_params *params, u32 buftype, + struct hfi_buffer_requirements *bufreq) +{ + enum hfi_version version = params->version; + struct enc_bufsize_ops *enc_ops; + u32 width = params->width; + u32 height = params->height; + bool is_tenbit = params->enc.is_tenbit; + u32 num_bframes = params->enc.num_b_frames; + u32 codec = params->codec; + u32 work_mode = params->enc.work_mode; + u32 rc_type = params->enc.rc_type; + u32 num_vpp_pipes = params->num_vpp_pipes; + u32 num_ref; + + switch (codec) { + case V4L2_PIX_FMT_H264: + enc_ops = &enc_h264_ops; + break; + case V4L2_PIX_FMT_HEVC: + enc_ops = &enc_h265_ops; + break; + case V4L2_PIX_FMT_VP8: + enc_ops = &enc_vp8_ops; + break; + default: + return -EINVAL; + } + + num_ref = num_bframes > 0 ? num_bframes + 1 : 1; + + bufreq->type = buftype; + bufreq->region_size = 0; + bufreq->count_min = 1; + bufreq->count_actual = 1; + bufreq->hold_count = 1; + bufreq->contiguous = 1; + bufreq->alignment = 256; + + if (buftype == HFI_BUFFER_INPUT) { + bufreq->count_min = MIN_INPUT_BUFFERS; + bufreq->size = + venus_helper_get_framesz_raw(params->hfi_color_fmt, + width, height); + } else if (buftype == HFI_BUFFER_OUTPUT || + buftype == HFI_BUFFER_OUTPUT2) { + bufreq->count_min = + output_buffer_count(VIDC_SESSION_TYPE_ENC, codec); + bufreq->size = calculate_enc_output_frame_size(width, height, + rc_type); + } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH(version)) { + bufreq->size = enc_ops->scratch(width, height, work_mode, + num_vpp_pipes, rc_type); + } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH_1(version)) { + bufreq->size = enc_ops->scratch1(width, height, num_ref, + is_tenbit, num_vpp_pipes); + } else if (buftype == HFI_BUFFER_INTERNAL_SCRATCH_2(version)) { + bufreq->size = enc_ops->scratch2(width, height, num_ref, + is_tenbit); + } else if (buftype == HFI_BUFFER_INTERNAL_PERSIST) { + bufreq->size = enc_ops->persist(); + } else { + return -EINVAL; + } + + return 0; +} + +int hfi_plat_bufreq_v6(struct hfi_plat_buffers_params *params, u32 session_type, + u32 buftype, struct hfi_buffer_requirements *bufreq) +{ + if (session_type == VIDC_SESSION_TYPE_DEC) + return bufreq_dec(params, buftype, bufreq); + else + return bufreq_enc(params, buftype, bufreq); +} diff --git a/drivers/media/platform/qcom/venus/hfi_platform.c b/drivers/media/platform/qcom/venus/hfi_platform.c new file mode 100644 index 000000000000..8f47804e973f --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_platform.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include "hfi_platform.h" + +const struct hfi_platform *hfi_platform_get(enum hfi_version version) +{ + switch (version) { + case HFI_VERSION_4XX: + return &hfi_plat_v4; + case HFI_VERSION_6XX: + return &hfi_plat_v6; + default: + break; + } + + return NULL; +} + +unsigned long +hfi_platform_get_codec_vpp_freq(enum hfi_version version, u32 codec, u32 session_type) +{ + const struct hfi_platform *plat; + unsigned long freq = 0; + + plat = hfi_platform_get(version); + if (!plat) + return 0; + + if (plat->codec_vpp_freq) + freq = plat->codec_vpp_freq(session_type, codec); + + return freq; +} + +unsigned long +hfi_platform_get_codec_vsp_freq(enum hfi_version version, u32 codec, u32 session_type) +{ + const struct hfi_platform *plat; + unsigned long freq = 0; + + plat = hfi_platform_get(version); + if (!plat) + return 0; + + if (plat->codec_vpp_freq) + freq = plat->codec_vsp_freq(session_type, codec); + + return freq; +} + +u8 hfi_platform_num_vpp_pipes(enum hfi_version version) +{ + const struct hfi_platform *plat; + + plat = hfi_platform_get(version); + if (!plat) + return 0; + + if (plat->num_vpp_pipes) + return plat->num_vpp_pipes(); + + return 0; +} diff --git a/drivers/media/platform/qcom/venus/hfi_platform.h b/drivers/media/platform/qcom/venus/hfi_platform.h new file mode 100644 index 000000000000..3819bb2b36bd --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_platform.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __HFI_PLATFORM_H__ +#define __HFI_PLATFORM_H__ + +#include <linux/types.h> +#include <linux/videodev2.h> + +#include "hfi.h" +#include "hfi_plat_bufs.h" +#include "hfi_helper.h" + +#define MAX_PLANES 4 +#define MAX_FMT_ENTRIES 32 +#define MAX_CAP_ENTRIES 32 +#define MAX_ALLOC_MODE_ENTRIES 16 +#define MAX_CODEC_NUM 32 +#define MAX_SESSIONS 16 + +struct raw_formats { + u32 buftype; + u32 fmt; +}; + +struct hfi_plat_caps { + u32 codec; + u32 domain; + bool cap_bufs_mode_dynamic; + unsigned int num_caps; + struct hfi_capability caps[MAX_CAP_ENTRIES]; + unsigned int num_pl; + struct hfi_profile_level pl[HFI_MAX_PROFILE_COUNT]; + unsigned int num_fmts; + struct raw_formats fmts[MAX_FMT_ENTRIES]; + bool valid; /* used only for Venus v1xx */ +}; + +struct hfi_platform_codec_freq_data { + u32 pixfmt; + u32 session_type; + unsigned long vpp_freq; + unsigned long vsp_freq; +}; + +struct hfi_platform { + unsigned long (*codec_vpp_freq)(u32 session_type, u32 codec); + unsigned long (*codec_vsp_freq)(u32 session_type, u32 codec); + void (*codecs)(u32 *enc_codecs, u32 *dec_codecs, u32 *count); + const struct hfi_plat_caps *(*capabilities)(unsigned int *entries); + u8 (*num_vpp_pipes)(void); + int (*bufreq)(struct hfi_plat_buffers_params *params, u32 session_type, + u32 buftype, struct hfi_buffer_requirements *bufreq); +}; + +extern const struct hfi_platform hfi_plat_v4; +extern const struct hfi_platform hfi_plat_v6; + +const struct hfi_platform *hfi_platform_get(enum hfi_version version); +unsigned long hfi_platform_get_codec_vpp_freq(enum hfi_version version, u32 codec, + u32 session_type); +unsigned long hfi_platform_get_codec_vsp_freq(enum hfi_version version, u32 codec, + u32 session_type); +u8 hfi_platform_num_vpp_pipes(enum hfi_version version); +#endif diff --git a/drivers/media/platform/qcom/venus/hfi_platform_v4.c b/drivers/media/platform/qcom/venus/hfi_platform_v4.c new file mode 100644 index 000000000000..3848bb6d7408 --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_platform_v4.c @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include "hfi_platform.h" + +static const struct hfi_plat_caps caps[] = { +{ + .codec = HFI_VIDEO_CODEC_H264, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_H264_PROFILE_BASELINE, HFI_H264_LEVEL_52}, + .pl[1] = {HFI_H264_PROFILE_MAIN, HFI_H264_LEVEL_52}, + .pl[2] = {HFI_H264_PROFILE_HIGH, HFI_H264_LEVEL_52}, + .pl[3] = {HFI_H264_PROFILE_CONSTRAINED_BASE, HFI_H264_LEVEL_52}, + .pl[4] = {HFI_H264_PROFILE_CONSTRAINED_HIGH, HFI_H264_LEVEL_52}, + .num_pl = 5, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_HEVC, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0 << 28}, + .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0 << 28}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, + .num_fmts = 7, +}, { + .codec = HFI_VIDEO_CODEC_VP8, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_0}, + .pl[1] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_1}, + .pl[2] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_2}, + .pl[3] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_3}, + .num_pl = 4, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_VP9, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_VP9_PROFILE_P0, 200}, + .pl[1] = {HFI_VP9_PROFILE_P2_10B, 200}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, + .num_fmts = 7, +}, { + .codec = HFI_VIDEO_CODEC_MPEG2, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 1920, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 1920, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 8160, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 40000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 244800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 30, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 1, 1}, + .num_caps = 10, + .pl[0] = {HFI_MPEG2_PROFILE_SIMPLE, HFI_MPEG2_LEVEL_H14}, + .pl[1] = {HFI_MPEG2_PROFILE_MAIN, HFI_MPEG2_LEVEL_H14}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_H264, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 4, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 16, 16, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 51, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 51, 1}, + .caps[17] = {HFI_CAPABILITY_B_FRAME_QP, 0, 51, 1}, + .caps[18] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .num_caps = 21, + .pl[0] = {HFI_H264_PROFILE_BASELINE, HFI_H264_LEVEL_52}, + .pl[1] = {HFI_H264_PROFILE_MAIN, HFI_H264_LEVEL_52}, + .pl[2] = {HFI_H264_PROFILE_HIGH, HFI_H264_LEVEL_52}, + .pl[3] = {HFI_H264_PROFILE_CONSTRAINED_BASE, HFI_H264_LEVEL_52}, + .pl[4] = {HFI_H264_PROFILE_CONSTRAINED_HIGH, HFI_H264_LEVEL_52}, + .num_pl = 5, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_HEVC, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 4, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 32, 32, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 63, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 63, 1}, + .caps[17] = {HFI_CAPABILITY_B_FRAME_QP, 0, 63, 1}, + .caps[18] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .caps[21] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, + .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, + .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .num_caps = 24, + .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_VP8, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 240, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 3, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 2, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 16, 16, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 127, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 127, 1}, + .caps[17] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[18] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, + .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[21] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .caps[22] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, + .num_caps = 23, + .pl[0] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_0}, + .pl[1] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_1}, + .pl[2] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_2}, + .pl[3] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_3}, + .num_pl = 4, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +} }; + +static const struct hfi_plat_caps *get_capabilities(unsigned int *entries) +{ + *entries = ARRAY_SIZE(caps); + return caps; +} + +static void get_codecs(u32 *enc_codecs, u32 *dec_codecs, u32 *count) +{ + *enc_codecs = HFI_VIDEO_CODEC_H264 | HFI_VIDEO_CODEC_HEVC | + HFI_VIDEO_CODEC_VP8; + *dec_codecs = HFI_VIDEO_CODEC_H264 | HFI_VIDEO_CODEC_HEVC | + HFI_VIDEO_CODEC_VP8 | HFI_VIDEO_CODEC_VP9 | + HFI_VIDEO_CODEC_MPEG2; + *count = 8; +} + +static const struct hfi_platform_codec_freq_data codec_freq_data[] = { + { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_ENC, 675, 10 }, + { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_ENC, 675, 10 }, + { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_ENC, 675, 10 }, + { V4L2_PIX_FMT_MPEG2, VIDC_SESSION_TYPE_DEC, 200, 10 }, + { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_DEC, 200, 10 }, + { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_DEC, 200, 10 }, + { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_DEC, 200, 10 }, + { V4L2_PIX_FMT_VP9, VIDC_SESSION_TYPE_DEC, 200, 10 }, +}; + +static const struct hfi_platform_codec_freq_data * +get_codec_freq_data(u32 session_type, u32 pixfmt) +{ + const struct hfi_platform_codec_freq_data *data = codec_freq_data; + unsigned int i, data_size = ARRAY_SIZE(codec_freq_data); + const struct hfi_platform_codec_freq_data *found = NULL; + + for (i = 0; i < data_size; i++) { + if (data[i].pixfmt == pixfmt && data[i].session_type == session_type) { + found = &data[i]; + break; + } + } + + return found; +} + +static unsigned long codec_vpp_freq(u32 session_type, u32 codec) +{ + const struct hfi_platform_codec_freq_data *data; + + data = get_codec_freq_data(session_type, codec); + if (data) + return data->vpp_freq; + + return 0; +} + +static unsigned long codec_vsp_freq(u32 session_type, u32 codec) +{ + const struct hfi_platform_codec_freq_data *data; + + data = get_codec_freq_data(session_type, codec); + if (data) + return data->vsp_freq; + + return 0; +} + +const struct hfi_platform hfi_plat_v4 = { + .codec_vpp_freq = codec_vpp_freq, + .codec_vsp_freq = codec_vsp_freq, + .codecs = get_codecs, + .capabilities = get_capabilities, +}; diff --git a/drivers/media/platform/qcom/venus/hfi_platform_v6.c b/drivers/media/platform/qcom/venus/hfi_platform_v6.c new file mode 100644 index 000000000000..2278be13cb90 --- /dev/null +++ b/drivers/media/platform/qcom/venus/hfi_platform_v6.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#include "hfi_platform.h" + +static const struct hfi_plat_caps caps[] = { +{ + .codec = HFI_VIDEO_CODEC_H264, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 5760, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 5760, 1}, + /* ((5760 * 2880) / 256) */ + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 36, 64800, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 200000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 65536, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 65536, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 36, 1958400, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 0, 1, 1}, + .num_caps = 9, + .pl[0] = {HFI_H264_PROFILE_BASELINE, HFI_H264_LEVEL_52}, + .pl[1] = {HFI_H264_PROFILE_MAIN, HFI_H264_LEVEL_52}, + .pl[2] = {HFI_H264_PROFILE_HIGH, HFI_H264_LEVEL_52}, + .pl[3] = {HFI_H264_PROFILE_CONSTRAINED_BASE, HFI_H264_LEVEL_52}, + .pl[4] = {HFI_H264_PROFILE_CONSTRAINED_HIGH, HFI_H264_LEVEL_52}, + .num_pl = 5, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_HEVC, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, + .num_fmts = 7, +}, { + .codec = HFI_VIDEO_CODEC_VP8, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_0}, + .pl[1] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_1}, + .pl[2] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_2}, + .pl[3] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_3}, + .num_pl = 4, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_VP9, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 2073600, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 3, 1}, + .num_caps = 10, + .pl[0] = {HFI_VP9_PROFILE_P0, 200}, + .pl[1] = {HFI_VP9_PROFILE_P2_10B, 200}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[4] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .fmts[5] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_P010}, + .fmts[6] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_YUV420_TP10}, + .num_fmts = 7, +}, { + .codec = HFI_VIDEO_CODEC_MPEG2, + .domain = VIDC_SESSION_TYPE_DEC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 1920, 1}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 1920, 1}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 8160, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 40000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 4096, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 4096, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 244800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 30, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 2, 1}, + .caps[9] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 1, 1}, + .num_caps = 10, + .pl[0] = {HFI_MPEG2_PROFILE_SIMPLE, HFI_MPEG2_LEVEL_H14}, + .pl[1] = {HFI_MPEG2_PROFILE_MAIN, HFI_MPEG2_LEVEL_H14}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_OUTPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[1] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV12}, + .fmts[3] = {HFI_BUFFER_OUTPUT2, HFI_COLOR_FORMAT_NV21}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_H264, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 4, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 16, 16, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 51, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 51, 1}, + .caps[17] = {HFI_CAPABILITY_B_FRAME_QP, 0, 51, 1}, + .caps[18] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .num_caps = 21, + .pl[0] = {HFI_H264_PROFILE_BASELINE, HFI_H264_LEVEL_52}, + .pl[1] = {HFI_H264_PROFILE_MAIN, HFI_H264_LEVEL_52}, + .pl[2] = {HFI_H264_PROFILE_HIGH, HFI_H264_LEVEL_52}, + .pl[3] = {HFI_H264_PROFILE_CONSTRAINED_BASE, HFI_H264_LEVEL_52}, + .pl[4] = {HFI_H264_PROFILE_CONSTRAINED_HIGH, HFI_H264_LEVEL_52}, + .num_pl = 5, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_HEVC, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 480, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 4, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 32, 32, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 63, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 63, 1}, + .caps[17] = {HFI_CAPABILITY_B_FRAME_QP, 0, 63, 1}, + .caps[18] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[19] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[20] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .caps[21] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, + .caps[22] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, + .caps[23] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .num_caps = 24, + .pl[0] = {HFI_HEVC_PROFILE_MAIN, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .pl[1] = {HFI_HEVC_PROFILE_MAIN10, HFI_HEVC_LEVEL_6 | HFI_HEVC_TIER_HIGH0}, + .num_pl = 2, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +}, { + .codec = HFI_VIDEO_CODEC_VP8, + .domain = VIDC_SESSION_TYPE_ENC, + .cap_bufs_mode_dynamic = true, + .caps[0] = {HFI_CAPABILITY_FRAME_WIDTH, 96, 4096, 16}, + .caps[1] = {HFI_CAPABILITY_FRAME_HEIGHT, 96, 4096, 16}, + .caps[2] = {HFI_CAPABILITY_MBS_PER_FRAME, 1, 36864, 1}, + .caps[3] = {HFI_CAPABILITY_BITRATE, 1, 120000000, 1}, + .caps[4] = {HFI_CAPABILITY_SCALE_X, 8192, 65536, 1}, + .caps[5] = {HFI_CAPABILITY_SCALE_Y, 8192, 65536, 1}, + .caps[6] = {HFI_CAPABILITY_MBS_PER_SECOND, 1, 1036800, 1}, + .caps[7] = {HFI_CAPABILITY_FRAMERATE, 1, 240, 1}, + .caps[8] = {HFI_CAPABILITY_MAX_VIDEOCORES, 1, 3, 1}, + .caps[9] = {HFI_CAPABILITY_PEAKBITRATE, 32000, 160000000, 1}, + .caps[10] = {HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS, 0, 3, 1}, + .caps[11] = {HFI_CAPABILITY_ENC_LTR_COUNT, 0, 2, 1}, + .caps[12] = {HFI_CAPABILITY_LCU_SIZE, 16, 16, 1}, + .caps[13] = {HFI_CAPABILITY_BFRAME, 0, 1, 1}, + .caps[14] = {HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS, 0, 5, 1}, + .caps[15] = {HFI_CAPABILITY_I_FRAME_QP, 0, 127, 1}, + .caps[16] = {HFI_CAPABILITY_P_FRAME_QP, 0, 127, 1}, + .caps[17] = {HFI_CAPABILITY_MAX_WORKMODES, 1, 2, 1}, + .caps[18] = {HFI_CAPABILITY_RATE_CONTROL_MODES, 0x1000001, 0x1000005, 1}, + .caps[19] = {HFI_CAPABILITY_BLUR_WIDTH, 96, 4096, 16}, + .caps[20] = {HFI_CAPABILITY_BLUR_HEIGHT, 96, 4096, 16}, + .caps[21] = {HFI_CAPABILITY_COLOR_SPACE_CONVERSION, 0, 2, 1}, + .caps[22] = {HFI_CAPABILITY_ROTATION, 1, 4, 90}, + .num_caps = 23, + .pl[0] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_0}, + .pl[1] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_1}, + .pl[2] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_2}, + .pl[3] = {HFI_VPX_PROFILE_MAIN, HFI_VPX_LEVEL_VERSION_3}, + .num_pl = 4, + .fmts[0] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12}, + .fmts[1] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_NV12_UBWC}, + .fmts[2] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_YUV420_TP10_UBWC}, + .fmts[3] = {HFI_BUFFER_INPUT, HFI_COLOR_FORMAT_P010}, + .num_fmts = 4, +} }; + +static const struct hfi_plat_caps *get_capabilities(unsigned int *entries) +{ + *entries = ARRAY_SIZE(caps); + return caps; +} + +static void get_codecs(u32 *enc_codecs, u32 *dec_codecs, u32 *count) +{ + *enc_codecs = HFI_VIDEO_CODEC_H264 | HFI_VIDEO_CODEC_HEVC | + HFI_VIDEO_CODEC_VP8; + *dec_codecs = HFI_VIDEO_CODEC_H264 | HFI_VIDEO_CODEC_HEVC | + HFI_VIDEO_CODEC_VP8 | HFI_VIDEO_CODEC_VP9 | + HFI_VIDEO_CODEC_MPEG2; + *count = 8; +} + +static const struct hfi_platform_codec_freq_data codec_freq_data[] = { + { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_ENC, 675, 25 }, + { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_ENC, 675, 25 }, + { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_ENC, 675, 60 }, + { V4L2_PIX_FMT_MPEG2, VIDC_SESSION_TYPE_DEC, 200, 25 }, + { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_DEC, 200, 25 }, + { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_DEC, 200, 25 }, + { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_DEC, 200, 60 }, + { V4L2_PIX_FMT_VP9, VIDC_SESSION_TYPE_DEC, 200, 60 }, +}; + +static const struct hfi_platform_codec_freq_data * +get_codec_freq_data(u32 session_type, u32 pixfmt) +{ + const struct hfi_platform_codec_freq_data *data = codec_freq_data; + unsigned int i, data_size = ARRAY_SIZE(codec_freq_data); + const struct hfi_platform_codec_freq_data *found = NULL; + + for (i = 0; i < data_size; i++) { + if (data[i].pixfmt == pixfmt && data[i].session_type == session_type) { + found = &data[i]; + break; + } + } + + return found; +} + +static unsigned long codec_vpp_freq(u32 session_type, u32 codec) +{ + const struct hfi_platform_codec_freq_data *data; + + data = get_codec_freq_data(session_type, codec); + if (data) + return data->vpp_freq; + + return 0; +} + +static unsigned long codec_vsp_freq(u32 session_type, u32 codec) +{ + const struct hfi_platform_codec_freq_data *data; + + data = get_codec_freq_data(session_type, codec); + if (data) + return data->vsp_freq; + + return 0; +} + +static u8 num_vpp_pipes(void) +{ + return 4; +} + +const struct hfi_platform hfi_plat_v6 = { + .codec_vpp_freq = codec_vpp_freq, + .codec_vsp_freq = codec_vsp_freq, + .codecs = get_codecs, + .capabilities = get_capabilities, + .num_vpp_pipes = num_vpp_pipes, + .bufreq = hfi_plat_bufreq_v6, +}; diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index 4be4a75ddcb6..50e03f8fc278 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -372,7 +372,7 @@ static void venus_soft_int(struct venus_hfi_device *hdev) } static int venus_iface_cmdq_write_nolock(struct venus_hfi_device *hdev, - void *pkt) + void *pkt, bool sync) { struct device *dev = hdev->core->dev; struct hfi_pkt_hdr *cmd_packet; @@ -394,18 +394,29 @@ static int venus_iface_cmdq_write_nolock(struct venus_hfi_device *hdev, return ret; } + if (sync) { + /* + * Inform video hardware to raise interrupt for synchronous + * commands + */ + queue = &hdev->queues[IFACEQ_MSG_IDX]; + queue->qhdr->rx_req = 1; + /* ensure rx_req is updated in memory */ + wmb(); + } + if (rx_req) venus_soft_int(hdev); return 0; } -static int venus_iface_cmdq_write(struct venus_hfi_device *hdev, void *pkt) +static int venus_iface_cmdq_write(struct venus_hfi_device *hdev, void *pkt, bool sync) { int ret; mutex_lock(&hdev->lock); - ret = venus_iface_cmdq_write_nolock(hdev, pkt); + ret = venus_iface_cmdq_write_nolock(hdev, pkt, sync); mutex_unlock(&hdev->lock); return ret; @@ -428,7 +439,7 @@ static int venus_hfi_core_set_resource(struct venus_core *core, u32 id, if (ret) return ret; - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -778,7 +789,7 @@ static int venus_sys_set_debug(struct venus_hfi_device *hdev, u32 debug) pkt_sys_debug_config(pkt, HFI_DEBUG_MODE_QUEUE, debug); - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -795,7 +806,7 @@ static int venus_sys_set_coverage(struct venus_hfi_device *hdev, u32 mode) pkt_sys_coverage_config(pkt, mode); - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -816,7 +827,7 @@ static int venus_sys_set_idle_message(struct venus_hfi_device *hdev, pkt_sys_idle_indicator(pkt, enable); - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -834,7 +845,7 @@ static int venus_sys_set_power_control(struct venus_hfi_device *hdev, pkt_sys_power_control(pkt, enable); - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -885,14 +896,14 @@ static int venus_sys_set_default_properties(struct venus_hfi_device *hdev) return ret; } -static int venus_session_cmd(struct venus_inst *inst, u32 pkt_type) +static int venus_session_cmd(struct venus_inst *inst, u32 pkt_type, bool sync) { struct venus_hfi_device *hdev = to_hfi_priv(inst->core); struct hfi_session_pkt pkt; pkt_session_cmd(&pkt, pkt_type, inst); - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, sync); } static void venus_flush_debug_queue(struct venus_hfi_device *hdev) @@ -922,7 +933,7 @@ static int venus_prepare_power_collapse(struct venus_hfi_device *hdev, pkt_sys_pc_prep(&pkt); - ret = venus_iface_cmdq_write(hdev, &pkt); + ret = venus_iface_cmdq_write(hdev, &pkt, false); if (ret) return ret; @@ -1064,13 +1075,13 @@ static int venus_core_init(struct venus_core *core) venus_set_state(hdev, VENUS_STATE_INIT); - ret = venus_iface_cmdq_write(hdev, &pkt); + ret = venus_iface_cmdq_write(hdev, &pkt, false); if (ret) return ret; pkt_sys_image_version(&version_pkt); - ret = venus_iface_cmdq_write(hdev, &version_pkt); + ret = venus_iface_cmdq_write(hdev, &version_pkt, false); if (ret) dev_warn(dev, "failed to send image version pkt to fw\n"); @@ -1099,7 +1110,7 @@ static int venus_core_ping(struct venus_core *core, u32 cookie) pkt_sys_ping(&pkt, cookie); - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, false); } static int venus_core_trigger_ssr(struct venus_core *core, u32 trigger_type) @@ -1112,7 +1123,7 @@ static int venus_core_trigger_ssr(struct venus_core *core, u32 trigger_type) if (ret) return ret; - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, false); } static int venus_session_init(struct venus_inst *inst, u32 session_type, @@ -1130,7 +1141,7 @@ static int venus_session_init(struct venus_inst *inst, u32 session_type, if (ret) goto err; - ret = venus_iface_cmdq_write(hdev, &pkt); + ret = venus_iface_cmdq_write(hdev, &pkt, true); if (ret) goto err; @@ -1151,7 +1162,7 @@ static int venus_session_end(struct venus_inst *inst) dev_warn(dev, "fw coverage msg ON failed\n"); } - return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_END); + return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_END, true); } static int venus_session_abort(struct venus_inst *inst) @@ -1160,7 +1171,7 @@ static int venus_session_abort(struct venus_inst *inst) venus_flush_debug_queue(hdev); - return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_ABORT); + return venus_session_cmd(inst, HFI_CMD_SYS_SESSION_ABORT, true); } static int venus_session_flush(struct venus_inst *inst, u32 flush_mode) @@ -1173,22 +1184,22 @@ static int venus_session_flush(struct venus_inst *inst, u32 flush_mode) if (ret) return ret; - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, true); } static int venus_session_start(struct venus_inst *inst) { - return venus_session_cmd(inst, HFI_CMD_SESSION_START); + return venus_session_cmd(inst, HFI_CMD_SESSION_START, true); } static int venus_session_stop(struct venus_inst *inst) { - return venus_session_cmd(inst, HFI_CMD_SESSION_STOP); + return venus_session_cmd(inst, HFI_CMD_SESSION_STOP, true); } static int venus_session_continue(struct venus_inst *inst) { - return venus_session_cmd(inst, HFI_CMD_SESSION_CONTINUE); + return venus_session_cmd(inst, HFI_CMD_SESSION_CONTINUE, false); } static int venus_session_etb(struct venus_inst *inst, @@ -1205,7 +1216,7 @@ static int venus_session_etb(struct venus_inst *inst, if (ret) return ret; - ret = venus_iface_cmdq_write(hdev, &pkt); + ret = venus_iface_cmdq_write(hdev, &pkt, false); } else if (session_type == VIDC_SESSION_TYPE_ENC) { struct hfi_session_empty_buffer_uncompressed_plane0_pkt pkt; @@ -1213,7 +1224,7 @@ static int venus_session_etb(struct venus_inst *inst, if (ret) return ret; - ret = venus_iface_cmdq_write(hdev, &pkt); + ret = venus_iface_cmdq_write(hdev, &pkt, false); } else { ret = -EINVAL; } @@ -1232,7 +1243,7 @@ static int venus_session_ftb(struct venus_inst *inst, if (ret) return ret; - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, false); } static int venus_session_set_buffers(struct venus_inst *inst, @@ -1252,7 +1263,7 @@ static int venus_session_set_buffers(struct venus_inst *inst, if (ret) return ret; - return venus_iface_cmdq_write(hdev, pkt); + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_session_unset_buffers(struct venus_inst *inst, @@ -1272,17 +1283,17 @@ static int venus_session_unset_buffers(struct venus_inst *inst, if (ret) return ret; - return venus_iface_cmdq_write(hdev, pkt); + return venus_iface_cmdq_write(hdev, pkt, true); } static int venus_session_load_res(struct venus_inst *inst) { - return venus_session_cmd(inst, HFI_CMD_SESSION_LOAD_RESOURCES); + return venus_session_cmd(inst, HFI_CMD_SESSION_LOAD_RESOURCES, true); } static int venus_session_release_res(struct venus_inst *inst) { - return venus_session_cmd(inst, HFI_CMD_SESSION_RELEASE_RESOURCES); + return venus_session_cmd(inst, HFI_CMD_SESSION_RELEASE_RESOURCES, true); } static int venus_session_parse_seq_hdr(struct venus_inst *inst, u32 seq_hdr, @@ -1299,7 +1310,7 @@ static int venus_session_parse_seq_hdr(struct venus_inst *inst, u32 seq_hdr, if (ret) return ret; - ret = venus_iface_cmdq_write(hdev, pkt); + ret = venus_iface_cmdq_write(hdev, pkt, false); if (ret) return ret; @@ -1320,7 +1331,7 @@ static int venus_session_get_seq_hdr(struct venus_inst *inst, u32 seq_hdr, if (ret) return ret; - return venus_iface_cmdq_write(hdev, pkt); + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_session_set_property(struct venus_inst *inst, u32 ptype, @@ -1339,7 +1350,7 @@ static int venus_session_set_property(struct venus_inst *inst, u32 ptype, if (ret) return ret; - return venus_iface_cmdq_write(hdev, pkt); + return venus_iface_cmdq_write(hdev, pkt, false); } static int venus_session_get_property(struct venus_inst *inst, u32 ptype) @@ -1352,7 +1363,7 @@ static int venus_session_get_property(struct venus_inst *inst, u32 ptype) if (ret) return ret; - return venus_iface_cmdq_write(hdev, &pkt); + return venus_iface_cmdq_write(hdev, &pkt, true); } static int venus_resume(struct venus_core *core) @@ -1591,9 +1602,6 @@ int venus_hfi_create(struct venus_core *core) hdev->suspended = true; core->priv = hdev; core->ops = &venus_hfi_ops; - core->core_caps = ENC_ROTATION_CAPABILITY | ENC_SCALING_CAPABILITY | - ENC_DEINTERLACE_CAPABILITY | - DEC_MULTI_STREAM_CAPABILITY; ret = venus_interface_queues_init(hdev); if (ret) diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index a3850261d697..43c4e3d9e281 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -18,6 +18,7 @@ #include "hfi_parser.h" #include "hfi_venus_io.h" #include "pm_helpers.h" +#include "hfi_platform.h" static bool legacy_binding; @@ -510,7 +511,7 @@ min_loaded_core(struct venus_inst *inst, u32 *min_coreid, u32 *min_load) if (inst_pos->state != INST_START) continue; - vpp_freq = inst_pos->clk_data.codec_freq_data->vpp_freq; + vpp_freq = inst_pos->clk_data.vpp_freq; coreid = inst_pos->clk_data.core_id; mbs_per_sec = load_per_instance(inst_pos); @@ -559,7 +560,7 @@ static int decide_core(struct venus_inst *inst) return 0; inst_load = load_per_instance(inst); - inst_load *= inst->clk_data.codec_freq_data->vpp_freq; + inst_load *= inst->clk_data.vpp_freq; max_freq = core->res->freq_tbl[0].freq; min_loaded_core(inst, &min_coreid, &min_load); @@ -773,13 +774,6 @@ static int vcodec_domains_get(struct device *dev) core->pmdomains[i] = pd; } - core->pd_dl_venus = device_link_add(dev, core->pmdomains[0], - DL_FLAG_PM_RUNTIME | - DL_FLAG_STATELESS | - DL_FLAG_RPM_ACTIVE); - if (!core->pd_dl_venus) - return -ENODEV; - skip_pmdomains: if (!core->has_opp_table) return 0; @@ -806,14 +800,12 @@ skip_pmdomains: opp_dl_add_err: dev_pm_opp_detach_genpd(core->opp_table); opp_attach_err: - if (core->pd_dl_venus) { - device_link_del(core->pd_dl_venus); - for (i = 0; i < res->vcodec_pmdomains_num; i++) { - if (IS_ERR_OR_NULL(core->pmdomains[i])) - continue; - dev_pm_domain_detach(core->pmdomains[i], true); - } + for (i = 0; i < res->vcodec_pmdomains_num; i++) { + if (IS_ERR_OR_NULL(core->pmdomains[i])) + continue; + dev_pm_domain_detach(core->pmdomains[i], true); } + return ret; } @@ -826,9 +818,6 @@ static void vcodec_domains_put(struct device *dev) if (!res->vcodec_pmdomains_num) goto skip_pmdomains; - if (core->pd_dl_venus) - device_link_del(core->pd_dl_venus); - for (i = 0; i < res->vcodec_pmdomains_num; i++) { if (IS_ERR_OR_NULL(core->pmdomains[i])) continue; @@ -915,16 +904,30 @@ static void core_put_v4(struct device *dev) static int core_power_v4(struct device *dev, int on) { struct venus_core *core = dev_get_drvdata(dev); + struct device *pmctrl = core->pmdomains[0]; int ret = 0; if (on == POWER_ON) { + if (pmctrl) { + ret = pm_runtime_get_sync(pmctrl); + if (ret < 0) { + pm_runtime_put_noidle(pmctrl); + return ret; + } + } + ret = core_clks_enable(core); + if (ret < 0 && pmctrl) + pm_runtime_put_sync(pmctrl); } else { /* Drop the performance state vote */ if (core->opp_pmdomain) dev_pm_opp_set_rate(dev, 0); core_clks_disable(core); + + if (pmctrl) + pm_runtime_put_sync(pmctrl); } return ret; @@ -939,10 +942,13 @@ static unsigned long calculate_inst_freq(struct venus_inst *inst, mbs_per_sec = load_per_instance(inst); - vpp_freq = mbs_per_sec * inst->clk_data.codec_freq_data->vpp_freq; + if (inst->state != INST_START) + return 0; + + vpp_freq = mbs_per_sec * inst->clk_data.vpp_freq; /* 21 / 20 is overhead factor */ vpp_freq += vpp_freq / 20; - vsp_freq = mbs_per_sec * inst->clk_data.codec_freq_data->vsp_freq; + vsp_freq = mbs_per_sec * inst->clk_data.vsp_freq; /* 10 / 7 is overhead factor */ if (inst->session_type == VIDC_SESSION_TYPE_ENC) diff --git a/drivers/media/platform/qcom/venus/vdec.c b/drivers/media/platform/qcom/venus/vdec.c index 8488411204c3..e4dc97f00fc3 100644 --- a/drivers/media/platform/qcom/venus/vdec.c +++ b/drivers/media/platform/qcom/venus/vdec.c @@ -13,7 +13,7 @@ #include <media/v4l2-event.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-mem2mem.h> -#include <media/videobuf2-dma-sg.h> +#include <media/videobuf2-dma-contig.h> #include "hfi_venus_io.h" #include "hfi_parser.h" @@ -519,8 +519,10 @@ vdec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *cmd) ret = hfi_session_process_buf(inst, &fdata); - if (!ret && inst->codec_state == VENUS_DEC_STATE_DECODING) + if (!ret && inst->codec_state == VENUS_DEC_STATE_DECODING) { inst->codec_state = VENUS_DEC_STATE_DRAIN; + inst->drain_active = true; + } } unlock: @@ -637,6 +639,7 @@ static int vdec_output_conf(struct venus_inst *inst) { struct venus_core *core = inst->core; struct hfi_enable en = { .enable = 1 }; + struct hfi_buffer_requirements bufreq; u32 width = inst->out_width; u32 height = inst->out_height; u32 out_fmt, out2_fmt; @@ -712,6 +715,23 @@ static int vdec_output_conf(struct venus_inst *inst) } if (IS_V3(core) || IS_V4(core)) { + ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT, &bufreq); + if (ret) + return ret; + + if (bufreq.size > inst->output_buf_size) + return -EINVAL; + + if (inst->dpb_fmt) { + ret = venus_helper_get_bufreq(inst, HFI_BUFFER_OUTPUT2, + &bufreq); + if (ret) + return ret; + + if (bufreq.size > inst->output2_buf_size) + return -EINVAL; + } + if (inst->output2_buf_size) { ret = venus_helper_set_bufsize(inst, inst->output2_buf_size, @@ -740,8 +760,8 @@ static int vdec_session_init(struct venus_inst *inst) { int ret; - ret = hfi_session_init(inst, inst->fmt_out->pixfmt); - if (ret == -EINVAL) + ret = venus_helper_session_init(inst); + if (ret == -EALREADY) return 0; else if (ret) return ret; @@ -751,10 +771,6 @@ static int vdec_session_init(struct venus_inst *inst) if (ret) goto deinit; - ret = venus_helper_init_codec_freq_data(inst); - if (ret) - goto deinit; - return 0; deinit: hfi_session_deinit(inst); @@ -917,10 +933,6 @@ static int vdec_start_capture(struct venus_inst *inst) return 0; reconfigure: - ret = hfi_session_flush(inst, HFI_FLUSH_OUTPUT, true); - if (ret) - return ret; - ret = vdec_output_conf(inst); if (ret) return ret; @@ -948,15 +960,21 @@ reconfigure: venus_pm_load_scale(inst); + inst->next_buf_last = false; + ret = hfi_session_continue(inst); if (ret) goto free_dpb_bufs; inst->codec_state = VENUS_DEC_STATE_DECODING; + if (inst->drain_active) + inst->codec_state = VENUS_DEC_STATE_DRAIN; + inst->streamon_cap = 1; inst->sequence_cap = 0; inst->reconfig = false; + inst->drain_active = false; return 0; @@ -972,7 +990,10 @@ static int vdec_start_output(struct venus_inst *inst) if (inst->codec_state == VENUS_DEC_STATE_SEEK) { ret = venus_helper_process_initial_out_bufs(inst); - inst->codec_state = VENUS_DEC_STATE_DECODING; + if (inst->next_buf_last) + inst->codec_state = VENUS_DEC_STATE_DRC; + else + inst->codec_state = VENUS_DEC_STATE_DECODING; goto done; } @@ -988,6 +1009,7 @@ static int vdec_start_output(struct venus_inst *inst) venus_helper_init_instance(inst); inst->sequence_out = 0; inst->reconfig = false; + inst->next_buf_last = false; ret = vdec_set_properties(inst); if (ret) @@ -1077,13 +1099,14 @@ static int vdec_stop_capture(struct venus_inst *inst) ret = hfi_session_flush(inst, HFI_FLUSH_ALL, true); fallthrough; case VENUS_DEC_STATE_DRAIN: - vdec_cancel_dst_buffers(inst); inst->codec_state = VENUS_DEC_STATE_STOPPED; + inst->drain_active = false; + fallthrough; + case VENUS_DEC_STATE_SEEK: + vdec_cancel_dst_buffers(inst); break; case VENUS_DEC_STATE_DRC: - WARN_ON(1); - fallthrough; - case VENUS_DEC_STATE_DRC_FLUSH_DONE: + ret = hfi_session_flush(inst, HFI_FLUSH_OUTPUT, true); inst->codec_state = VENUS_DEC_STATE_CAPTURE_SETUP; venus_helper_free_dpb_bufs(inst); break; @@ -1102,6 +1125,7 @@ static int vdec_stop_output(struct venus_inst *inst) case VENUS_DEC_STATE_DECODING: case VENUS_DEC_STATE_DRAIN: case VENUS_DEC_STATE_STOPPED: + case VENUS_DEC_STATE_DRC: ret = hfi_session_flush(inst, HFI_FLUSH_ALL, true); inst->codec_state = VENUS_DEC_STATE_SEEK; break; @@ -1207,10 +1231,28 @@ static void vdec_buf_cleanup(struct vb2_buffer *vb) static void vdec_vb2_buf_queue(struct vb2_buffer *vb) { struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + static const struct v4l2_event eos = { .type = V4L2_EVENT_EOS }; vdec_pm_get_put(inst); + mutex_lock(&inst->lock); + + if (inst->next_buf_last && V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type) && + inst->codec_state == VENUS_DEC_STATE_DRC) { + vbuf->flags |= V4L2_BUF_FLAG_LAST; + vbuf->sequence = inst->sequence_cap++; + vbuf->field = V4L2_FIELD_NONE; + vb2_set_plane_payload(vb, 0, 0); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_DONE); + v4l2_event_queue_fh(&inst->fh, &eos); + inst->next_buf_last = false; + mutex_unlock(&inst->lock); + return; + } + venus_helper_vb2_buf_queue(vb); + mutex_unlock(&inst->lock); } static const struct vb2_ops vdec_vb2_ops = { @@ -1253,20 +1295,15 @@ static void vdec_buf_done(struct venus_inst *inst, unsigned int buf_type, vb->timestamp = timestamp_us * NSEC_PER_USEC; vbuf->sequence = inst->sequence_cap++; - if (inst->last_buf == vb) { - inst->last_buf = NULL; - vbuf->flags |= V4L2_BUF_FLAG_LAST; - vb2_set_plane_payload(vb, 0, 0); - vb->timestamp = 0; - } - if (vbuf->flags & V4L2_BUF_FLAG_LAST) { const struct v4l2_event ev = { .type = V4L2_EVENT_EOS }; v4l2_event_queue_fh(&inst->fh, &ev); - if (inst->codec_state == VENUS_DEC_STATE_DRAIN) + if (inst->codec_state == VENUS_DEC_STATE_DRAIN) { + inst->drain_active = false; inst->codec_state = VENUS_DEC_STATE_STOPPED; + } } if (!bytesused) @@ -1334,22 +1371,22 @@ static void vdec_event_change(struct venus_inst *inst, if (inst->bit_depth != ev_data->bit_depth) inst->bit_depth = ev_data->bit_depth; + if (inst->pic_struct != ev_data->pic_struct) + inst->pic_struct = ev_data->pic_struct; + dev_dbg(dev, VDBGM "event %s sufficient resources (%ux%u)\n", sufficient ? "" : "not", ev_data->width, ev_data->height); - if (sufficient) { - hfi_session_continue(inst); - } else { - switch (inst->codec_state) { - case VENUS_DEC_STATE_INIT: - inst->codec_state = VENUS_DEC_STATE_CAPTURE_SETUP; - break; - case VENUS_DEC_STATE_DECODING: - inst->codec_state = VENUS_DEC_STATE_DRC; - break; - default: - break; - } + switch (inst->codec_state) { + case VENUS_DEC_STATE_INIT: + inst->codec_state = VENUS_DEC_STATE_CAPTURE_SETUP; + break; + case VENUS_DEC_STATE_DECODING: + case VENUS_DEC_STATE_DRAIN: + inst->codec_state = VENUS_DEC_STATE_DRC; + break; + default: + break; } /* @@ -1358,19 +1395,17 @@ static void vdec_event_change(struct venus_inst *inst, * itself doesn't mark the last decoder output buffer with HFI EOS flag. */ - if (!sufficient && inst->codec_state == VENUS_DEC_STATE_DRC) { - struct vb2_v4l2_buffer *last; + if (inst->codec_state == VENUS_DEC_STATE_DRC) { int ret; - last = v4l2_m2m_last_dst_buf(inst->m2m_ctx); - if (last) - inst->last_buf = &last->vb2_buf; + inst->next_buf_last = true; ret = hfi_session_flush(inst, HFI_FLUSH_OUTPUT, false); if (ret) dev_dbg(dev, VDBGH "flush output error %d\n", ret); } + inst->next_buf_last = true; inst->reconfig = true; v4l2_event_queue_fh(&inst->fh, &ev); wake_up(&inst->reconf_wait); @@ -1413,8 +1448,7 @@ static void vdec_event_notify(struct venus_inst *inst, u32 event, static void vdec_flush_done(struct venus_inst *inst) { - if (inst->codec_state == VENUS_DEC_STATE_DRC) - inst->codec_state = VENUS_DEC_STATE_DRC_FLUSH_DONE; + dev_dbg(inst->core->dev_dec, VDBGH "flush done\n"); } static const struct hfi_inst_ops vdec_hfi_ops = { @@ -1461,7 +1495,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->io_modes = VB2_MMAP | VB2_DMABUF; src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->ops = &vdec_vb2_ops; - src_vq->mem_ops = &vb2_dma_sg_memops; + src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->drv_priv = inst; src_vq->buf_struct_size = sizeof(struct venus_buffer); src_vq->allow_zero_bytesused = 1; @@ -1475,7 +1509,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->ops = &vdec_vb2_ops; - dst_vq->mem_ops = &vb2_dma_sg_memops; + dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->drv_priv = inst; dst_vq->buf_struct_size = sizeof(struct venus_buffer); dst_vq->allow_zero_bytesused = 1; @@ -1508,6 +1542,7 @@ static int vdec_open(struct file *file) inst->clk_data.core_id = VIDC_CORE_ID_DEFAULT; inst->core_acquired = false; inst->bit_depth = VIDC_BITDEPTH_8; + inst->pic_struct = HFI_INTERLACE_FRAME_PROGRESSIVE; init_waitqueue_head(&inst->reconf_wait); venus_helper_init_instance(inst); diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c index 1c61602c5de1..6976ed553647 100644 --- a/drivers/media/platform/qcom/venus/venc.c +++ b/drivers/media/platform/qcom/venus/venc.c @@ -10,7 +10,7 @@ #include <linux/pm_runtime.h> #include <linux/slab.h> #include <media/v4l2-mem2mem.h> -#include <media/videobuf2-dma-sg.h> +#include <media/videobuf2-dma-contig.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-event.h> #include <media/v4l2-ctrls.h> @@ -190,8 +190,10 @@ venc_try_fmt_common(struct venus_inst *inst, struct v4l2_format *f) pixmp->height = clamp(pixmp->height, frame_height_min(inst), frame_height_max(inst)); - if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + pixmp->width = ALIGN(pixmp->width, 128); pixmp->height = ALIGN(pixmp->height, 32); + } pixmp->width = ALIGN(pixmp->width, 2); pixmp->height = ALIGN(pixmp->height, 2); @@ -335,13 +337,13 @@ venc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) switch (s->target) { case V4L2_SEL_TGT_CROP_DEFAULT: case V4L2_SEL_TGT_CROP_BOUNDS: - s->r.width = inst->width; - s->r.height = inst->height; - break; - case V4L2_SEL_TGT_CROP: s->r.width = inst->out_width; s->r.height = inst->out_height; break; + case V4L2_SEL_TGT_CROP: + s->r.width = inst->width; + s->r.height = inst->height; + break; default: return -EINVAL; } @@ -360,12 +362,19 @@ venc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) return -EINVAL; + if (s->r.width > inst->out_width || + s->r.height > inst->out_height) + return -EINVAL; + + s->r.width = ALIGN(s->r.width, 2); + s->r.height = ALIGN(s->r.height, 2); + switch (s->target) { case V4L2_SEL_TGT_CROP: - if (s->r.width != inst->out_width || - s->r.height != inst->out_height || - s->r.top != 0 || s->r.left != 0) - return -EINVAL; + s->r.top = 0; + s->r.left = 0; + inst->width = s->r.width; + inst->height = s->r.height; break; default: return -EINVAL; @@ -536,6 +545,7 @@ static int venc_set_properties(struct venus_inst *inst) struct hfi_idr_period idrp; struct hfi_quantization quant; struct hfi_quantization_range quant_range; + struct hfi_enable en; u32 ptype, rate_control, bitrate; u32 profile, level; int ret; @@ -588,16 +598,19 @@ static int venc_set_properties(struct venus_inst *inst) return ret; } - /* IDR periodicity, n: - * n = 0 - only the first I-frame is IDR frame - * n = 1 - all I-frames will be IDR frames - * n > 1 - every n-th I-frame will be IDR frame - */ - ptype = HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD; - idrp.idr_period = 0; - ret = hfi_session_set_property(inst, ptype, &idrp); - if (ret) - return ret; + if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 || + inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) { + /* IDR periodicity, n: + * n = 0 - only the first I-frame is IDR frame + * n = 1 - all I-frames will be IDR frames + * n > 1 - every n-th I-frame will be IDR frame + */ + ptype = HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD; + idrp.idr_period = 0; + ret = hfi_session_set_property(inst, ptype, &idrp); + if (ret) + return ret; + } if (ctr->num_b_frames) { u32 max_num_b_frames = NUM_B_FRAMES_MAX; @@ -655,6 +668,19 @@ static int venc_set_properties(struct venus_inst *inst) if (ret) return ret; + if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_H264 || + inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) { + ptype = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER; + if (ctr->header_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) + en.enable = 0; + else + en.enable = 1; + + ret = hfi_session_set_property(inst, ptype, &en); + if (ret) + return ret; + } + if (!ctr->bitrate_peak) bitrate *= 2; else @@ -669,17 +695,28 @@ static int venc_set_properties(struct venus_inst *inst) return ret; ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP; - quant.qp_i = ctr->h264_i_qp; - quant.qp_p = ctr->h264_p_qp; - quant.qp_b = ctr->h264_b_qp; + if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) { + quant.qp_i = ctr->hevc_i_qp; + quant.qp_p = ctr->hevc_p_qp; + quant.qp_b = ctr->hevc_b_qp; + } else { + quant.qp_i = ctr->h264_i_qp; + quant.qp_p = ctr->h264_p_qp; + quant.qp_b = ctr->h264_b_qp; + } quant.layer_id = 0; ret = hfi_session_set_property(inst, ptype, &quant); if (ret) return ret; ptype = HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE; - quant_range.min_qp = ctr->h264_min_qp; - quant_range.max_qp = ctr->h264_max_qp; + if (inst->fmt_cap->pixfmt == V4L2_PIX_FMT_HEVC) { + quant_range.min_qp = ctr->hevc_min_qp; + quant_range.max_qp = ctr->hevc_max_qp; + } else { + quant_range.min_qp = ctr->h264_min_qp; + quant_range.max_qp = ctr->h264_max_qp; + } quant_range.layer_id = 0; ret = hfi_session_set_property(inst, ptype, &quant_range); if (ret) @@ -724,10 +761,17 @@ static int venc_init_session(struct venus_inst *inst) { int ret; - ret = hfi_session_init(inst, inst->fmt_cap->pixfmt); - if (ret) + ret = venus_helper_session_init(inst); + if (ret == -EALREADY) + return 0; + else if (ret) return ret; + ret = venus_helper_set_stride(inst, inst->out_width, + inst->out_height); + if (ret) + goto deinit; + ret = venus_helper_set_input_resolution(inst, inst->width, inst->height); if (ret) @@ -743,10 +787,6 @@ static int venc_init_session(struct venus_inst *inst) if (ret) goto deinit; - ret = venus_helper_init_codec_freq_data(inst); - if (ret) - goto deinit; - ret = venc_set_properties(inst); if (ret) goto deinit; @@ -762,17 +802,13 @@ static int venc_out_num_buffers(struct venus_inst *inst, unsigned int *num) struct hfi_buffer_requirements bufreq; int ret; - ret = venc_init_session(inst); + ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq); if (ret) return ret; - ret = venus_helper_get_bufreq(inst, HFI_BUFFER_INPUT, &bufreq); - *num = bufreq.count_actual; - hfi_session_deinit(inst); - - return ret; + return 0; } static int venc_queue_setup(struct vb2_queue *q, @@ -781,7 +817,7 @@ static int venc_queue_setup(struct vb2_queue *q, { struct venus_inst *inst = vb2_get_drv_priv(q); unsigned int num, min = 4; - int ret = 0; + int ret; if (*num_planes) { if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && @@ -803,6 +839,13 @@ static int venc_queue_setup(struct vb2_queue *q, return 0; } + mutex_lock(&inst->lock); + ret = venc_init_session(inst); + mutex_unlock(&inst->lock); + + if (ret) + return ret; + switch (q->type) { case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: *num_planes = inst->fmt_out->num_planes; @@ -816,8 +859,8 @@ static int venc_queue_setup(struct vb2_queue *q, inst->num_input_bufs = *num_buffers; sizes[0] = venus_helper_get_framesz(inst->fmt_out->pixfmt, - inst->width, - inst->height); + inst->out_width, + inst->out_height); inst->input_buf_size = sizes[0]; break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: @@ -838,6 +881,49 @@ static int venc_queue_setup(struct vb2_queue *q, return ret; } +static int venc_buf_init(struct vb2_buffer *vb) +{ + struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + + inst->buf_count++; + + return venus_helper_vb2_buf_init(vb); +} + +static void venc_release_session(struct venus_inst *inst) +{ + int ret; + + mutex_lock(&inst->lock); + + ret = hfi_session_deinit(inst); + if (ret || inst->session_error) + hfi_session_abort(inst); + + mutex_unlock(&inst->lock); + + venus_pm_load_scale(inst); + INIT_LIST_HEAD(&inst->registeredbufs); + venus_pm_release_core(inst); +} + +static void venc_buf_cleanup(struct vb2_buffer *vb) +{ + struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct venus_buffer *buf = to_venus_buffer(vbuf); + + mutex_lock(&inst->lock); + if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + if (!list_empty(&inst->registeredbufs)) + list_del_init(&buf->reg_list); + mutex_unlock(&inst->lock); + + inst->buf_count--; + if (!inst->buf_count) + venc_release_session(inst); +} + static int venc_verify_conf(struct venus_inst *inst) { enum hfi_version ver = inst->core->res->hfi_version; @@ -888,38 +974,32 @@ static int venc_start_streaming(struct vb2_queue *q, unsigned int count) inst->sequence_cap = 0; inst->sequence_out = 0; - ret = venc_init_session(inst); - if (ret) - goto bufs_done; - ret = venus_pm_acquire_core(inst); if (ret) - goto deinit_sess; + goto error; ret = venc_set_properties(inst); if (ret) - goto deinit_sess; + goto error; ret = venc_verify_conf(inst); if (ret) - goto deinit_sess; + goto error; ret = venus_helper_set_num_bufs(inst, inst->num_input_bufs, inst->num_output_bufs, 0); if (ret) - goto deinit_sess; + goto error; ret = venus_helper_vb2_start_streaming(inst); if (ret) - goto deinit_sess; + goto error; mutex_unlock(&inst->lock); return 0; -deinit_sess: - hfi_session_deinit(inst); -bufs_done: +error: venus_helper_buffers_done(inst, q->type, VB2_BUF_STATE_QUEUED); if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) inst->streamon_out = 0; @@ -929,13 +1009,23 @@ bufs_done: return ret; } +static void venc_vb2_buf_queue(struct vb2_buffer *vb) +{ + struct venus_inst *inst = vb2_get_drv_priv(vb->vb2_queue); + + mutex_lock(&inst->lock); + venus_helper_vb2_buf_queue(vb); + mutex_unlock(&inst->lock); +} + static const struct vb2_ops venc_vb2_ops = { .queue_setup = venc_queue_setup, - .buf_init = venus_helper_vb2_buf_init, + .buf_init = venc_buf_init, + .buf_cleanup = venc_buf_cleanup, .buf_prepare = venus_helper_vb2_buf_prepare, .start_streaming = venc_start_streaming, .stop_streaming = venus_helper_vb2_stop_streaming, - .buf_queue = venus_helper_vb2_buf_queue, + .buf_queue = venc_vb2_buf_queue, }; static void venc_buf_done(struct venus_inst *inst, unsigned int buf_type, @@ -1001,7 +1091,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; src_vq->ops = &venc_vb2_ops; - src_vq->mem_ops = &vb2_dma_sg_memops; + src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->drv_priv = inst; src_vq->buf_struct_size = sizeof(struct venus_buffer); src_vq->allow_zero_bytesused = 1; @@ -1017,7 +1107,7 @@ static int m2m_queue_init(void *priv, struct vb2_queue *src_vq, dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; dst_vq->ops = &venc_vb2_ops; - dst_vq->mem_ops = &vb2_dma_sg_memops; + dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->drv_priv = inst; dst_vq->buf_struct_size = sizeof(struct venus_buffer); dst_vq->allow_zero_bytesused = 1; diff --git a/drivers/media/platform/qcom/venus/venc_ctrls.c b/drivers/media/platform/qcom/venus/venc_ctrls.c index cf860e6446c0..a52b80055173 100644 --- a/drivers/media/platform/qcom/venus/venc_ctrls.c +++ b/drivers/media/platform/qcom/venus/venc_ctrls.c @@ -135,9 +135,60 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: ctr->h264_min_qp = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: + ctr->h264_i_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: + ctr->h264_p_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: + ctr->h264_b_min_qp = ctrl->val; + break; case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: ctr->h264_max_qp = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: + ctr->h264_i_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: + ctr->h264_p_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: + ctr->h264_b_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: + ctr->hevc_i_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: + ctr->hevc_p_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: + ctr->hevc_b_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: + ctr->hevc_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: + ctr->hevc_i_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: + ctr->hevc_p_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: + ctr->hevc_b_min_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: + ctr->hevc_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: + ctr->hevc_i_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: + ctr->hevc_p_max_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: + ctr->hevc_b_max_qp = ctrl->val; + break; case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: ctr->multi_slice_mode = ctrl->val; break; @@ -158,6 +209,20 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_MPEG_VIDEO_HEADER_MODE: ctr->header_mode = ctrl->val; + mutex_lock(&inst->lock); + if (inst->streamon_out && inst->streamon_cap) { + if (ctrl->val == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) + en.enable = 0; + else + en.enable = 1; + ptype = HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER; + ret = hfi_session_set_property(inst, ptype, &en); + if (ret) { + mutex_unlock(&inst->lock); + return ret; + } + } + mutex_unlock(&inst->lock); break; case V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB: break; @@ -208,6 +273,9 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: ctr->frame_skip_mode = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID: + ctr->base_priority_id = ctrl->val; + break; default: return -EINVAL; } @@ -223,7 +291,7 @@ int venc_ctrl_init(struct venus_inst *inst) { int ret; - ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 33); + ret = v4l2_ctrl_handler_init(&inst->ctrl_handler, 51); if (ret) return ret; @@ -289,7 +357,8 @@ int venc_ctrl_init(struct venus_inst *inst) v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops, V4L2_CID_MPEG_VIDEO_HEADER_MODE, V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, - 1 << V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + ~((1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + (1 << V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME)), V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE); v4l2_ctrl_new_std_menu(&inst->ctrl_handler, &venc_ctrl_ops, @@ -311,19 +380,70 @@ int venc_ctrl_init(struct venus_inst *inst) BITRATE_STEP, BITRATE_DEFAULT_PEAK); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 26); + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 26); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 28); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, 1, 51, 1, 30); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 28); + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 1, 51, 1, 1); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP, 1, 51, 1, 30); + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP, 1, 51, 1, 1); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 1, 51, 1, 1); + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP, 1, 51, 1, 1); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_MAX_QP, 1, 51, 1, 51); + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP, 1, 51, 1, 1); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, 1, 51, 1, 51); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP, 1, 51, 1, 51); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP, 1, 51, 1, 51); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP, 1, 51, 1, 51); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, 1, 63, 1, 26); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP, 1, 63, 1, 28); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP, 1, 63, 1, 30); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, 1, 63, 1, 1); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP, 1, 63, 1, 1); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP, 1, 63, 1, 1); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP, 1, 63, 1, 1); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, 1, 63, 1, 63); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP, 1, 63, 1, 63); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP, 1, 63, 1, 63); + + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP, 1, 63, 1, 63); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, SLICE_BYTE_SIZE_MIN, @@ -374,6 +494,10 @@ int venc_ctrl_init(struct venus_inst *inst) (1 << V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT)), V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED); + v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID, 0, + 6, 1, 0); + ret = inst->ctrl_handler.error; if (ret) goto err; diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c index e48d666f2c63..cb3025992817 100644 --- a/drivers/media/platform/rcar-vin/rcar-core.c +++ b/drivers/media/platform/rcar-vin/rcar-core.c @@ -642,7 +642,7 @@ static int rvin_parallel_parse_of(struct rvin_dev *vin) } asd = v4l2_async_notifier_add_fwnode_subdev(&vin->notifier, fwnode, - sizeof(*asd)); + struct v4l2_async_subdev); if (IS_ERR(asd)) { ret = PTR_ERR(asd); goto out; @@ -842,7 +842,8 @@ static int rvin_mc_parse_of(struct rvin_dev *vin, unsigned int id) } asd = v4l2_async_notifier_add_fwnode_subdev(&vin->group->notifier, - fwnode, sizeof(*asd)); + fwnode, + struct v4l2_async_subdev); if (IS_ERR(asd)) { ret = PTR_ERR(asd); goto out; diff --git a/drivers/media/platform/rcar-vin/rcar-csi2.c b/drivers/media/platform/rcar-vin/rcar-csi2.c index 945d2eb87233..e06cd512aba2 100644 --- a/drivers/media/platform/rcar-vin/rcar-csi2.c +++ b/drivers/media/platform/rcar-vin/rcar-csi2.c @@ -910,7 +910,7 @@ static int rcsi2_parse_dt(struct rcar_csi2 *priv) priv->notifier.ops = &rcar_csi2_notify_ops; asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, fwnode, - sizeof(*asd)); + struct v4l2_async_subdev); fwnode_handle_put(fwnode); if (IS_ERR(asd)) return PTR_ERR(asd); diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c index 48280ddb15b9..f30dafbdf61c 100644 --- a/drivers/media/platform/rcar-vin/rcar-dma.c +++ b/drivers/media/platform/rcar-vin/rcar-dma.c @@ -1301,6 +1301,11 @@ void rvin_stop_streaming(struct rvin_dev *vin) spin_lock_irqsave(&vin->qlock, flags); + if (vin->state == STOPPED) { + spin_unlock_irqrestore(&vin->qlock, flags); + return; + } + vin->state = STOPPING; /* Wait until only scratch buffer is used, max 3 interrupts. */ diff --git a/drivers/media/platform/rcar-vin/rcar-v4l2.c b/drivers/media/platform/rcar-vin/rcar-v4l2.c index e6ea2b7991b8..457a65bf6b66 100644 --- a/drivers/media/platform/rcar-vin/rcar-v4l2.c +++ b/drivers/media/platform/rcar-vin/rcar-v4l2.c @@ -966,12 +966,9 @@ void rvin_v4l2_unregister(struct rvin_dev *vin) video_unregister_device(&vin->vdev); } -static void rvin_notify(struct v4l2_subdev *sd, - unsigned int notification, void *arg) +static void rvin_notify_video_device(struct rvin_dev *vin, + unsigned int notification, void *arg) { - struct rvin_dev *vin = - container_of(sd->v4l2_dev, struct rvin_dev, v4l2_dev); - switch (notification) { case V4L2_DEVICE_NOTIFY_EVENT: v4l2_event_queue(&vin->vdev, arg); @@ -981,6 +978,41 @@ static void rvin_notify(struct v4l2_subdev *sd, } } +static void rvin_notify(struct v4l2_subdev *sd, + unsigned int notification, void *arg) +{ + struct v4l2_subdev *remote; + struct rvin_group *group; + struct media_pad *pad; + struct rvin_dev *vin = + container_of(sd->v4l2_dev, struct rvin_dev, v4l2_dev); + unsigned int i; + + /* If no media controller, no need to route the event. */ + if (!vin->info->use_mc) { + rvin_notify_video_device(vin, notification, arg); + return; + } + + group = vin->group; + + for (i = 0; i < RCAR_VIN_NUM; i++) { + vin = group->vin[i]; + if (!vin) + continue; + + pad = media_entity_remote_pad(&vin->pad); + if (!pad) + continue; + + remote = media_entity_to_v4l2_subdev(pad->entity); + if (remote != sd) + continue; + + rvin_notify_video_device(vin, notification, arg); + } +} + int rvin_v4l2_register(struct rvin_dev *vin) { struct video_device *vdev = &vin->vdev; diff --git a/drivers/media/platform/rcar_drif.c b/drivers/media/platform/rcar_drif.c index f318cd4b8086..83bd9a412a56 100644 --- a/drivers/media/platform/rcar_drif.c +++ b/drivers/media/platform/rcar_drif.c @@ -1231,7 +1231,7 @@ static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr) } asd = v4l2_async_notifier_add_fwnode_subdev(notifier, fwnode, - sizeof(*asd)); + struct v4l2_async_subdev); fwnode_handle_put(fwnode); if (IS_ERR(asd)) return PTR_ERR(asd); diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index c9448de885b6..01c1fbb97bf6 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -1439,8 +1439,6 @@ static void fdp1_compute_stride(struct v4l2_pix_format_mplane *pix, pix->plane_fmt[i].sizeimage = pix->plane_fmt[i].bytesperline * pix->height / vsub; - memset(pix->plane_fmt[i].reserved, 0, - sizeof(pix->plane_fmt[i].reserved)); } if (fmt->num_planes == 3) { @@ -1448,8 +1446,6 @@ static void fdp1_compute_stride(struct v4l2_pix_format_mplane *pix, pix->plane_fmt[2].bytesperline = pix->plane_fmt[1].bytesperline; pix->plane_fmt[2].sizeimage = pix->plane_fmt[1].sizeimage; - memset(pix->plane_fmt[2].reserved, 0, - sizeof(pix->plane_fmt[2].reserved)); } } diff --git a/drivers/media/platform/rcar_jpu.c b/drivers/media/platform/rcar_jpu.c index 9b99ff368698..a7c198c17deb 100644 --- a/drivers/media/platform/rcar_jpu.c +++ b/drivers/media/platform/rcar_jpu.c @@ -648,6 +648,7 @@ static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width, if (get_word_be(&jpeg_buffer, &word)) return 0; skip(&jpeg_buffer, (long)word - 2); + break; case 0: break; default: @@ -793,7 +794,6 @@ static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo, pix->colorspace = fmt->colorspace; pix->field = V4L2_FIELD_NONE; pix->num_planes = fmt->num_planes; - memset(pix->reserved, 0, sizeof(pix->reserved)); jpu_bound_align_image(&pix->width, JPU_WIDTH_MIN, JPU_WIDTH_MAX, fmt->h_align, &pix->height, JPU_HEIGHT_MIN, @@ -808,8 +808,6 @@ static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo, pix->plane_fmt[0].sizeimage = JPU_JPEG_HDR_SIZE + (JPU_JPEG_MAX_BYTES_PER_PIXEL * w * h); pix->plane_fmt[0].bytesperline = 0; - memset(pix->plane_fmt[0].reserved, 0, - sizeof(pix->plane_fmt[0].reserved)); } else { unsigned int i, bpl = 0; @@ -822,8 +820,6 @@ static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo, for (i = 0; i < pix->num_planes; ++i) { pix->plane_fmt[i].bytesperline = bpl; pix->plane_fmt[i].sizeimage = bpl * h * fmt->bpp[i] / 8; - memset(pix->plane_fmt[i].reserved, 0, - sizeof(pix->plane_fmt[i].reserved)); } } diff --git a/drivers/media/platform/renesas-ceu.c b/drivers/media/platform/renesas-ceu.c index 4a633ad0e8fa..1678175c49bd 100644 --- a/drivers/media/platform/renesas-ceu.c +++ b/drivers/media/platform/renesas-ceu.c @@ -152,8 +152,8 @@ static inline struct ceu_buffer *vb2_to_ceu(struct vb2_v4l2_buffer *vbuf) * ceu_subdev - Wraps v4l2 sub-device and provides async subdevice. */ struct ceu_subdev { - struct v4l2_subdev *v4l2_sd; struct v4l2_async_subdev asd; + struct v4l2_subdev *v4l2_sd; /* per-subdevice mbus configuration options */ unsigned int mbus_flags; @@ -174,7 +174,7 @@ struct ceu_device { struct v4l2_device v4l2_dev; /* subdevices descriptors */ - struct ceu_subdev *subdevs; + struct ceu_subdev **subdevs; /* the subdevice currently in use */ struct ceu_subdev *sd; unsigned int sd_index; @@ -1195,7 +1195,7 @@ static int ceu_enum_input(struct file *file, void *priv, if (inp->index >= ceudev->num_sd) return -EINVAL; - ceusd = &ceudev->subdevs[inp->index]; + ceusd = ceudev->subdevs[inp->index]; inp->type = V4L2_INPUT_TYPE_CAMERA; inp->std = 0; @@ -1230,7 +1230,7 @@ static int ceu_s_input(struct file *file, void *priv, unsigned int i) return 0; ceu_sd_old = ceudev->sd; - ceudev->sd = &ceudev->subdevs[i]; + ceudev->sd = ceudev->subdevs[i]; /* * Make sure we can generate output image formats and apply @@ -1423,7 +1423,7 @@ static int ceu_notify_complete(struct v4l2_async_notifier *notifier) * ceu formats. */ if (!ceudev->sd) { - ceudev->sd = &ceudev->subdevs[0]; + ceudev->sd = ceudev->subdevs[0]; ceudev->sd_index = 0; } @@ -1467,8 +1467,8 @@ static const struct v4l2_async_notifier_operations ceu_notify_ops = { /* * ceu_init_async_subdevs() - Initialize CEU subdevices and async_subdevs in - * ceu device. Both DT and platform data parsing use - * this routine. + * ceu device. Both DT and platform data parsing use + * this routine. * * Returns 0 for success, -ENOMEM for failure. */ @@ -1510,21 +1510,16 @@ static int ceu_parse_platform_data(struct ceu_device *ceudev, /* Setup the ceu subdevice and the async subdevice. */ async_sd = &pdata->subdevs[i]; - ceu_sd = &ceudev->subdevs[i]; - - INIT_LIST_HEAD(&ceu_sd->asd.list); - - ceu_sd->mbus_flags = async_sd->flags; - ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_I2C; - ceu_sd->asd.match.i2c.adapter_id = async_sd->i2c_adapter_id; - ceu_sd->asd.match.i2c.address = async_sd->i2c_address; - - ret = v4l2_async_notifier_add_subdev(&ceudev->notifier, - &ceu_sd->asd); - if (ret) { + ceu_sd = v4l2_async_notifier_add_i2c_subdev(&ceudev->notifier, + async_sd->i2c_adapter_id, + async_sd->i2c_address, + struct ceu_subdev); + if (IS_ERR(ceu_sd)) { v4l2_async_notifier_cleanup(&ceudev->notifier); - return ret; + return PTR_ERR(ceu_sd); } + ceu_sd->mbus_flags = async_sd->flags; + ceudev->subdevs[i] = ceu_sd; } return pdata->num_subdevs; @@ -1536,7 +1531,7 @@ static int ceu_parse_platform_data(struct ceu_device *ceudev, static int ceu_parse_dt(struct ceu_device *ceudev) { struct device_node *of = ceudev->dev->of_node; - struct device_node *ep, *remote; + struct device_node *ep; struct ceu_subdev *ceu_sd; unsigned int i; int num_ep; @@ -1578,20 +1573,15 @@ static int ceu_parse_dt(struct ceu_device *ceudev) } /* Setup the ceu subdevice and the async subdevice. */ - ceu_sd = &ceudev->subdevs[i]; - INIT_LIST_HEAD(&ceu_sd->asd.list); - - remote = of_graph_get_remote_port_parent(ep); - ceu_sd->mbus_flags = fw_ep.bus.parallel.flags; - ceu_sd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - ceu_sd->asd.match.fwnode = of_fwnode_handle(remote); - - ret = v4l2_async_notifier_add_subdev(&ceudev->notifier, - &ceu_sd->asd); - if (ret) { - of_node_put(remote); + ceu_sd = v4l2_async_notifier_add_fwnode_remote_subdev( + &ceudev->notifier, of_fwnode_handle(ep), + struct ceu_subdev); + if (IS_ERR(ceu_sd)) { + ret = PTR_ERR(ceu_sd); goto error_cleanup; } + ceu_sd->mbus_flags = fw_ep.bus.parallel.flags; + ceudev->subdevs[i] = ceu_sd; of_node_put(ep); } diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c index f7e9fd305548..7474150b94ed 100644 --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c @@ -252,7 +252,7 @@ static int rkisp1_subdev_notifier(struct rkisp1_device *rkisp1) struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY }; - struct rkisp1_sensor_async *rk_asd = NULL; + struct rkisp1_sensor_async *rk_asd; struct fwnode_handle *ep; ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(rkisp1->dev), @@ -265,9 +265,10 @@ static int rkisp1_subdev_notifier(struct rkisp1_device *rkisp1) if (ret) goto err_parse; - rk_asd = kzalloc(sizeof(*rk_asd), GFP_KERNEL); - if (!rk_asd) { - ret = -ENOMEM; + rk_asd = v4l2_async_notifier_add_fwnode_remote_subdev(ntf, ep, + struct rkisp1_sensor_async); + if (IS_ERR(rk_asd)) { + ret = PTR_ERR(rk_asd); goto err_parse; } @@ -275,11 +276,6 @@ static int rkisp1_subdev_notifier(struct rkisp1_device *rkisp1) rk_asd->mbus_flags = vep.bus.mipi_csi2.flags; rk_asd->lanes = vep.bus.mipi_csi2.num_data_lanes; - ret = v4l2_async_notifier_add_fwnode_remote_subdev(ntf, ep, - &rk_asd->asd); - if (ret) - goto err_parse; - dev_dbg(rkisp1->dev, "registered ep id %d with %d lanes\n", vep.base.id, rk_asd->lanes); @@ -290,7 +286,6 @@ static int rkisp1_subdev_notifier(struct rkisp1_device *rkisp1) continue; err_parse: fwnode_handle_put(ep); - kfree(rk_asd); v4l2_async_notifier_cleanup(ntf); return ret; } diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c index 889982d8ca41..2e5b57e3aedc 100644 --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c @@ -600,6 +600,39 @@ static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd, return -EINVAL; } +static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + const struct rkisp1_isp_mbus_info *mbus_info; + + if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS || + fse->pad == RKISP1_ISP_PAD_SOURCE_STATS) + return -ENOTTY; + + if (fse->index > 0) + return -EINVAL; + + mbus_info = rkisp1_isp_mbus_info_get(fse->code); + if (!mbus_info) + return -EINVAL; + + if (!(mbus_info->direction & RKISP1_ISP_SD_SINK) && + fse->pad == RKISP1_ISP_PAD_SINK_VIDEO) + return -EINVAL; + + if (!(mbus_info->direction & RKISP1_ISP_SD_SRC) && + fse->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) + return -EINVAL; + + fse->min_width = RKISP1_ISP_MIN_WIDTH; + fse->max_width = RKISP1_ISP_MAX_WIDTH; + fse->min_height = RKISP1_ISP_MIN_HEIGHT; + fse->max_height = RKISP1_ISP_MAX_HEIGHT; + + return 0; +} + static int rkisp1_isp_init_config(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg) { @@ -880,6 +913,7 @@ static int rkisp1_subdev_link_validate(struct media_link *link) static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = { .enum_mbus_code = rkisp1_isp_enum_mbus_code, + .enum_frame_size = rkisp1_isp_enum_frame_size, .get_selection = rkisp1_isp_get_selection, .set_selection = rkisp1_isp_set_selection, .init_cfg = rkisp1_isp_init_config, diff --git a/drivers/media/platform/sh_vou.c b/drivers/media/platform/sh_vou.c index b22dc1d72527..4ac48441f22c 100644 --- a/drivers/media/platform/sh_vou.c +++ b/drivers/media/platform/sh_vou.c @@ -1355,7 +1355,7 @@ static int sh_vou_remove(struct platform_device *pdev) return 0; } -static struct platform_driver __refdata sh_vou = { +static struct platform_driver sh_vou = { .remove = sh_vou_remove, .driver = { .name = "sh-vou", diff --git a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c index 5ceb366648b3..a7a6ea666740 100644 --- a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c +++ b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c @@ -826,6 +826,7 @@ static int c8sectpfe_probe(struct platform_device *pdev) dev_err(dev, "reset gpio for tsin%d not valid (gpio=%d)\n", tsin->tsin_id, tsin->rst_gpio); + ret = -EINVAL; goto err_node_put; } diff --git a/drivers/media/platform/sti/hva/hva-hw.c b/drivers/media/platform/sti/hva/hva-hw.c index 43f279e2a6a3..f59811e27f51 100644 --- a/drivers/media/platform/sti/hva/hva-hw.c +++ b/drivers/media/platform/sti/hva/hva-hw.c @@ -447,6 +447,7 @@ int hva_hw_runtime_resume(struct device *dev) if (clk_set_rate(hva->clk, CLK_RATE)) { dev_err(dev, "%s failed to set clock frequency\n", HVA_PREFIX); + clk_disable_unprepare(hva->clk); return -EINVAL; } diff --git a/drivers/media/platform/stm32/stm32-dcmi.c b/drivers/media/platform/stm32/stm32-dcmi.c index b745f1342c2e..bbcc2254fa2e 100644 --- a/drivers/media/platform/stm32/stm32-dcmi.c +++ b/drivers/media/platform/stm32/stm32-dcmi.c @@ -99,13 +99,6 @@ enum state { #define OVERRUN_ERROR_THRESHOLD 3 -struct dcmi_graph_entity { - struct v4l2_async_subdev asd; - - struct device_node *remote_node; - struct v4l2_subdev *source; -}; - struct dcmi_format { u32 fourcc; u32 mbus_code; @@ -139,7 +132,7 @@ struct stm32_dcmi { struct v4l2_device v4l2_dev; struct video_device *vdev; struct v4l2_async_notifier notifier; - struct dcmi_graph_entity entity; + struct v4l2_subdev *source; struct v4l2_format fmt; struct v4l2_rect crop; bool do_crop; @@ -610,7 +603,7 @@ static int dcmi_pipeline_s_fmt(struct stm32_dcmi *dcmi, struct v4l2_subdev_pad_config *pad_cfg, struct v4l2_subdev_format *format) { - struct media_entity *entity = &dcmi->entity.source->entity; + struct media_entity *entity = &dcmi->source->entity; struct v4l2_subdev *subdev; struct media_pad *sink_pad = NULL; struct media_pad *src_pad = NULL; @@ -1018,7 +1011,7 @@ static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f, } v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); - ret = v4l2_subdev_call(dcmi->entity.source, pad, set_fmt, + ret = v4l2_subdev_call(dcmi->source, pad, set_fmt, &pad_cfg, &format); if (ret < 0) return ret; @@ -1152,7 +1145,7 @@ static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi, }; int ret; - ret = v4l2_subdev_call(dcmi->entity.source, pad, get_fmt, NULL, &fmt); + ret = v4l2_subdev_call(dcmi->source, pad, get_fmt, NULL, &fmt); if (ret) return ret; @@ -1181,7 +1174,7 @@ static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi, } v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); - ret = v4l2_subdev_call(dcmi->entity.source, pad, set_fmt, + ret = v4l2_subdev_call(dcmi->source, pad, set_fmt, &pad_cfg, &format); if (ret < 0) return ret; @@ -1204,7 +1197,7 @@ static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi, /* * Get sensor bounds first */ - ret = v4l2_subdev_call(dcmi->entity.source, pad, get_selection, + ret = v4l2_subdev_call(dcmi->source, pad, get_selection, NULL, &bounds); if (!ret) *r = bounds.r; @@ -1385,7 +1378,7 @@ static int dcmi_enum_framesizes(struct file *file, void *fh, fse.code = sd_fmt->mbus_code; - ret = v4l2_subdev_call(dcmi->entity.source, pad, enum_frame_size, + ret = v4l2_subdev_call(dcmi->source, pad, enum_frame_size, NULL, &fse); if (ret) return ret; @@ -1402,7 +1395,7 @@ static int dcmi_g_parm(struct file *file, void *priv, { struct stm32_dcmi *dcmi = video_drvdata(file); - return v4l2_g_parm_cap(video_devdata(file), dcmi->entity.source, p); + return v4l2_g_parm_cap(video_devdata(file), dcmi->source, p); } static int dcmi_s_parm(struct file *file, void *priv, @@ -1410,7 +1403,7 @@ static int dcmi_s_parm(struct file *file, void *priv, { struct stm32_dcmi *dcmi = video_drvdata(file); - return v4l2_s_parm_cap(video_devdata(file), dcmi->entity.source, p); + return v4l2_s_parm_cap(video_devdata(file), dcmi->source, p); } static int dcmi_enum_frameintervals(struct file *file, void *fh, @@ -1432,7 +1425,7 @@ static int dcmi_enum_frameintervals(struct file *file, void *fh, fie.code = sd_fmt->mbus_code; - ret = v4l2_subdev_call(dcmi->entity.source, pad, + ret = v4l2_subdev_call(dcmi->source, pad, enum_frame_interval, NULL, &fie); if (ret) return ret; @@ -1452,7 +1445,7 @@ MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match); static int dcmi_open(struct file *file) { struct stm32_dcmi *dcmi = video_drvdata(file); - struct v4l2_subdev *sd = dcmi->entity.source; + struct v4l2_subdev *sd = dcmi->source; int ret; if (mutex_lock_interruptible(&dcmi->lock)) @@ -1483,7 +1476,7 @@ unlock: static int dcmi_release(struct file *file) { struct stm32_dcmi *dcmi = video_drvdata(file); - struct v4l2_subdev *sd = dcmi->entity.source; + struct v4l2_subdev *sd = dcmi->source; bool fh_singular; int ret; @@ -1616,7 +1609,7 @@ static int dcmi_formats_init(struct stm32_dcmi *dcmi) { const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)]; unsigned int num_fmts = 0, i, j; - struct v4l2_subdev *subdev = dcmi->entity.source; + struct v4l2_subdev *subdev = dcmi->source; struct v4l2_subdev_mbus_code_enum mbus_code = { .which = V4L2_SUBDEV_FORMAT_ACTIVE, }; @@ -1675,7 +1668,7 @@ static int dcmi_formats_init(struct stm32_dcmi *dcmi) static int dcmi_framesizes_init(struct stm32_dcmi *dcmi) { unsigned int num_fsize = 0; - struct v4l2_subdev *subdev = dcmi->entity.source; + struct v4l2_subdev *subdev = dcmi->source; struct v4l2_subdev_frame_size_enum fse = { .which = V4L2_SUBDEV_FORMAT_ACTIVE, .code = dcmi->sd_format->mbus_code, @@ -1727,14 +1720,13 @@ static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier) * we search for the source subdevice * in order to expose it through V4L2 interface */ - dcmi->entity.source = - media_entity_to_v4l2_subdev(dcmi_find_source(dcmi)); - if (!dcmi->entity.source) { + dcmi->source = media_entity_to_v4l2_subdev(dcmi_find_source(dcmi)); + if (!dcmi->source) { dev_err(dcmi->dev, "Source subdevice not found\n"); return -ENODEV; } - dcmi->vdev->ctrl_handler = dcmi->entity.source->ctrl_handler; + dcmi->vdev->ctrl_handler = dcmi->source->ctrl_handler; ret = dcmi_formats_init(dcmi); if (ret) { @@ -1813,46 +1805,29 @@ static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = { .complete = dcmi_graph_notify_complete, }; -static int dcmi_graph_parse(struct stm32_dcmi *dcmi, struct device_node *node) -{ - struct device_node *ep = NULL; - struct device_node *remote; - - ep = of_graph_get_next_endpoint(node, ep); - if (!ep) - return -EINVAL; - - remote = of_graph_get_remote_port_parent(ep); - of_node_put(ep); - if (!remote) - return -EINVAL; - - /* Remote node to connect */ - dcmi->entity.remote_node = remote; - dcmi->entity.asd.match_type = V4L2_ASYNC_MATCH_FWNODE; - dcmi->entity.asd.match.fwnode = of_fwnode_handle(remote); - return 0; -} - static int dcmi_graph_init(struct stm32_dcmi *dcmi) { + struct v4l2_async_subdev *asd; + struct device_node *ep; int ret; - /* Parse the graph to extract a list of subdevice DT nodes. */ - ret = dcmi_graph_parse(dcmi, dcmi->dev->of_node); - if (ret < 0) { - dev_err(dcmi->dev, "Failed to parse graph\n"); - return ret; + ep = of_graph_get_next_endpoint(dcmi->dev->of_node, NULL); + if (!ep) { + dev_err(dcmi->dev, "Failed to get next endpoint\n"); + return -EINVAL; } v4l2_async_notifier_init(&dcmi->notifier); - ret = v4l2_async_notifier_add_subdev(&dcmi->notifier, - &dcmi->entity.asd); - if (ret) { + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &dcmi->notifier, of_fwnode_handle(ep), + struct v4l2_async_subdev); + + of_node_put(ep); + + if (IS_ERR(asd)) { dev_err(dcmi->dev, "Failed to add subdev notifier\n"); - of_node_put(dcmi->entity.remote_node); - return ret; + return PTR_ERR(asd); } dcmi->notifier.ops = &dcmi_graph_notify_ops; diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c index ec46cff80fdb..8d40a7acba9c 100644 --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c @@ -118,6 +118,7 @@ static int sun4i_csi_notifier_init(struct sun4i_csi *csi) struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_PARALLEL, }; + struct v4l2_async_subdev *asd; struct fwnode_handle *ep; int ret; @@ -134,10 +135,12 @@ static int sun4i_csi_notifier_init(struct sun4i_csi *csi) csi->bus = vep.bus.parallel; - ret = v4l2_async_notifier_add_fwnode_remote_subdev(&csi->notifier, - ep, &csi->asd); - if (ret) + asd = v4l2_async_notifier_add_fwnode_remote_subdev(&csi->notifier, ep, + struct v4l2_async_subdev); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); goto out; + } csi->notifier.ops = &sun4i_csi_notify_ops; diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h index 0f67ff652c2e..a5f61ee0ec4d 100644 --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h @@ -139,7 +139,6 @@ struct sun4i_csi { struct v4l2_mbus_framefmt subdev_fmt; /* V4L2 Async variables */ - struct v4l2_async_subdev asd; struct v4l2_async_notifier notifier; struct v4l2_subdev *src_subdev; int src_pad; diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c index 1a2f65d83a6c..4785faddf630 100644 --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_v4l2.c @@ -113,8 +113,6 @@ static void _sun4i_csi_try_fmt(struct sun4i_csi *csi, pix->num_planes = _fmt->num_planes; pix->pixelformat = _fmt->fourcc; - memset(pix->reserved, 0, sizeof(pix->reserved)); - /* Align the width and height on the subsampling */ width = ALIGN(pix->width, _fmt->hsub); height = ALIGN(pix->height, _fmt->vsub); @@ -131,8 +129,6 @@ static void _sun4i_csi_try_fmt(struct sun4i_csi *csi, bpl = pix->width / hsub * _fmt->bpp[i] / 8; pix->plane_fmt[i].bytesperline = bpl; pix->plane_fmt[i].sizeimage = bpl * pix->height / vsub; - memset(pix->plane_fmt[i].reserved, 0, - sizeof(pix->plane_fmt[i].reserved)); } } diff --git a/drivers/media/platform/ti-vpe/cal-camerarx.c b/drivers/media/platform/ti-vpe/cal-camerarx.c index 806cbf175d39..dd48017859cd 100644 --- a/drivers/media/platform/ti-vpe/cal-camerarx.c +++ b/drivers/media/platform/ti-vpe/cal-camerarx.c @@ -116,8 +116,7 @@ void cal_camerarx_disable(struct cal_camerarx *phy) #define TCLK_MISS 1 #define TCLK_SETTLE 14 -static void cal_camerarx_config(struct cal_camerarx *phy, s64 external_rate, - const struct cal_fmt *fmt) +static void cal_camerarx_config(struct cal_camerarx *phy, s64 external_rate) { unsigned int reg0, reg1; unsigned int ths_term, ths_settle; @@ -132,9 +131,9 @@ static void cal_camerarx_config(struct cal_camerarx *phy, s64 external_rate, * CSI-2 is DDR and we only count used lanes. * * csi2_ddrclk_khz = external_rate / 1000 - * / (2 * num_lanes) * fmt->bpp; + * / (2 * num_lanes) * phy->fmtinfo->bpp; */ - csi2_ddrclk_khz = div_s64(external_rate * fmt->bpp, + csi2_ddrclk_khz = div_s64(external_rate * phy->fmtinfo->bpp, 2 * num_lanes * 1000); phy_dbg(1, phy, "csi2_ddrclk_khz: %d\n", csi2_ddrclk_khz); @@ -234,7 +233,42 @@ static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy) phy_err(phy, "Timeout waiting for stop state\n"); } -int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt) +static void cal_camerarx_enable_irqs(struct cal_camerarx *phy) +{ + const u32 cio_err_mask = + CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK | + CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK | + CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK | + CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK; + + /* Enable CIO error IRQs. */ + cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), + CAL_HL_IRQ_CIO_MASK(phy->instance)); + cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), + cio_err_mask); +} + +static void cal_camerarx_disable_irqs(struct cal_camerarx *phy) +{ + /* Disable CIO error irqs */ + cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0), + CAL_HL_IRQ_CIO_MASK(phy->instance)); + cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0); +} + +static void cal_camerarx_ppi_enable(struct cal_camerarx *phy) +{ + cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), + 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK); +} + +static void cal_camerarx_ppi_disable(struct cal_camerarx *phy) +{ + cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), + 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK); +} + +static int cal_camerarx_start(struct cal_camerarx *phy) { s64 external_rate; u32 sscounter; @@ -251,6 +285,8 @@ int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt) return ret; } + cal_camerarx_enable_irqs(phy); + /* * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP / * DRA75xP / DRA76xP / DRA77xP TRM. The DRA71x / DRA72x and the AM65x / @@ -289,7 +325,7 @@ int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt) camerarx_read(phy, CAL_CSI2_PHY_REG0); /* Program the PHY timing parameters. */ - cal_camerarx_config(phy, external_rate, fmt); + cal_camerarx_config(phy, external_rate); /* * b. Assert the FORCERXMODE signal. @@ -340,6 +376,7 @@ int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt) ret = v4l2_subdev_call(phy->sensor, video, s_stream, 1); if (ret) { v4l2_subdev_call(phy->sensor, core, s_power, 0); + cal_camerarx_disable_irqs(phy); phy_err(phy, "stream on failed in subdev\n"); return ret; } @@ -359,14 +396,21 @@ int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt) * implemented. */ + /* Finally, enable the PHY Protocol Interface (PPI). */ + cal_camerarx_ppi_enable(phy); + return 0; } -void cal_camerarx_stop(struct cal_camerarx *phy) +static void cal_camerarx_stop(struct cal_camerarx *phy) { unsigned int i; int ret; + cal_camerarx_ppi_disable(phy); + + cal_camerarx_disable_irqs(phy); + cal_camerarx_power(phy, false); /* Assert Complex IO Reset */ @@ -428,74 +472,6 @@ void cal_camerarx_i913_errata(struct cal_camerarx *phy) camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10); } -/* - * Enable the expected IRQ sources - */ -void cal_camerarx_enable_irqs(struct cal_camerarx *phy) -{ - u32 val; - - const u32 cio_err_mask = - CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK | - CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK | - CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK | - CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK; - - /* Enable CIO error irqs */ - cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), - CAL_HL_IRQ_CIO_MASK(phy->instance)); - cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), - cio_err_mask); - - /* Always enable OCPO error */ - cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK); - - /* Enable IRQ_WDMA_END 0/1 */ - val = 0; - cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance)); - cal_write(phy->cal, CAL_HL_IRQENABLE_SET(1), val); - /* Enable IRQ_WDMA_START 0/1 */ - val = 0; - cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance)); - cal_write(phy->cal, CAL_HL_IRQENABLE_SET(2), val); - /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ - cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000); -} - -void cal_camerarx_disable_irqs(struct cal_camerarx *phy) -{ - u32 val; - - /* Disable CIO error irqs */ - cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0), - CAL_HL_IRQ_CIO_MASK(phy->instance)); - cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0); - - /* Disable IRQ_WDMA_END 0/1 */ - val = 0; - cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance)); - cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(1), val); - /* Disable IRQ_WDMA_START 0/1 */ - val = 0; - cal_set_field(&val, 1, CAL_HL_IRQ_MASK(phy->instance)); - cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(2), val); - /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ - cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(0), 0); -} - -void cal_camerarx_ppi_enable(struct cal_camerarx *phy) -{ - cal_write(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), BIT(3)); - cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), - 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK); -} - -void cal_camerarx_ppi_disable(struct cal_camerarx *phy) -{ - cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), - 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK); -} - static int cal_camerarx_regmap_init(struct cal_dev *cal, struct cal_camerarx *phy) { @@ -533,8 +509,8 @@ static int cal_camerarx_regmap_init(struct cal_dev *cal, static int cal_camerarx_parse_dt(struct cal_camerarx *phy) { struct v4l2_fwnode_endpoint *endpoint = &phy->endpoint; - struct device_node *ep_node; char data_lanes[V4L2_FWNODE_CSI2_MAX_DATA_LANES * 2]; + struct device_node *ep_node; unsigned int i; int ret; @@ -582,9 +558,11 @@ static int cal_camerarx_parse_dt(struct cal_camerarx *phy) endpoint->bus.mipi_csi2.flags); /* Retrieve the connected device and store it for later use. */ - phy->sensor_node = of_graph_get_remote_port_parent(ep_node); + phy->sensor_ep_node = of_graph_get_remote_endpoint(ep_node); + phy->sensor_node = of_graph_get_port_parent(phy->sensor_ep_node); if (!phy->sensor_node) { phy_dbg(3, phy, "Can't get remote parent\n"); + of_node_put(phy->sensor_ep_node); ret = -EINVAL; goto done; } @@ -596,11 +574,227 @@ done: return ret; } +/* ------------------------------------------------------------------ + * V4L2 Subdev Operations + * ------------------------------------------------------------------ + */ + +static inline struct cal_camerarx *to_cal_camerarx(struct v4l2_subdev *sd) +{ + return container_of(sd, struct cal_camerarx, subdev); +} + +static struct v4l2_mbus_framefmt * +cal_camerarx_get_pad_format(struct cal_camerarx *phy, + struct v4l2_subdev_pad_config *cfg, + unsigned int pad, u32 which) +{ + switch (which) { + case V4L2_SUBDEV_FORMAT_TRY: + return v4l2_subdev_get_try_format(&phy->subdev, cfg, pad); + case V4L2_SUBDEV_FORMAT_ACTIVE: + return &phy->formats[pad]; + default: + return NULL; + } +} + +static int cal_camerarx_sd_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct cal_camerarx *phy = to_cal_camerarx(sd); + + if (enable) + return cal_camerarx_start(phy); + + cal_camerarx_stop(phy); + return 0; +} + +static int cal_camerarx_sd_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct cal_camerarx *phy = to_cal_camerarx(sd); + + /* No transcoding, source and sink codes must match. */ + if (code->pad == CAL_CAMERARX_PAD_SOURCE) { + struct v4l2_mbus_framefmt *fmt; + + if (code->index > 0) + return -EINVAL; + + fmt = cal_camerarx_get_pad_format(phy, cfg, + CAL_CAMERARX_PAD_SINK, + code->which); + code->code = fmt->code; + return 0; + } + + if (code->index >= cal_num_formats) + return -EINVAL; + + code->code = cal_formats[code->index].code; + + return 0; +} + +static int cal_camerarx_sd_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct cal_camerarx *phy = to_cal_camerarx(sd); + const struct cal_format_info *fmtinfo; + + if (fse->index > 0) + return -EINVAL; + + /* No transcoding, source and sink formats must match. */ + if (fse->pad == CAL_CAMERARX_PAD_SOURCE) { + struct v4l2_mbus_framefmt *fmt; + + fmt = cal_camerarx_get_pad_format(phy, cfg, + CAL_CAMERARX_PAD_SINK, + fse->which); + if (fse->code != fmt->code) + return -EINVAL; + + fse->min_width = fmt->width; + fse->max_width = fmt->width; + fse->min_height = fmt->height; + fse->max_height = fmt->height; + + return 0; + } + + fmtinfo = cal_format_by_code(fse->code); + if (!fmtinfo) + return -EINVAL; + + fse->min_width = CAL_MIN_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); + fse->max_width = CAL_MAX_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); + fse->min_height = CAL_MIN_HEIGHT_LINES; + fse->max_height = CAL_MAX_HEIGHT_LINES; + + return 0; +} + +static int cal_camerarx_sd_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct cal_camerarx *phy = to_cal_camerarx(sd); + struct v4l2_mbus_framefmt *fmt; + + fmt = cal_camerarx_get_pad_format(phy, cfg, format->pad, format->which); + format->format = *fmt; + + return 0; +} + +static int cal_camerarx_sd_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct cal_camerarx *phy = to_cal_camerarx(sd); + const struct cal_format_info *fmtinfo; + struct v4l2_mbus_framefmt *fmt; + unsigned int bpp; + + /* No transcoding, source and sink formats must match. */ + if (format->pad == CAL_CAMERARX_PAD_SOURCE) + return cal_camerarx_sd_get_fmt(sd, cfg, format); + + /* + * Default to the first format is the requested media bus code isn't + * supported. + */ + fmtinfo = cal_format_by_code(format->format.code); + if (!fmtinfo) + fmtinfo = &cal_formats[0]; + + /* + * Clamp the size, update the code. The field and colorspace are + * accepted as-is. + */ + bpp = ALIGN(fmtinfo->bpp, 8); + + format->format.width = clamp_t(unsigned int, format->format.width, + CAL_MIN_WIDTH_BYTES * 8 / bpp, + CAL_MAX_WIDTH_BYTES * 8 / bpp); + format->format.height = clamp_t(unsigned int, format->format.height, + CAL_MIN_HEIGHT_LINES, + CAL_MAX_HEIGHT_LINES); + format->format.code = fmtinfo->code; + + /* Store the format and propagate it to the source pad. */ + fmt = cal_camerarx_get_pad_format(phy, cfg, CAL_CAMERARX_PAD_SINK, + format->which); + *fmt = format->format; + + fmt = cal_camerarx_get_pad_format(phy, cfg, CAL_CAMERARX_PAD_SOURCE, + format->which); + *fmt = format->format; + + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) + phy->fmtinfo = fmtinfo; + + return 0; +} + +static int cal_camerarx_sd_init_cfg(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg) +{ + struct v4l2_subdev_format format = { + .which = cfg ? V4L2_SUBDEV_FORMAT_TRY + : V4L2_SUBDEV_FORMAT_ACTIVE, + .pad = CAL_CAMERARX_PAD_SINK, + .format = { + .width = 640, + .height = 480, + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .field = V4L2_FIELD_NONE, + .colorspace = V4L2_COLORSPACE_SRGB, + .ycbcr_enc = V4L2_YCBCR_ENC_601, + .quantization = V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func = V4L2_XFER_FUNC_SRGB, + }, + }; + + return cal_camerarx_sd_set_fmt(sd, cfg, &format); +} + +static const struct v4l2_subdev_video_ops cal_camerarx_video_ops = { + .s_stream = cal_camerarx_sd_s_stream, +}; + +static const struct v4l2_subdev_pad_ops cal_camerarx_pad_ops = { + .init_cfg = cal_camerarx_sd_init_cfg, + .enum_mbus_code = cal_camerarx_sd_enum_mbus_code, + .enum_frame_size = cal_camerarx_sd_enum_frame_size, + .get_fmt = cal_camerarx_sd_get_fmt, + .set_fmt = cal_camerarx_sd_set_fmt, +}; + +static const struct v4l2_subdev_ops cal_camerarx_subdev_ops = { + .video = &cal_camerarx_video_ops, + .pad = &cal_camerarx_pad_ops, +}; + +static struct media_entity_operations cal_camerarx_media_ops = { + .link_validate = v4l2_subdev_link_validate, +}; + +/* ------------------------------------------------------------------ + * Create and Destroy + * ------------------------------------------------------------------ + */ + struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal, unsigned int instance) { struct platform_device *pdev = to_platform_device(cal->dev); struct cal_camerarx *phy; + struct v4l2_subdev *sd; int ret; phy = kzalloc(sizeof(*phy), GFP_KERNEL); @@ -632,9 +826,31 @@ struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal, if (ret) goto error; + /* Initialize the V4L2 subdev and media entity. */ + sd = &phy->subdev; + v4l2_subdev_init(sd, &cal_camerarx_subdev_ops); + sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + snprintf(sd->name, sizeof(sd->name), "CAMERARX%u", instance); + sd->dev = cal->dev; + + phy->pads[CAL_CAMERARX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + phy->pads[CAL_CAMERARX_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + sd->entity.ops = &cal_camerarx_media_ops; + ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(phy->pads), + phy->pads); + if (ret) + goto error; + + cal_camerarx_sd_init_cfg(sd, NULL); + + ret = v4l2_device_register_subdev(&cal->v4l2_dev, sd); + if (ret) + goto error; + return phy; error: + media_entity_cleanup(&phy->subdev.entity); kfree(phy); return ERR_PTR(ret); } @@ -644,6 +860,9 @@ void cal_camerarx_destroy(struct cal_camerarx *phy) if (!phy) return; + v4l2_device_unregister_subdev(&phy->subdev); + media_entity_cleanup(&phy->subdev.entity); + of_node_put(phy->sensor_ep_node); of_node_put(phy->sensor_node); kfree(phy); } diff --git a/drivers/media/platform/ti-vpe/cal-video.c b/drivers/media/platform/ti-vpe/cal-video.c index df472a175e83..779f1e1bc529 100644 --- a/drivers/media/platform/ti-vpe/cal-video.c +++ b/drivers/media/platform/ti-vpe/cal-video.c @@ -9,7 +9,6 @@ * Laurent Pinchart <laurent.pinchart@ideasonboard.com> */ -#include <linux/delay.h> #include <linux/ioctl.h> #include <linux/pm_runtime.h> #include <linux/videodev2.h> @@ -26,107 +25,6 @@ #include "cal.h" -/* ------------------------------------------------------------------ - * Format Handling - * ------------------------------------------------------------------ - */ - -static const struct cal_fmt cal_formats[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .code = MEDIA_BUS_FMT_YUYV8_2X8, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_UYVY, - .code = MEDIA_BUS_FMT_UYVY8_2X8, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_YVYU, - .code = MEDIA_BUS_FMT_YVYU8_2X8, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_VYUY, - .code = MEDIA_BUS_FMT_VYUY8_2X8, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */ - .code = MEDIA_BUS_FMT_RGB565_2X8_LE, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */ - .code = MEDIA_BUS_FMT_RGB565_2X8_BE, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */ - .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */ - .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, - .bpp = 16, - }, { - .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */ - .code = MEDIA_BUS_FMT_RGB888_2X12_LE, - .bpp = 24, - }, { - .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */ - .code = MEDIA_BUS_FMT_RGB888_2X12_BE, - .bpp = 24, - }, { - .fourcc = V4L2_PIX_FMT_RGB32, /* argb */ - .code = MEDIA_BUS_FMT_ARGB8888_1X32, - .bpp = 32, - }, { - .fourcc = V4L2_PIX_FMT_SBGGR8, - .code = MEDIA_BUS_FMT_SBGGR8_1X8, - .bpp = 8, - }, { - .fourcc = V4L2_PIX_FMT_SGBRG8, - .code = MEDIA_BUS_FMT_SGBRG8_1X8, - .bpp = 8, - }, { - .fourcc = V4L2_PIX_FMT_SGRBG8, - .code = MEDIA_BUS_FMT_SGRBG8_1X8, - .bpp = 8, - }, { - .fourcc = V4L2_PIX_FMT_SRGGB8, - .code = MEDIA_BUS_FMT_SRGGB8_1X8, - .bpp = 8, - }, { - .fourcc = V4L2_PIX_FMT_SBGGR10, - .code = MEDIA_BUS_FMT_SBGGR10_1X10, - .bpp = 10, - }, { - .fourcc = V4L2_PIX_FMT_SGBRG10, - .code = MEDIA_BUS_FMT_SGBRG10_1X10, - .bpp = 10, - }, { - .fourcc = V4L2_PIX_FMT_SGRBG10, - .code = MEDIA_BUS_FMT_SGRBG10_1X10, - .bpp = 10, - }, { - .fourcc = V4L2_PIX_FMT_SRGGB10, - .code = MEDIA_BUS_FMT_SRGGB10_1X10, - .bpp = 10, - }, { - .fourcc = V4L2_PIX_FMT_SBGGR12, - .code = MEDIA_BUS_FMT_SBGGR12_1X12, - .bpp = 12, - }, { - .fourcc = V4L2_PIX_FMT_SGBRG12, - .code = MEDIA_BUS_FMT_SGBRG12_1X12, - .bpp = 12, - }, { - .fourcc = V4L2_PIX_FMT_SGRBG12, - .code = MEDIA_BUS_FMT_SGRBG12_1X12, - .bpp = 12, - }, { - .fourcc = V4L2_PIX_FMT_SRGGB12, - .code = MEDIA_BUS_FMT_SRGGB12_1X12, - .bpp = 12, - }, -}; - /* Print Four-character-code (FOURCC) */ static char *fourcc_to_str(u32 fmt) { @@ -146,31 +44,31 @@ static char *fourcc_to_str(u32 fmt) * ------------------------------------------------------------------ */ -static const struct cal_fmt *find_format_by_pix(struct cal_ctx *ctx, - u32 pixelformat) +static const struct cal_format_info *find_format_by_pix(struct cal_ctx *ctx, + u32 pixelformat) { - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; unsigned int k; for (k = 0; k < ctx->num_active_fmt; k++) { - fmt = ctx->active_fmt[k]; - if (fmt->fourcc == pixelformat) - return fmt; + fmtinfo = ctx->active_fmt[k]; + if (fmtinfo->fourcc == pixelformat) + return fmtinfo; } return NULL; } -static const struct cal_fmt *find_format_by_code(struct cal_ctx *ctx, - u32 code) +static const struct cal_format_info *find_format_by_code(struct cal_ctx *ctx, + u32 code) { - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; unsigned int k; for (k = 0; k < ctx->num_active_fmt; k++) { - fmt = ctx->active_fmt[k]; - if (fmt->code == code) - return fmt; + fmtinfo = ctx->active_fmt[k]; + if (fmtinfo->code == code) + return fmtinfo; } return NULL; @@ -193,14 +91,14 @@ static int cal_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f) { struct cal_ctx *ctx = video_drvdata(file); - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; if (f->index >= ctx->num_active_fmt) return -EINVAL; - fmt = ctx->active_fmt[f->index]; + fmtinfo = ctx->active_fmt[f->index]; - f->pixelformat = fmt->fourcc; + f->pixelformat = fmtinfo->fourcc; f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; return 0; } @@ -248,27 +146,23 @@ static int __subdev_set_format(struct cal_ctx *ctx, return 0; } -static int cal_calc_format_size(struct cal_ctx *ctx, - const struct cal_fmt *fmt, - struct v4l2_format *f) +static void cal_calc_format_size(struct cal_ctx *ctx, + const struct cal_format_info *fmtinfo, + struct v4l2_format *f) { u32 bpl, max_width; - if (!fmt) { - ctx_dbg(3, ctx, "No cal_fmt provided!\n"); - return -EINVAL; - } - /* * Maximum width is bound by the DMA max width in bytes. * We need to recalculate the actual maxi width depending on the * number of bytes per pixels required. */ - max_width = MAX_WIDTH_BYTES / (ALIGN(fmt->bpp, 8) >> 3); + max_width = CAL_MAX_WIDTH_BYTES / (ALIGN(fmtinfo->bpp, 8) >> 3); v4l_bound_align_image(&f->fmt.pix.width, 48, max_width, 2, - &f->fmt.pix.height, 32, MAX_HEIGHT_LINES, 0, 0); + &f->fmt.pix.height, 32, CAL_MAX_HEIGHT_LINES, + 0, 0); - bpl = (f->fmt.pix.width * ALIGN(fmt->bpp, 8)) >> 3; + bpl = (f->fmt.pix.width * ALIGN(fmtinfo->bpp, 8)) >> 3; f->fmt.pix.bytesperline = ALIGN(bpl, 16); f->fmt.pix.sizeimage = f->fmt.pix.height * @@ -278,8 +172,6 @@ static int cal_calc_format_size(struct cal_ctx *ctx, __func__, fourcc_to_str(f->fmt.pix.pixelformat), f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.bytesperline, f->fmt.pix.sizeimage); - - return 0; } static int cal_g_fmt_vid_cap(struct file *file, void *priv, @@ -296,18 +188,18 @@ static int cal_try_fmt_vid_cap(struct file *file, void *priv, struct v4l2_format *f) { struct cal_ctx *ctx = video_drvdata(file); - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; struct v4l2_subdev_frame_size_enum fse; int ret, found; - fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat); - if (!fmt) { + fmtinfo = find_format_by_pix(ctx, f->fmt.pix.pixelformat); + if (!fmtinfo) { ctx_dbg(3, ctx, "Fourcc format (0x%08x) not found.\n", f->fmt.pix.pixelformat); /* Just get the first one enumerated */ - fmt = ctx->active_fmt[0]; - f->fmt.pix.pixelformat = fmt->fourcc; + fmtinfo = ctx->active_fmt[0]; + f->fmt.pix.pixelformat = fmtinfo->fourcc; } f->fmt.pix.field = ctx->v_fmt.fmt.pix.field; @@ -316,7 +208,7 @@ static int cal_try_fmt_vid_cap(struct file *file, void *priv, ret = 0; found = false; fse.pad = 0; - fse.code = fmt->code; + fse.code = fmtinfo->code; fse.which = V4L2_SUBDEV_FORMAT_ACTIVE; for (fse.index = 0; ; fse.index++) { ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_size, @@ -348,7 +240,8 @@ static int cal_try_fmt_vid_cap(struct file *file, void *priv, * updated properly during s_fmt */ f->fmt.pix.colorspace = ctx->v_fmt.fmt.pix.colorspace; - return cal_calc_format_size(ctx, fmt, f); + cal_calc_format_size(ctx, fmtinfo, f); + return 0; } static int cal_s_fmt_vid_cap(struct file *file, void *priv, @@ -356,8 +249,11 @@ static int cal_s_fmt_vid_cap(struct file *file, void *priv, { struct cal_ctx *ctx = video_drvdata(file); struct vb2_queue *q = &ctx->vb_vidq; - const struct cal_fmt *fmt; - struct v4l2_mbus_framefmt mbus_fmt; + struct v4l2_subdev_format sd_fmt = { + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + .pad = CAL_CAMERARX_PAD_SINK, + }; + const struct cal_format_info *fmtinfo; int ret; if (vb2_is_busy(q)) { @@ -369,28 +265,31 @@ static int cal_s_fmt_vid_cap(struct file *file, void *priv, if (ret < 0) return ret; - fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat); + fmtinfo = find_format_by_pix(ctx, f->fmt.pix.pixelformat); - v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code); + v4l2_fill_mbus_format(&sd_fmt.format, &f->fmt.pix, fmtinfo->code); - ret = __subdev_set_format(ctx, &mbus_fmt); + ret = __subdev_set_format(ctx, &sd_fmt.format); if (ret) return ret; /* Just double check nothing has gone wrong */ - if (mbus_fmt.code != fmt->code) { + if (sd_fmt.format.code != fmtinfo->code) { ctx_dbg(3, ctx, "%s subdev changed format on us, this should not happen\n", __func__); return -EINVAL; } - v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt); + v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &sd_fmt.format); ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc; - cal_calc_format_size(ctx, fmt, &ctx->v_fmt); - ctx->fmt = fmt; - ctx->m_fmt = mbus_fmt; + ctx->v_fmt.fmt.pix.pixelformat = fmtinfo->fourcc; + ctx->v_fmt.fmt.pix.field = sd_fmt.format.field; + cal_calc_format_size(ctx, fmtinfo, &ctx->v_fmt); + + v4l2_subdev_call(&ctx->phy->subdev, pad, set_fmt, NULL, &sd_fmt); + + ctx->fmtinfo = fmtinfo; *f = ctx->v_fmt; return 0; @@ -400,13 +299,13 @@ static int cal_enum_framesizes(struct file *file, void *fh, struct v4l2_frmsizeenum *fsize) { struct cal_ctx *ctx = video_drvdata(file); - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; struct v4l2_subdev_frame_size_enum fse; int ret; /* check for valid format */ - fmt = find_format_by_pix(ctx, fsize->pixel_format); - if (!fmt) { + fmtinfo = find_format_by_pix(ctx, fsize->pixel_format); + if (!fmtinfo) { ctx_dbg(3, ctx, "Invalid pixel code: %x\n", fsize->pixel_format); return -EINVAL; @@ -414,7 +313,7 @@ static int cal_enum_framesizes(struct file *file, void *fh, fse.index = fsize->index; fse.pad = 0; - fse.code = fmt->code; + fse.code = fmtinfo->code; fse.which = V4L2_SUBDEV_FORMAT_ACTIVE; ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_size, NULL, @@ -460,7 +359,7 @@ static int cal_enum_frameintervals(struct file *file, void *priv, struct v4l2_frmivalenum *fival) { struct cal_ctx *ctx = video_drvdata(file); - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; struct v4l2_subdev_frame_interval_enum fie = { .index = fival->index, .width = fival->width, @@ -469,11 +368,11 @@ static int cal_enum_frameintervals(struct file *file, void *priv, }; int ret; - fmt = find_format_by_pix(ctx, fival->pixel_format); - if (!fmt) + fmtinfo = find_format_by_pix(ctx, fival->pixel_format); + if (!fmtinfo) return -EINVAL; - fie.code = fmt->code; + fie.code = fmtinfo->code; ret = v4l2_subdev_call(ctx->phy->sensor, pad, enum_frame_interval, NULL, &fie); if (ret) @@ -488,7 +387,6 @@ static const struct v4l2_file_operations cal_fops = { .owner = THIS_MODULE, .open = v4l2_fh_open, .release = vb2_fop_release, - .read = vb2_fop_read, .poll = vb2_fop_poll, .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ .mmap = vb2_fop_mmap, @@ -555,9 +453,6 @@ static int cal_buffer_prepare(struct vb2_buffer *vb) vb.vb2_buf); unsigned long size; - if (WARN_ON(!ctx->fmt)) - return -EINVAL; - size = ctx->v_fmt.fmt.pix.sizeimage; if (vb2_plane_size(vb, 0) < size) { ctx_err(ctx, @@ -575,121 +470,88 @@ static void cal_buffer_queue(struct vb2_buffer *vb) struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); struct cal_buffer *buf = container_of(vb, struct cal_buffer, vb.vb2_buf); - struct cal_dmaqueue *vidq = &ctx->vidq; unsigned long flags; /* recheck locking */ - spin_lock_irqsave(&ctx->slock, flags); - list_add_tail(&buf->list, &vidq->active); - spin_unlock_irqrestore(&ctx->slock, flags); + spin_lock_irqsave(&ctx->dma.lock, flags); + list_add_tail(&buf->list, &ctx->dma.queue); + spin_unlock_irqrestore(&ctx->dma.lock, flags); } -static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) +static void cal_release_buffers(struct cal_ctx *ctx, + enum vb2_buffer_state state) { - struct cal_ctx *ctx = vb2_get_drv_priv(vq); - struct cal_dmaqueue *dma_q = &ctx->vidq; struct cal_buffer *buf, *tmp; - unsigned long addr; - unsigned long flags; - int ret; - spin_lock_irqsave(&ctx->slock, flags); - if (list_empty(&dma_q->active)) { - spin_unlock_irqrestore(&ctx->slock, flags); - ctx_dbg(3, ctx, "buffer queue is empty\n"); - return -EIO; + /* Release all queued buffers. */ + spin_lock_irq(&ctx->dma.lock); + + list_for_each_entry_safe(buf, tmp, &ctx->dma.queue, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, state); + } + + if (ctx->dma.pending) { + vb2_buffer_done(&ctx->dma.pending->vb.vb2_buf, state); + ctx->dma.pending = NULL; + } + + if (ctx->dma.active) { + vb2_buffer_done(&ctx->dma.active->vb.vb2_buf, state); + ctx->dma.active = NULL; } - buf = list_entry(dma_q->active.next, struct cal_buffer, list); - ctx->cur_frm = buf; - ctx->next_frm = buf; + spin_unlock_irq(&ctx->dma.lock); +} + +static int cal_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct cal_ctx *ctx = vb2_get_drv_priv(vq); + struct cal_buffer *buf; + dma_addr_t addr; + int ret; + + spin_lock_irq(&ctx->dma.lock); + buf = list_first_entry(&ctx->dma.queue, struct cal_buffer, list); + ctx->dma.pending = buf; list_del(&buf->list); - spin_unlock_irqrestore(&ctx->slock, flags); + spin_unlock_irq(&ctx->dma.lock); - addr = vb2_dma_contig_plane_dma_addr(&ctx->cur_frm->vb.vb2_buf, 0); - ctx->sequence = 0; + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); pm_runtime_get_sync(ctx->cal->dev); - cal_ctx_csi2_config(ctx); - cal_ctx_pix_proc_config(ctx); - cal_ctx_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline, - ctx->v_fmt.fmt.pix.height); + cal_ctx_set_dma_addr(ctx, addr); + cal_ctx_start(ctx); - cal_camerarx_enable_irqs(ctx->phy); - - ret = cal_camerarx_start(ctx->phy, ctx->fmt); + ret = v4l2_subdev_call(&ctx->phy->subdev, video, s_stream, 1); if (ret) goto err; - cal_ctx_wr_dma_addr(ctx, addr); - cal_camerarx_ppi_enable(ctx->phy); - if (cal_debug >= 4) cal_quickdump_regs(ctx->cal); return 0; err: - spin_lock_irqsave(&ctx->slock, flags); - vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED); - ctx->cur_frm = NULL; - ctx->next_frm = NULL; - list_for_each_entry_safe(buf, tmp, &dma_q->active, list) { - list_del(&buf->list); - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); - } - spin_unlock_irqrestore(&ctx->slock, flags); + cal_ctx_stop(ctx); + pm_runtime_put_sync(ctx->cal->dev); + + cal_release_buffers(ctx, VB2_BUF_STATE_QUEUED); return ret; } static void cal_stop_streaming(struct vb2_queue *vq) { struct cal_ctx *ctx = vb2_get_drv_priv(vq); - struct cal_dmaqueue *dma_q = &ctx->vidq; - struct cal_buffer *buf, *tmp; - unsigned long timeout; - unsigned long flags; - bool dma_act; - - cal_camerarx_ppi_disable(ctx->phy); - - /* wait for stream and dma to finish */ - dma_act = true; - timeout = jiffies + msecs_to_jiffies(500); - while (dma_act && time_before(jiffies, timeout)) { - msleep(50); - - spin_lock_irqsave(&ctx->slock, flags); - dma_act = ctx->dma_act; - spin_unlock_irqrestore(&ctx->slock, flags); - } - - if (dma_act) - ctx_err(ctx, "failed to disable dma cleanly\n"); - - cal_camerarx_disable_irqs(ctx->phy); - cal_camerarx_stop(ctx->phy); - /* Release all active buffers */ - spin_lock_irqsave(&ctx->slock, flags); - list_for_each_entry_safe(buf, tmp, &dma_q->active, list) { - list_del(&buf->list); - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } + cal_ctx_stop(ctx); - if (ctx->cur_frm == ctx->next_frm) { - vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR); - } else { - vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR); - vb2_buffer_done(&ctx->next_frm->vb.vb2_buf, - VB2_BUF_STATE_ERROR); - } - ctx->cur_frm = NULL; - ctx->next_frm = NULL; - spin_unlock_irqrestore(&ctx->slock, flags); + v4l2_subdev_call(&ctx->phy->subdev, video, s_stream, 0); pm_runtime_put_sync(ctx->cal->dev); + + cal_release_buffers(ctx, VB2_BUF_STATE_ERROR); } static const struct vb2_ops cal_video_qops = { @@ -713,20 +575,19 @@ static const struct video_device cal_videodev = { .ioctl_ops = &cal_ioctl_ops, .minor = -1, .release = video_device_release_empty, - .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | - V4L2_CAP_READWRITE, + .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING, }; static int cal_ctx_v4l2_init_formats(struct cal_ctx *ctx) { struct v4l2_subdev_mbus_code_enum mbus_code; struct v4l2_mbus_framefmt mbus_fmt; - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; unsigned int i, j, k; int ret = 0; /* Enumerate sub device formats and enable all matching local formats */ - ctx->active_fmt = devm_kcalloc(ctx->cal->dev, ARRAY_SIZE(cal_formats), + ctx->active_fmt = devm_kcalloc(ctx->cal->dev, cal_num_formats, sizeof(*ctx->active_fmt), GFP_KERNEL); ctx->num_active_fmt = 0; @@ -744,15 +605,15 @@ static int cal_ctx_v4l2_init_formats(struct cal_ctx *ctx) "subdev %s: code: %04x idx: %u\n", ctx->phy->sensor->name, mbus_code.code, j); - for (k = 0; k < ARRAY_SIZE(cal_formats); k++) { - const struct cal_fmt *fmt = &cal_formats[k]; + for (k = 0; k < cal_num_formats; k++) { + fmtinfo = &cal_formats[k]; - if (mbus_code.code == fmt->code) { - ctx->active_fmt[i] = fmt; + if (mbus_code.code == fmtinfo->code) { + ctx->active_fmt[i] = fmtinfo; ctx_dbg(2, ctx, "matched fourcc: %s: code: %04x idx: %u\n", - fourcc_to_str(fmt->fourcc), - fmt->code, i); + fourcc_to_str(fmtinfo->fourcc), + fmtinfo->code, i); ctx->num_active_fmt = ++i; } } @@ -768,20 +629,20 @@ static int cal_ctx_v4l2_init_formats(struct cal_ctx *ctx) if (ret) return ret; - fmt = find_format_by_code(ctx, mbus_fmt.code); - if (!fmt) { + fmtinfo = find_format_by_code(ctx, mbus_fmt.code); + if (!fmtinfo) { ctx_dbg(3, ctx, "mbus code format (0x%08x) not found.\n", mbus_fmt.code); return -EINVAL; } - /* Save current subdev format */ + /* Save current format */ v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt); ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc; - cal_calc_format_size(ctx, fmt, &ctx->v_fmt); - ctx->fmt = fmt; - ctx->m_fmt = mbus_fmt; + ctx->v_fmt.fmt.pix.pixelformat = fmtinfo->fourcc; + ctx->v_fmt.fmt.pix.field = mbus_fmt.field; + cal_calc_format_size(ctx, fmtinfo, &ctx->v_fmt); + ctx->fmtinfo = fmtinfo; return 0; } @@ -809,6 +670,18 @@ int cal_ctx_v4l2_register(struct cal_ctx *ctx) return ret; } + ret = media_create_pad_link(&ctx->phy->subdev.entity, + CAL_CAMERARX_PAD_SOURCE, + &vfd->entity, 0, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + ctx_err(ctx, "Failed to create media link for context %u\n", + ctx->index); + video_unregister_device(vfd); + return ret; + } + ctx_info(ctx, "V4L2 device registered as %s\n", video_device_node_name(vfd)); @@ -830,13 +703,14 @@ int cal_ctx_v4l2_init(struct cal_ctx *ctx) struct vb2_queue *q = &ctx->vb_vidq; int ret; - INIT_LIST_HEAD(&ctx->vidq.active); - spin_lock_init(&ctx->slock); + INIT_LIST_HEAD(&ctx->dma.queue); + spin_lock_init(&ctx->dma.lock); mutex_init(&ctx->mutex); + init_waitqueue_head(&ctx->dma.wait); /* Initialize the vb2 queue. */ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; - q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; + q->io_modes = VB2_MMAP | VB2_DMABUF; q->drv_priv = ctx; q->buf_struct_size = sizeof(struct cal_buffer); q->ops = &cal_video_qops; diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 59a0266b1f39..fa0931788040 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -44,6 +44,133 @@ module_param_named(debug, cal_debug, uint, 0644); MODULE_PARM_DESC(debug, "activates debug info"); /* ------------------------------------------------------------------ + * Format Handling + * ------------------------------------------------------------------ + */ + +const struct cal_format_info cal_formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_YVYU, + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_VYUY, + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */ + .code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */ + .code = MEDIA_BUS_FMT_RGB565_2X8_BE, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */ + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */ + .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */ + .code = MEDIA_BUS_FMT_RGB888_2X12_LE, + .bpp = 24, + }, { + .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */ + .code = MEDIA_BUS_FMT_RGB888_2X12_BE, + .bpp = 24, + }, { + .fourcc = V4L2_PIX_FMT_RGB32, /* argb */ + .code = MEDIA_BUS_FMT_ARGB8888_1X32, + .bpp = 32, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR8, + .code = MEDIA_BUS_FMT_SBGGR8_1X8, + .bpp = 8, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG8, + .code = MEDIA_BUS_FMT_SGBRG8_1X8, + .bpp = 8, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG8, + .code = MEDIA_BUS_FMT_SGRBG8_1X8, + .bpp = 8, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB8, + .code = MEDIA_BUS_FMT_SRGGB8_1X8, + .bpp = 8, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR10, + .code = MEDIA_BUS_FMT_SBGGR10_1X10, + .bpp = 10, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG10, + .code = MEDIA_BUS_FMT_SGBRG10_1X10, + .bpp = 10, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG10, + .code = MEDIA_BUS_FMT_SGRBG10_1X10, + .bpp = 10, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB10, + .code = MEDIA_BUS_FMT_SRGGB10_1X10, + .bpp = 10, + }, { + .fourcc = V4L2_PIX_FMT_SBGGR12, + .code = MEDIA_BUS_FMT_SBGGR12_1X12, + .bpp = 12, + }, { + .fourcc = V4L2_PIX_FMT_SGBRG12, + .code = MEDIA_BUS_FMT_SGBRG12_1X12, + .bpp = 12, + }, { + .fourcc = V4L2_PIX_FMT_SGRBG12, + .code = MEDIA_BUS_FMT_SGRBG12_1X12, + .bpp = 12, + }, { + .fourcc = V4L2_PIX_FMT_SRGGB12, + .code = MEDIA_BUS_FMT_SRGGB12_1X12, + .bpp = 12, + }, +}; + +const unsigned int cal_num_formats = ARRAY_SIZE(cal_formats); + +const struct cal_format_info *cal_format_by_fourcc(u32 fourcc) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) { + if (cal_formats[i].fourcc == fourcc) + return &cal_formats[i]; + } + + return NULL; +} + +const struct cal_format_info *cal_format_by_code(u32 code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) { + if (cal_formats[i].code == code) + return &cal_formats[i]; + } + + return NULL; +} + +/* ------------------------------------------------------------------ * Platform Data * ------------------------------------------------------------------ */ @@ -136,12 +263,9 @@ void cal_quickdump_regs(struct cal_dev *cal) (__force const void *)cal->base, resource_size(cal->res), false); - for (i = 0; i < ARRAY_SIZE(cal->phy); ++i) { + for (i = 0; i < cal->data->num_csi2_phy; ++i) { struct cal_camerarx *phy = cal->phy[i]; - if (!phy) - continue; - cal_info(cal, "CSI2 Core %u Registers @ %pa:\n", i, &phy->res->start); print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4, @@ -156,7 +280,7 @@ void cal_quickdump_regs(struct cal_dev *cal) * ------------------------------------------------------------------ */ -void cal_ctx_csi2_config(struct cal_ctx *ctx) +static void cal_ctx_csi2_config(struct cal_ctx *ctx) { u32 val; @@ -181,11 +305,11 @@ void cal_ctx_csi2_config(struct cal_ctx *ctx) cal_read(ctx->cal, CAL_CSI2_CTX0(ctx->index))); } -void cal_ctx_pix_proc_config(struct cal_ctx *ctx) +static void cal_ctx_pix_proc_config(struct cal_ctx *ctx) { u32 val, extract, pack; - switch (ctx->fmt->bpp) { + switch (ctx->fmtinfo->bpp) { case 8: extract = CAL_PIX_PROC_EXTRACT_B8; pack = CAL_PIX_PROC_PACK_B8; @@ -214,7 +338,7 @@ void cal_ctx_pix_proc_config(struct cal_ctx *ctx) */ dev_warn_once(ctx->cal->dev, "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n", - __FILE__, __LINE__, __func__, ctx->fmt->bpp); + __FILE__, __LINE__, __func__, ctx->fmtinfo->bpp); extract = CAL_PIX_PROC_EXTRACT_B8; pack = CAL_PIX_PROC_PACK_B8; break; @@ -232,14 +356,15 @@ void cal_ctx_pix_proc_config(struct cal_ctx *ctx) cal_read(ctx->cal, CAL_PIX_PROC(ctx->index))); } -void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width, - unsigned int height) +static void cal_ctx_wr_dma_config(struct cal_ctx *ctx) { + unsigned int stride = ctx->v_fmt.fmt.pix.bytesperline; u32 val; val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index)); cal_set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK); - cal_set_field(&val, height, CAL_WR_DMA_CTRL_YSIZE_MASK); + cal_set_field(&val, ctx->v_fmt.fmt.pix.height, + CAL_WR_DMA_CTRL_YSIZE_MASK); cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT, CAL_WR_DMA_CTRL_DTAG_MASK); cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST, @@ -251,14 +376,8 @@ void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width, ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->index, cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index))); - /* - * width/16 not sure but giving it a whirl. - * zero does not work right - */ - cal_write_field(ctx->cal, - CAL_WR_DMA_OFST(ctx->index), - (width / 16), - CAL_WR_DMA_OFST_MASK); + cal_write_field(ctx->cal, CAL_WR_DMA_OFST(ctx->index), + stride / 16, CAL_WR_DMA_OFST_MASK); ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->index, cal_read(ctx->cal, CAL_WR_DMA_OFST(ctx->index))); @@ -266,11 +385,11 @@ void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width, /* 64 bit word means no skipping */ cal_set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK); /* - * (width*8)/64 this should be size of an entire line - * in 64bit word but 0 means all data until the end - * is detected automagically + * The XSIZE field is expressed in 64-bit units and prevents overflows + * in case of synchronization issues by limiting the number of bytes + * written per line. */ - cal_set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK); + cal_set_field(&val, stride / 8, CAL_WR_DMA_XSIZE_MASK); cal_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index), val); ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->index, cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->index))); @@ -287,9 +406,74 @@ void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width, ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", cal_read(ctx->cal, CAL_CTRL)); } -void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr) +void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr) +{ + cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), addr); +} + +static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx) +{ + u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->index)); + + cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_DIS, + CAL_WR_DMA_CTRL_MODE_MASK); + cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->index), val); +} + +static bool cal_ctx_wr_dma_stopped(struct cal_ctx *ctx) { - cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->index), dmaaddr); + bool stopped; + + spin_lock_irq(&ctx->dma.lock); + stopped = ctx->dma.state == CAL_DMA_STOPPED; + spin_unlock_irq(&ctx->dma.lock); + + return stopped; +} + +void cal_ctx_start(struct cal_ctx *ctx) +{ + ctx->sequence = 0; + ctx->dma.state = CAL_DMA_RUNNING; + + /* Configure the CSI-2, pixel processing and write DMA contexts. */ + cal_ctx_csi2_config(ctx); + cal_ctx_pix_proc_config(ctx); + cal_ctx_wr_dma_config(ctx); + + /* Enable IRQ_WDMA_END and IRQ_WDMA_START. */ + cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1), + CAL_HL_IRQ_MASK(ctx->index)); + cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2), + CAL_HL_IRQ_MASK(ctx->index)); +} + +void cal_ctx_stop(struct cal_ctx *ctx) +{ + long timeout; + + /* + * Request DMA stop and wait until it completes. If completion times + * out, forcefully disable the DMA. + */ + spin_lock_irq(&ctx->dma.lock); + ctx->dma.state = CAL_DMA_STOP_REQUESTED; + spin_unlock_irq(&ctx->dma.lock); + + timeout = wait_event_timeout(ctx->dma.wait, cal_ctx_wr_dma_stopped(ctx), + msecs_to_jiffies(500)); + if (!timeout) { + ctx_err(ctx, "failed to disable dma cleanly\n"); + cal_ctx_wr_dma_disable(ctx); + } + + /* Disable IRQ_WDMA_END and IRQ_WDMA_START. */ + cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1), + CAL_HL_IRQ_MASK(ctx->index)); + cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2), + CAL_HL_IRQ_MASK(ctx->index)); + + ctx->dma.state = CAL_DMA_STOPPED; } /* ------------------------------------------------------------------ @@ -297,35 +481,70 @@ void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr) * ------------------------------------------------------------------ */ -static inline void cal_schedule_next_buffer(struct cal_ctx *ctx) +static inline void cal_irq_wdma_start(struct cal_ctx *ctx) { - struct cal_dmaqueue *dma_q = &ctx->vidq; - struct cal_buffer *buf; - unsigned long addr; + spin_lock(&ctx->dma.lock); + + if (ctx->dma.state == CAL_DMA_STOP_REQUESTED) { + /* + * If a stop is requested, disable the write DMA context + * immediately. The CAL_WR_DMA_CTRL_j.MODE field is shadowed, + * the current frame will complete and the DMA will then stop. + */ + cal_ctx_wr_dma_disable(ctx); + ctx->dma.state = CAL_DMA_STOP_PENDING; + } else if (!list_empty(&ctx->dma.queue) && !ctx->dma.pending) { + /* + * Otherwise, if a new buffer is available, queue it to the + * hardware. + */ + struct cal_buffer *buf; + dma_addr_t addr; + + buf = list_first_entry(&ctx->dma.queue, struct cal_buffer, + list); + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + cal_ctx_set_dma_addr(ctx, addr); - buf = list_entry(dma_q->active.next, struct cal_buffer, list); - ctx->next_frm = buf; - list_del(&buf->list); + ctx->dma.pending = buf; + list_del(&buf->list); + } - addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); - cal_ctx_wr_dma_addr(ctx, addr); + spin_unlock(&ctx->dma.lock); } -static inline void cal_process_buffer_complete(struct cal_ctx *ctx) +static inline void cal_irq_wdma_end(struct cal_ctx *ctx) { - ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns(); - ctx->cur_frm->vb.field = ctx->m_fmt.field; - ctx->cur_frm->vb.sequence = ctx->sequence++; + struct cal_buffer *buf = NULL; + + spin_lock(&ctx->dma.lock); + + /* If the DMA context was stopping, it is now stopped. */ + if (ctx->dma.state == CAL_DMA_STOP_PENDING) { + ctx->dma.state = CAL_DMA_STOPPED; + wake_up(&ctx->dma.wait); + } - vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE); - ctx->cur_frm = ctx->next_frm; + /* If a new buffer was queued, complete the current buffer. */ + if (ctx->dma.pending) { + buf = ctx->dma.active; + ctx->dma.active = ctx->dma.pending; + ctx->dma.pending = NULL; + } + + spin_unlock(&ctx->dma.lock); + + if (buf) { + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.field = ctx->v_fmt.fmt.pix.field; + buf->vb.sequence = ctx->sequence++; + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + } } static irqreturn_t cal_irq(int irq_cal, void *data) { struct cal_dev *cal = data; - struct cal_ctx *ctx; - struct cal_dmaqueue *dma_q; u32 status; status = cal_read(cal, CAL_HL_IRQSTATUS(0)); @@ -337,7 +556,7 @@ static irqreturn_t cal_irq(int irq_cal, void *data) if (status & CAL_HL_IRQ_OCPO_ERR_MASK) dev_err_ratelimited(cal->dev, "OCPO ERROR\n"); - for (i = 0; i < CAL_NUM_CSI2_PORTS; ++i) { + for (i = 0; i < cal->data->num_csi2_phy; ++i) { if (status & CAL_HL_IRQ_CIO_MASK(i)) { u32 cio_stat = cal_read(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i)); @@ -360,17 +579,8 @@ static irqreturn_t cal_irq(int irq_cal, void *data) cal_write(cal, CAL_HL_IRQSTATUS(1), status); for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) { - if (status & CAL_HL_IRQ_MASK(i)) { - ctx = cal->ctx[i]; - - spin_lock(&ctx->slock); - ctx->dma_act = false; - - if (ctx->cur_frm != ctx->next_frm) - cal_process_buffer_complete(ctx); - - spin_unlock(&ctx->slock); - } + if (status & CAL_HL_IRQ_MASK(i)) + cal_irq_wdma_end(cal->ctx[i]); } } @@ -383,17 +593,8 @@ static irqreturn_t cal_irq(int irq_cal, void *data) cal_write(cal, CAL_HL_IRQSTATUS(2), status); for (i = 0; i < ARRAY_SIZE(cal->ctx); ++i) { - if (status & CAL_HL_IRQ_MASK(i)) { - ctx = cal->ctx[i]; - dma_q = &ctx->vidq; - - spin_lock(&ctx->slock); - ctx->dma_act = true; - if (!list_empty(&dma_q->active) && - ctx->cur_frm == ctx->next_frm) - cal_schedule_next_buffer(ctx); - spin_unlock(&ctx->slock); - } + if (status & CAL_HL_IRQ_MASK(i)) + cal_irq_wdma_start(cal->ctx[i]); } } @@ -406,7 +607,7 @@ static irqreturn_t cal_irq(int irq_cal, void *data) */ struct cal_v4l2_async_subdev { - struct v4l2_async_subdev asd; + struct v4l2_async_subdev asd; /* Must be first */ struct cal_camerarx *phy; }; @@ -421,6 +622,8 @@ static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier, struct v4l2_async_subdev *asd) { struct cal_camerarx *phy = to_cal_asd(asd)->phy; + int pad; + int ret; if (phy->sensor) { phy_info(phy, "Rejecting subdev %s (Already set!!)", @@ -431,6 +634,25 @@ static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier, phy->sensor = subdev; phy_dbg(1, phy, "Using sensor %s for capture\n", subdev->name); + pad = media_entity_get_fwnode_pad(&subdev->entity, + of_fwnode_handle(phy->sensor_ep_node), + MEDIA_PAD_FL_SOURCE); + if (pad < 0) { + phy_err(phy, "Sensor %s has no connected source pad\n", + subdev->name); + return pad; + } + + ret = media_create_pad_link(&subdev->entity, pad, + &phy->subdev.entity, CAL_CAMERARX_PAD_SINK, + MEDIA_LNK_FL_IMMUTABLE | + MEDIA_LNK_FL_ENABLED); + if (ret) { + phy_err(phy, "Failed to create media link for sensor %s\n", + subdev->name); + return ret; + } + return 0; } @@ -460,26 +682,24 @@ static int cal_async_notifier_register(struct cal_dev *cal) v4l2_async_notifier_init(&cal->notifier); cal->notifier.ops = &cal_async_notifier_ops; - for (i = 0; i < ARRAY_SIZE(cal->phy); ++i) { + for (i = 0; i < cal->data->num_csi2_phy; ++i) { struct cal_camerarx *phy = cal->phy[i]; struct cal_v4l2_async_subdev *casd; - struct v4l2_async_subdev *asd; struct fwnode_handle *fwnode; - if (!phy || !phy->sensor_node) + if (!phy->sensor_node) continue; fwnode = of_fwnode_handle(phy->sensor_node); - asd = v4l2_async_notifier_add_fwnode_subdev(&cal->notifier, - fwnode, - sizeof(*asd)); - if (IS_ERR(asd)) { + casd = v4l2_async_notifier_add_fwnode_subdev(&cal->notifier, + fwnode, + struct cal_v4l2_async_subdev); + if (IS_ERR(casd)) { phy_err(phy, "Failed to add subdev to notifier\n"); - ret = PTR_ERR(asd); + ret = PTR_ERR(casd); goto error; } - casd = to_cal_asd(asd); casd->phy = phy; } @@ -797,6 +1017,11 @@ static int cal_probe(struct platform_device *pdev) cal_get_hwinfo(cal); pm_runtime_put_sync(&pdev->dev); + /* Initialize the media device. */ + ret = cal_media_init(cal); + if (ret < 0) + goto error_pm_runtime; + /* Create CAMERARX PHYs. */ for (i = 0; i < cal->data->num_csi2_phy; ++i) { cal->phy[i] = cal_camerarx_create(cal, i); @@ -816,11 +1041,6 @@ static int cal_probe(struct platform_device *pdev) goto error_camerarx; } - /* Initialize the media device. */ - ret = cal_media_init(cal); - if (ret < 0) - goto error_camerarx; - /* Create contexts. */ for (i = 0; i < cal->data->num_csi2_phy; ++i) { if (!cal->phy[i]->sensor_node) @@ -848,12 +1068,12 @@ error_context: cal_ctx_v4l2_cleanup(ctx); } - cal_media_cleanup(cal); - error_camerarx: - for (i = 0; i < ARRAY_SIZE(cal->phy); i++) + for (i = 0; i < cal->data->num_csi2_phy; i++) cal_camerarx_destroy(cal->phy[i]); + cal_media_cleanup(cal); + error_pm_runtime: pm_runtime_disable(&pdev->dev); @@ -878,7 +1098,7 @@ static int cal_remove(struct platform_device *pdev) cal_media_cleanup(cal); - for (i = 0; i < ARRAY_SIZE(cal->phy); i++) + for (i = 0; i < cal->data->num_csi2_phy; i++) cal_camerarx_destroy(cal->phy[i]); pm_runtime_put_sync(&pdev->dev); @@ -890,16 +1110,23 @@ static int cal_remove(struct platform_device *pdev) static int cal_runtime_resume(struct device *dev) { struct cal_dev *cal = dev_get_drvdata(dev); + unsigned int i; if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) { /* * Apply errata on both port everytime we (re-)enable * the clock */ - cal_camerarx_i913_errata(cal->phy[0]); - cal_camerarx_i913_errata(cal->phy[1]); + for (i = 0; i < cal->data->num_csi2_phy; i++) + cal_camerarx_i913_errata(cal->phy[i]); } + /* + * Enable global interrupts that are not related to a particular + * CAMERARAX or context. + */ + cal_write(cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK); + return 0; } diff --git a/drivers/media/platform/ti-vpe/cal.h b/drivers/media/platform/ti-vpe/cal.h index 4123405ee0cf..d471b7f82519 100644 --- a/drivers/media/platform/ti-vpe/cal.h +++ b/drivers/media/platform/ti-vpe/cal.h @@ -17,6 +17,7 @@ #include <linux/mutex.h> #include <linux/spinlock.h> #include <linux/videodev2.h> +#include <linux/wait.h> #include <media/media-device.h> #include <media/v4l2-async.h> @@ -24,21 +25,32 @@ #include <media/v4l2-dev.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> +#include <media/v4l2-subdev.h> #include <media/videobuf2-v4l2.h> #define CAL_MODULE_NAME "cal" #define CAL_NUM_CONTEXT 2 #define CAL_NUM_CSI2_PORTS 2 -#define MAX_WIDTH_BYTES (8192 * 8) -#define MAX_HEIGHT_LINES 16383 +/* + * The width is limited by the size of the CAL_WR_DMA_XSIZE_j.XSIZE field, + * expressed in multiples of 64 bits. The height is limited by the size of the + * CAL_CSI2_CTXi_j.CTXi_LINES and CAL_WR_DMA_CTRL_j.YSIZE fields, expressed in + * lines. + */ +#define CAL_MIN_WIDTH_BYTES 16 +#define CAL_MAX_WIDTH_BYTES (8192 * 8) +#define CAL_MIN_HEIGHT_LINES 1 +#define CAL_MAX_HEIGHT_LINES 16383 + +#define CAL_CAMERARX_PAD_SINK 0 +#define CAL_CAMERARX_PAD_SOURCE 1 struct device; struct device_node; struct resource; struct regmap; struct regmap_fied; -struct v4l2_subdev; /* CTRL_CORE_CAMERRX_CONTROL register field id */ enum cal_camerarx_field { @@ -49,7 +61,14 @@ enum cal_camerarx_field { F_MAX_FIELDS, }; -struct cal_fmt { +enum cal_dma_state { + CAL_DMA_RUNNING, + CAL_DMA_STOP_REQUESTED, + CAL_DMA_STOP_PENDING, + CAL_DMA_STOPPED, +}; + +struct cal_format_info { u32 fourcc; u32 code; /* Bits per pixel */ @@ -63,8 +82,38 @@ struct cal_buffer { struct list_head list; }; +/** + * struct cal_dmaqueue - Queue of DMA buffers + * @active: Buffer being DMA'ed to for the current frame + */ struct cal_dmaqueue { - struct list_head active; + /** + * Protects all fields in the cal_dmaqueue. + */ + spinlock_t lock; + + /** + * Buffers queued to the driver and waiting for DMA processing. + * Buffers are added to the list by the vb2 .buffer_queue() operation, + * and move to @pending when they are scheduled for the next frame. + */ + struct list_head queue; + /** + * Buffer provided to the hardware to DMA the next frame. Will move to + * @active at the end of the current frame. + */ + struct cal_buffer *pending; + /** + * Buffer being DMA'ed to for the current frame. Will be retired and + * given back to vb2 at the end of the current frame if a @pending + * buffer has been scheduled to replace it. + */ + struct cal_buffer *active; + + /** State of the DMA engine. */ + enum cal_dma_state state; + /** Wait queue to signal a @state transition to CAL_DMA_STOPPED. */ + struct wait_queue_head wait; }; struct cal_camerarx_data { @@ -108,8 +157,14 @@ struct cal_camerarx { unsigned int instance; struct v4l2_fwnode_endpoint endpoint; + struct device_node *sensor_ep_node; struct device_node *sensor_node; struct v4l2_subdev *sensor; + + struct v4l2_subdev subdev; + struct media_pad pads[2]; + struct v4l2_mbus_framefmt formats[2]; + const struct cal_format_info *fmtinfo; }; struct cal_dev { @@ -149,33 +204,22 @@ struct cal_ctx { /* v4l2_ioctl mutex */ struct mutex mutex; - /* v4l2 buffers lock */ - spinlock_t slock; - struct cal_dmaqueue vidq; + struct cal_dmaqueue dma; /* video capture */ - const struct cal_fmt *fmt; + const struct cal_format_info *fmtinfo; /* Used to store current pixel format */ - struct v4l2_format v_fmt; - /* Used to store current mbus frame format */ - struct v4l2_mbus_framefmt m_fmt; + struct v4l2_format v_fmt; /* Current subdev enumerated format */ - const struct cal_fmt **active_fmt; + const struct cal_format_info **active_fmt; unsigned int num_active_fmt; unsigned int sequence; struct vb2_queue vb_vidq; unsigned int index; unsigned int cport; - - /* Pointer pointing to current v4l2_buffer */ - struct cal_buffer *cur_frm; - /* Pointer pointing to next v4l2_buffer */ - struct cal_buffer *next_frm; - - bool dma_act; }; extern unsigned int cal_debug; @@ -215,7 +259,7 @@ static inline void cal_write(struct cal_dev *cal, u32 offset, u32 val) iowrite32(val, cal->base + offset); } -static inline u32 cal_read_field(struct cal_dev *cal, u32 offset, u32 mask) +static __always_inline u32 cal_read_field(struct cal_dev *cal, u32 offset, u32 mask) { return FIELD_GET(mask, cal_read(cal, offset)); } @@ -239,25 +283,22 @@ static inline void cal_set_field(u32 *valp, u32 field, u32 mask) *valp = val; } +extern const struct cal_format_info cal_formats[]; +extern const unsigned int cal_num_formats; +const struct cal_format_info *cal_format_by_fourcc(u32 fourcc); +const struct cal_format_info *cal_format_by_code(u32 code); + void cal_quickdump_regs(struct cal_dev *cal); void cal_camerarx_disable(struct cal_camerarx *phy); -int cal_camerarx_start(struct cal_camerarx *phy, const struct cal_fmt *fmt); -void cal_camerarx_stop(struct cal_camerarx *phy); -void cal_camerarx_enable_irqs(struct cal_camerarx *phy); -void cal_camerarx_disable_irqs(struct cal_camerarx *phy); -void cal_camerarx_ppi_enable(struct cal_camerarx *phy); -void cal_camerarx_ppi_disable(struct cal_camerarx *phy); void cal_camerarx_i913_errata(struct cal_camerarx *phy); struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal, unsigned int instance); void cal_camerarx_destroy(struct cal_camerarx *phy); -void cal_ctx_csi2_config(struct cal_ctx *ctx); -void cal_ctx_pix_proc_config(struct cal_ctx *ctx); -void cal_ctx_wr_dma_config(struct cal_ctx *ctx, unsigned int width, - unsigned int height); -void cal_ctx_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr); +void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr); +void cal_ctx_start(struct cal_ctx *ctx); +void cal_ctx_stop(struct cal_ctx *ctx); int cal_ctx_v4l2_register(struct cal_ctx *ctx); void cal_ctx_v4l2_unregister(struct cal_ctx *ctx); diff --git a/drivers/media/platform/ti-vpe/vpe.c b/drivers/media/platform/ti-vpe/vpe.c index 779dd74b82d0..10251b787674 100644 --- a/drivers/media/platform/ti-vpe/vpe.c +++ b/drivers/media/platform/ti-vpe/vpe.c @@ -1683,7 +1683,6 @@ static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f, } } - memset(pix->reserved, 0, sizeof(pix->reserved)); for (i = 0; i < pix->num_planes; i++) { plane_fmt = &pix->plane_fmt[i]; depth = fmt->vpdma_fmt[i]->depth; @@ -1713,7 +1712,6 @@ static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f, plane_fmt->bytesperline * depth) >> 3; } - memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved)); } return 0; diff --git a/drivers/media/platform/video-mux.c b/drivers/media/platform/video-mux.c index 53570250a25d..133122e38515 100644 --- a/drivers/media/platform/video-mux.c +++ b/drivers/media/platform/video-mux.c @@ -370,19 +370,13 @@ static int video_mux_async_register(struct video_mux *vmux, if (!ep) continue; - asd = kzalloc(sizeof(*asd), GFP_KERNEL); - if (!asd) { - fwnode_handle_put(ep); - return -ENOMEM; - } - - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &vmux->notifier, ep, asd); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &vmux->notifier, ep, struct v4l2_async_subdev); fwnode_handle_put(ep); - if (ret) { - kfree(asd); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); /* OK if asd already exists */ if (ret != -EEXIST) return ret; diff --git a/drivers/media/platform/vsp1/vsp1.h b/drivers/media/platform/vsp1/vsp1.h index 56c62122a81a..37cf33c7e6ca 100644 --- a/drivers/media/platform/vsp1/vsp1.h +++ b/drivers/media/platform/vsp1/vsp1.h @@ -44,16 +44,16 @@ struct vsp1_uif; #define VSP1_MAX_UIF 2 #define VSP1_MAX_WPF 4 -#define VSP1_HAS_LUT (1 << 1) -#define VSP1_HAS_SRU (1 << 2) -#define VSP1_HAS_BRU (1 << 3) -#define VSP1_HAS_CLU (1 << 4) -#define VSP1_HAS_WPF_VFLIP (1 << 5) -#define VSP1_HAS_WPF_HFLIP (1 << 6) -#define VSP1_HAS_HGO (1 << 7) -#define VSP1_HAS_HGT (1 << 8) -#define VSP1_HAS_BRS (1 << 9) -#define VSP1_HAS_EXT_DL (1 << 10) +#define VSP1_HAS_LUT BIT(1) +#define VSP1_HAS_SRU BIT(2) +#define VSP1_HAS_BRU BIT(3) +#define VSP1_HAS_CLU BIT(4) +#define VSP1_HAS_WPF_VFLIP BIT(5) +#define VSP1_HAS_WPF_HFLIP BIT(6) +#define VSP1_HAS_HGO BIT(7) +#define VSP1_HAS_HGT BIT(8) +#define VSP1_HAS_BRS BIT(9) +#define VSP1_HAS_EXT_DL BIT(10) struct vsp1_device_info { u32 version; diff --git a/drivers/media/platform/vsp1/vsp1_drv.c b/drivers/media/platform/vsp1/vsp1_drv.c index dc62533cf32c..aa66e4f5f3f3 100644 --- a/drivers/media/platform/vsp1/vsp1_drv.c +++ b/drivers/media/platform/vsp1/vsp1_drv.c @@ -882,8 +882,10 @@ static int vsp1_probe(struct platform_device *pdev) } done: - if (ret) + if (ret) { pm_runtime_disable(&pdev->dev); + rcar_fcp_put(vsp1->fcp); + } return ret; } diff --git a/drivers/media/platform/xilinx/xilinx-vipp.c b/drivers/media/platform/xilinx/xilinx-vipp.c index cc2856efea59..bf4015d852e3 100644 --- a/drivers/media/platform/xilinx/xilinx-vipp.c +++ b/drivers/media/platform/xilinx/xilinx-vipp.c @@ -359,7 +359,7 @@ static int xvip_graph_parse_one(struct xvip_composite_device *xdev, dev_dbg(xdev->dev, "parsing node %p\n", fwnode); while (1) { - struct v4l2_async_subdev *asd; + struct xvip_graph_entity *xge; ep = fwnode_graph_get_next_endpoint(fwnode, ep); if (ep == NULL) @@ -382,12 +382,12 @@ static int xvip_graph_parse_one(struct xvip_composite_device *xdev, continue; } - asd = v4l2_async_notifier_add_fwnode_subdev( + xge = v4l2_async_notifier_add_fwnode_subdev( &xdev->notifier, remote, - sizeof(struct xvip_graph_entity)); + struct xvip_graph_entity); fwnode_handle_put(remote); - if (IS_ERR(asd)) { - ret = PTR_ERR(asd); + if (IS_ERR(xge)) { + ret = PTR_ERR(xge); goto err_notifier_cleanup; } } diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig index 2c0ee2e5b446..8a4b4040be45 100644 --- a/drivers/media/rc/Kconfig +++ b/drivers/media/rc/Kconfig @@ -92,6 +92,7 @@ config IR_SONY_DECODER config IR_SANYO_DECODER tristate "Enable IR raw decoder for the Sanyo protocol" depends on RC_CORE + select BITREVERSE help Enable this option if you have an infrared remote control which @@ -101,6 +102,7 @@ config IR_SANYO_DECODER config IR_SHARP_DECODER tristate "Enable IR raw decoder for the Sharp protocol" depends on RC_CORE + select BITREVERSE help Enable this option if you have an infrared remote control which diff --git a/drivers/media/rc/img-ir/Kconfig b/drivers/media/rc/img-ir/Kconfig index 5c0508f2719f..a80cfcd87a95 100644 --- a/drivers/media/rc/img-ir/Kconfig +++ b/drivers/media/rc/img-ir/Kconfig @@ -30,6 +30,7 @@ config IR_IMG_HW config IR_IMG_NEC bool "NEC protocol support" depends on IR_IMG_HW + select BITREVERSE help Say Y here to enable support for the NEC, extended NEC, and 32-bit NEC protocols in the ImgTec infrared decoder block. diff --git a/drivers/media/rc/ir_toy.c b/drivers/media/rc/ir_toy.c index e0242c9b6aeb..3e729a17b35f 100644 --- a/drivers/media/rc/ir_toy.c +++ b/drivers/media/rc/ir_toy.c @@ -491,6 +491,7 @@ static void irtoy_disconnect(struct usb_interface *intf) static const struct usb_device_id irtoy_table[] = { { USB_DEVICE_INTERFACE_CLASS(0x04d8, 0xfd08, USB_CLASS_CDC_DATA) }, + { USB_DEVICE_INTERFACE_CLASS(0x04d8, 0xf58b, USB_CLASS_CDC_DATA) }, { } }; diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c index f1dbd059ed08..5642595a057e 100644 --- a/drivers/media/rc/mceusb.c +++ b/drivers/media/rc/mceusb.c @@ -701,11 +701,18 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, u8 *buf, int buf_len, data[0], data[1]); break; case MCE_RSP_EQIRCFS: + if (!data[0] && !data[1]) { + dev_dbg(dev, "%s: no carrier", inout); + break; + } + // prescaler should make sense + if (data[0] > 8) + break; period = DIV_ROUND_CLOSEST((1U << data[0] * 2) * (data[1] + 1), 10); if (!period) break; - carrier = (1000 * 1000) / period; + carrier = USEC_PER_SEC / period; dev_dbg(dev, "%s carrier of %u Hz (period %uus)", inout, carrier, period); break; @@ -1169,7 +1176,7 @@ static void mceusb_handle_command(struct mceusb_dev *ir, u8 *buf_in) switch (subcmd) { /* the one and only 5-byte return value command */ case MCE_RSP_GETPORTSTATUS: - if (buf_in[5] == 0) + if (buf_in[5] == 0 && *hi < 8) ir->txports_cabled |= 1 << *hi; break; diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c index 8555c7798706..168e1d2c876a 100644 --- a/drivers/media/rc/sunxi-cir.c +++ b/drivers/media/rc/sunxi-cir.c @@ -86,7 +86,6 @@ struct sunxi_ir_quirks { }; struct sunxi_ir { - spinlock_t ir_lock; struct rc_dev *rc; void __iomem *base; int irq; @@ -105,8 +104,6 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) struct sunxi_ir *ir = dev_id; struct ir_raw_event rawir = {}; - spin_lock(&ir->ir_lock); - status = readl(ir->base + SUNXI_IR_RXSTA_REG); /* clean all pending statuses */ @@ -137,8 +134,6 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) ir_raw_event_handle(ir->rc); } - spin_unlock(&ir->ir_lock); - return IRQ_HANDLED; } @@ -160,27 +155,102 @@ static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout) { struct sunxi_ir *ir = rc_dev->priv; unsigned int base_clk = clk_get_rate(ir->clk); - unsigned long flags; unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout); dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr); - spin_lock_irqsave(&ir->ir_lock, flags); /* Set noise threshold and idle threshold */ writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr), ir->base + SUNXI_IR_CIR_REG); - spin_unlock_irqrestore(&ir->ir_lock, flags); rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr); return 0; } +static int sunxi_ir_hw_init(struct device *dev) +{ + struct sunxi_ir *ir = dev_get_drvdata(dev); + u32 tmp; + int ret; + + ret = reset_control_deassert(ir->rst); + if (ret) + return ret; + + ret = clk_prepare_enable(ir->apb_clk); + if (ret) { + dev_err(dev, "failed to enable apb clk\n"); + goto exit_assert_reset; + } + + ret = clk_prepare_enable(ir->clk); + if (ret) { + dev_err(dev, "failed to enable ir clk\n"); + goto exit_disable_apb_clk; + } + + /* Enable CIR Mode */ + writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG); + + /* Set noise threshold and idle threshold */ + sunxi_ir_set_timeout(ir->rc, ir->rc->timeout); + + /* Invert Input Signal */ + writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); + + /* Clear All Rx Interrupt Status */ + writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); + + /* + * Enable IRQ on overflow, packet end, FIFO available with trigger + * level + */ + writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | + REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), + ir->base + SUNXI_IR_RXINT_REG); + + /* Enable IR Module */ + tmp = readl(ir->base + SUNXI_IR_CTL_REG); + writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); + + return 0; + +exit_disable_apb_clk: + clk_disable_unprepare(ir->apb_clk); +exit_assert_reset: + reset_control_assert(ir->rst); + + return ret; +} + +static void sunxi_ir_hw_exit(struct device *dev) +{ + struct sunxi_ir *ir = dev_get_drvdata(dev); + + clk_disable_unprepare(ir->clk); + clk_disable_unprepare(ir->apb_clk); + reset_control_assert(ir->rst); +} + +static int __maybe_unused sunxi_ir_suspend(struct device *dev) +{ + sunxi_ir_hw_exit(dev); + + return 0; +} + +static int __maybe_unused sunxi_ir_resume(struct device *dev) +{ + return sunxi_ir_hw_init(dev); +} + +static SIMPLE_DEV_PM_OPS(sunxi_ir_pm_ops, sunxi_ir_suspend, sunxi_ir_resume); + static int sunxi_ir_probe(struct platform_device *pdev) { int ret = 0; - unsigned long tmp = 0; struct device *dev = &pdev->dev; struct device_node *dn = dev->of_node; @@ -199,8 +269,6 @@ static int sunxi_ir_probe(struct platform_device *pdev) return -ENODEV; } - spin_lock_init(&ir->ir_lock); - ir->fifo_size = quirks->fifo_size; /* Clock */ @@ -223,43 +291,26 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rst = devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(ir->rst)) return PTR_ERR(ir->rst); - ret = reset_control_deassert(ir->rst); - if (ret) - return ret; } ret = clk_set_rate(ir->clk, b_clk_freq); if (ret) { dev_err(dev, "set ir base clock failed!\n"); - goto exit_reset_assert; + return ret; } dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); - if (clk_prepare_enable(ir->apb_clk)) { - dev_err(dev, "try to enable apb_ir_clk failed\n"); - ret = -EINVAL; - goto exit_reset_assert; - } - - if (clk_prepare_enable(ir->clk)) { - dev_err(dev, "try to enable ir_clk failed\n"); - ret = -EINVAL; - goto exit_clkdisable_apb_clk; - } - /* IO */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ir->base = devm_ioremap_resource(dev, res); if (IS_ERR(ir->base)) { - ret = PTR_ERR(ir->base); - goto exit_clkdisable_clk; + return PTR_ERR(ir->base); } ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW); if (!ir->rc) { dev_err(dev, "failed to allocate device\n"); - ret = -ENOMEM; - goto exit_clkdisable_clk; + return -ENOMEM; } ir->rc->priv = ir; @@ -275,6 +326,7 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; /* Frequency after IR internal divider with sample period in us */ ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64)); + ir->rc->timeout = IR_DEFAULT_TIMEOUT; ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0); ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255); ir->rc->s_timeout = sunxi_ir_set_timeout; @@ -301,67 +353,34 @@ static int sunxi_ir_probe(struct platform_device *pdev) goto exit_free_dev; } - /* Enable CIR Mode */ - writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); - - /* Set noise threshold and idle threshold */ - sunxi_ir_set_timeout(ir->rc, IR_DEFAULT_TIMEOUT); - - /* Invert Input Signal */ - writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); - - /* Clear All Rx Interrupt Status */ - writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); - - /* - * Enable IRQ on overflow, packet end, FIFO available with trigger - * level - */ - writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | - REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1), - ir->base + SUNXI_IR_RXINT_REG); - - /* Enable IR Module */ - tmp = readl(ir->base + SUNXI_IR_CTL_REG); - writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); + ret = sunxi_ir_hw_init(dev); + if (ret) + goto exit_free_dev; dev_info(dev, "initialized sunXi IR driver\n"); return 0; exit_free_dev: rc_free_device(ir->rc); -exit_clkdisable_clk: - clk_disable_unprepare(ir->clk); -exit_clkdisable_apb_clk: - clk_disable_unprepare(ir->apb_clk); -exit_reset_assert: - reset_control_assert(ir->rst); return ret; } static int sunxi_ir_remove(struct platform_device *pdev) { - unsigned long flags; struct sunxi_ir *ir = platform_get_drvdata(pdev); - clk_disable_unprepare(ir->clk); - clk_disable_unprepare(ir->apb_clk); - reset_control_assert(ir->rst); - - spin_lock_irqsave(&ir->ir_lock, flags); - /* disable IR IRQ */ - writel(0, ir->base + SUNXI_IR_RXINT_REG); - /* clear All Rx Interrupt Status */ - writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); - /* disable IR */ - writel(0, ir->base + SUNXI_IR_CTL_REG); - spin_unlock_irqrestore(&ir->ir_lock, flags); - rc_unregister_device(ir->rc); + sunxi_ir_hw_exit(&pdev->dev); + return 0; } +static void sunxi_ir_shutdown(struct platform_device *pdev) +{ + sunxi_ir_hw_exit(&pdev->dev); +} + static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = { .has_reset = false, .fifo_size = 16, @@ -397,9 +416,11 @@ MODULE_DEVICE_TABLE(of, sunxi_ir_match); static struct platform_driver sunxi_ir_driver = { .probe = sunxi_ir_probe, .remove = sunxi_ir_remove, + .shutdown = sunxi_ir_shutdown, .driver = { .name = SUNXI_IR_DEV, .of_match_table = sunxi_ir_match, + .pm = &sunxi_ir_pm_ops, }, }; diff --git a/drivers/media/test-drivers/vicodec/vicodec-core.c b/drivers/media/test-drivers/vicodec/vicodec-core.c index 025f3ff77302..33f1c893c1b6 100644 --- a/drivers/media/test-drivers/vicodec/vicodec-core.c +++ b/drivers/media/test-drivers/vicodec/vicodec-core.c @@ -811,9 +811,6 @@ static int vidioc_g_fmt(struct vicodec_ctx *ctx, struct v4l2_format *f) pix_mp->xfer_func = ctx->state.xfer_func; pix_mp->ycbcr_enc = ctx->state.ycbcr_enc; pix_mp->quantization = ctx->state.quantization; - memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved)); - memset(pix_mp->plane_fmt[0].reserved, 0, - sizeof(pix_mp->plane_fmt[0].reserved)); break; default: return -EINVAL; @@ -886,8 +883,6 @@ static int vidioc_try_fmt(struct vicodec_ctx *ctx, struct v4l2_format *f) info->sizeimage_mult / info->sizeimage_div; if (pix_mp->pixelformat == V4L2_PIX_FMT_FWHT) plane->sizeimage += sizeof(struct fwht_cframe_hdr); - memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved)); - memset(plane->reserved, 0, sizeof(plane->reserved)); break; default: return -EINVAL; diff --git a/drivers/media/test-drivers/vidtv/vidtv_bridge.c b/drivers/media/test-drivers/vidtv/vidtv_bridge.c index fc64d0c8492a..75617709c8ce 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_bridge.c +++ b/drivers/media/test-drivers/vidtv/vidtv_bridge.c @@ -17,6 +17,8 @@ #include <linux/time.h> #include <linux/types.h> #include <linux/workqueue.h> +#include <media/dvbdev.h> +#include <media/media-device.h> #include "vidtv_bridge.h" #include "vidtv_common.h" @@ -414,6 +416,7 @@ static int vidtv_bridge_dvb_init(struct vidtv_dvb *dvb) ret = vidtv_bridge_register_adap(dvb); if (ret < 0) goto fail_adapter; + dvb_register_media_controller(&dvb->adapter, &dvb->mdev); for (i = 0; i < NUM_FE; ++i) { ret = vidtv_bridge_probe_demod(dvb, i); @@ -493,6 +496,15 @@ static int vidtv_bridge_probe(struct platform_device *pdev) dvb->pdev = pdev; +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + dvb->mdev.dev = &pdev->dev; + + strscpy(dvb->mdev.model, "vidtv", sizeof(dvb->mdev.model)); + strscpy(dvb->mdev.bus_info, "platform:vidtv", sizeof(dvb->mdev.bus_info)); + + media_device_init(&dvb->mdev); +#endif + ret = vidtv_bridge_dvb_init(dvb); if (ret < 0) goto err_dvb; @@ -501,9 +513,22 @@ static int vidtv_bridge_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dvb); +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + ret = media_device_register(&dvb->mdev); + if (ret) { + dev_err(dvb->mdev.dev, + "media device register failed (err=%d)\n", ret); + goto err_media_device_register; + } +#endif /* CONFIG_MEDIA_CONTROLLER_DVB */ + dev_info(&pdev->dev, "Successfully initialized vidtv!\n"); return ret; +#ifdef CONFIG_MEDIA_CONTROLLER_DVB +err_media_device_register: + media_device_cleanup(&dvb->mdev); +#endif /* CONFIG_MEDIA_CONTROLLER_DVB */ err_dvb: kfree(dvb); return ret; @@ -516,6 +541,11 @@ static int vidtv_bridge_remove(struct platform_device *pdev) dvb = platform_get_drvdata(pdev); +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + media_device_unregister(&dvb->mdev); + media_device_cleanup(&dvb->mdev); +#endif /* CONFIG_MEDIA_CONTROLLER_DVB */ + mutex_destroy(&dvb->feed_lock); for (i = 0; i < NUM_FE; ++i) { @@ -527,6 +557,7 @@ static int vidtv_bridge_remove(struct platform_device *pdev) dvb_dmxdev_release(&dvb->dmx_dev); dvb_dmx_release(&dvb->demux); dvb_unregister_adapter(&dvb->adapter); + dev_info(&pdev->dev, "Successfully removed vidtv\n"); return 0; } @@ -536,14 +567,13 @@ static void vidtv_bridge_dev_release(struct device *dev) } static struct platform_device vidtv_bridge_dev = { - .name = "vidtv_bridge", + .name = VIDTV_PDEV_NAME, .dev.release = vidtv_bridge_dev_release, }; static struct platform_driver vidtv_bridge_driver = { .driver = { - .name = "vidtv_bridge", - .suppress_bind_attrs = true, + .name = VIDTV_PDEV_NAME, }, .probe = vidtv_bridge_probe, .remove = vidtv_bridge_remove, diff --git a/drivers/media/test-drivers/vidtv/vidtv_bridge.h b/drivers/media/test-drivers/vidtv/vidtv_bridge.h index 2528adaee27d..de47ce6e7b14 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_bridge.h +++ b/drivers/media/test-drivers/vidtv/vidtv_bridge.h @@ -16,6 +16,7 @@ * For now, only one frontend is supported. See vidtv_start_streaming() */ #define NUM_FE 1 +#define VIDTV_PDEV_NAME "vidtv" #include <linux/i2c.h> #include <linux/platform_device.h> @@ -24,6 +25,7 @@ #include <media/dmxdev.h> #include <media/dvb_demux.h> #include <media/dvb_frontend.h> +#include <media/media-device.h> #include "vidtv_mux.h" @@ -42,6 +44,7 @@ * @feed_lock: Protects access to the start/stop stream logic/data. * @streaming: Whether we are streaming now. * @mux: The abstraction responsible for delivering MPEG TS packets to the bridge. + * @mdev: The media_device struct for media controller support. */ struct vidtv_dvb { struct platform_device *pdev; @@ -60,6 +63,10 @@ struct vidtv_dvb { bool streaming; struct vidtv_mux *mux; + +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + struct media_device mdev; +#endif /* CONFIG_MEDIA_CONTROLLER_DVB */ }; #endif // VIDTV_BRIDG_H diff --git a/drivers/media/test-drivers/vidtv/vidtv_psi.c b/drivers/media/test-drivers/vidtv/vidtv_psi.c index 4511a2a98405..47ed7907db8d 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_psi.c +++ b/drivers/media/test-drivers/vidtv/vidtv_psi.c @@ -506,10 +506,9 @@ struct vidtv_psi_desc *vidtv_psi_desc_clone(struct vidtv_psi_desc *desc) case REGISTRATION_DESCRIPTOR: default: - curr = kzalloc(sizeof(*desc) + desc->length, GFP_KERNEL); + curr = kmemdup(desc, sizeof(*desc) + desc->length, GFP_KERNEL); if (!curr) return NULL; - memcpy(curr, desc, sizeof(*desc) + desc->length); } if (!curr) @@ -1164,6 +1163,8 @@ u32 vidtv_psi_pmt_write_into(struct vidtv_psi_pmt_write_args *args) struct vidtv_psi_desc *table_descriptor = args->pmt->descriptor; struct vidtv_psi_table_pmt_stream *stream = args->pmt->stream; struct vidtv_psi_desc *stream_descriptor; + u32 crc = INITIAL_CRC; + u32 nbytes = 0; struct header_write_args h_args = { .dest_buf = args->buf, .dest_offset = args->offset, @@ -1181,6 +1182,7 @@ u32 vidtv_psi_pmt_write_into(struct vidtv_psi_pmt_write_args *args) .new_psi_section = false, .is_crc = false, .dest_buf_sz = args->buf_sz, + .crc = &crc, }; struct desc_write_args d_args = { .dest_buf = args->buf, @@ -1193,8 +1195,6 @@ u32 vidtv_psi_pmt_write_into(struct vidtv_psi_pmt_write_args *args) .pid = args->pid, .dest_buf_sz = args->buf_sz, }; - u32 crc = INITIAL_CRC; - u32 nbytes = 0; vidtv_psi_pmt_table_update_sec_len(args->pmt); diff --git a/drivers/media/test-drivers/vidtv/vidtv_ts.h b/drivers/media/test-drivers/vidtv/vidtv_ts.h index f5e8e1f37f05..09b4ffd02829 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_ts.h +++ b/drivers/media/test-drivers/vidtv/vidtv_ts.h @@ -44,7 +44,6 @@ struct vidtv_mpeg_ts { u8 adaptation_field:1; u8 scrambling:2; } __packed; - struct vidtv_mpeg_ts_adaption *adaption; } __packed; /** diff --git a/drivers/media/test-drivers/vivid/vivid-ctrls.c b/drivers/media/test-drivers/vivid/vivid-ctrls.c index 11e3b5617f52..7957eadf3e2b 100644 --- a/drivers/media/test-drivers/vivid/vivid-ctrls.c +++ b/drivers/media/test-drivers/vivid/vivid-ctrls.c @@ -100,6 +100,14 @@ /* General User Controls */ +static void vivid_unregister_dev(bool valid, struct video_device *vdev) +{ + if (!valid) + return; + clear_bit(V4L2_FL_REGISTERED, &vdev->flags); + v4l2_event_wake_all(vdev); +} + static int vivid_user_gen_s_ctrl(struct v4l2_ctrl *ctrl) { struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_user_gen); @@ -108,26 +116,16 @@ static int vivid_user_gen_s_ctrl(struct v4l2_ctrl *ctrl) case VIVID_CID_DISCONNECT: v4l2_info(&dev->v4l2_dev, "disconnect\n"); dev->disconnect_error = true; - if (dev->has_vid_cap) - clear_bit(V4L2_FL_REGISTERED, &dev->vid_cap_dev.flags); - if (dev->has_vid_out) - clear_bit(V4L2_FL_REGISTERED, &dev->vid_out_dev.flags); - if (dev->has_vbi_cap) - clear_bit(V4L2_FL_REGISTERED, &dev->vbi_cap_dev.flags); - if (dev->has_vbi_out) - clear_bit(V4L2_FL_REGISTERED, &dev->vbi_out_dev.flags); - if (dev->has_radio_rx) - clear_bit(V4L2_FL_REGISTERED, &dev->radio_rx_dev.flags); - if (dev->has_radio_tx) - clear_bit(V4L2_FL_REGISTERED, &dev->radio_tx_dev.flags); - if (dev->has_sdr_cap) - clear_bit(V4L2_FL_REGISTERED, &dev->sdr_cap_dev.flags); - if (dev->has_meta_cap) - clear_bit(V4L2_FL_REGISTERED, &dev->meta_cap_dev.flags); - if (dev->has_meta_out) - clear_bit(V4L2_FL_REGISTERED, &dev->meta_out_dev.flags); - if (dev->has_touch_cap) - clear_bit(V4L2_FL_REGISTERED, &dev->touch_cap_dev.flags); + vivid_unregister_dev(dev->has_vid_cap, &dev->vid_cap_dev); + vivid_unregister_dev(dev->has_vid_out, &dev->vid_out_dev); + vivid_unregister_dev(dev->has_vbi_cap, &dev->vbi_cap_dev); + vivid_unregister_dev(dev->has_vbi_out, &dev->vbi_out_dev); + vivid_unregister_dev(dev->has_radio_rx, &dev->radio_rx_dev); + vivid_unregister_dev(dev->has_radio_tx, &dev->radio_tx_dev); + vivid_unregister_dev(dev->has_sdr_cap, &dev->sdr_cap_dev); + vivid_unregister_dev(dev->has_meta_cap, &dev->meta_cap_dev); + vivid_unregister_dev(dev->has_meta_out, &dev->meta_out_dev); + vivid_unregister_dev(dev->has_touch_cap, &dev->touch_cap_dev); break; case VIVID_CID_BUTTON: dev->button_pressed = 30; diff --git a/drivers/media/tuners/it913x.c b/drivers/media/tuners/it913x.c index e8e66390be41..7696a28fe407 100644 --- a/drivers/media/tuners/it913x.c +++ b/drivers/media/tuners/it913x.c @@ -62,6 +62,7 @@ static int it913x_init(struct dvb_frontend *fe) break; default: dev_err(&pdev->dev, "unknown clock identifier %d\n", utmp); + ret = -EINVAL; goto err; } diff --git a/drivers/media/tuners/qm1d1c0042.c b/drivers/media/tuners/qm1d1c0042.c index 0e26d22f0b26..53aa2558f71e 100644 --- a/drivers/media/tuners/qm1d1c0042.c +++ b/drivers/media/tuners/qm1d1c0042.c @@ -343,8 +343,10 @@ static int qm1d1c0042_init(struct dvb_frontend *fe) if (val == reg_initval[reg_index][0x00]) break; } - if (reg_index >= QM1D1C0042_NUM_REG_ROWS) + if (reg_index >= QM1D1C0042_NUM_REG_ROWS) { + ret = -EINVAL; goto failed; + } memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS); usleep_range(2000, 3000); diff --git a/drivers/media/usb/cx231xx/Kconfig b/drivers/media/usb/cx231xx/Kconfig index 2fe2b2d335ba..b80661b8375f 100644 --- a/drivers/media/usb/cx231xx/Kconfig +++ b/drivers/media/usb/cx231xx/Kconfig @@ -18,6 +18,7 @@ config VIDEO_CX231XX_RC bool "Conexant cx231xx Remote Controller additional support" depends on RC_CORE=y || RC_CORE=VIDEO_CX231XX depends on VIDEO_CX231XX + select BITREVERSE default y help cx231xx hardware has a builtin RX/TX support. However, a few diff --git a/drivers/media/usb/dvb-usb-v2/af9015.c b/drivers/media/usb/dvb-usb-v2/af9015.c index c70b3cef3176..d33514acc2b5 100644 --- a/drivers/media/usb/dvb-usb-v2/af9015.c +++ b/drivers/media/usb/dvb-usb-v2/af9015.c @@ -51,6 +51,7 @@ static int af9015_ctrl_msg(struct dvb_usb_device *d, struct req_t *req) if (((req->addr & 0xff00) == 0xff00) || ((req->addr & 0xff00) == 0xae00)) state->buf[0] = WRITE_VIRTUAL_MEMORY; + break; case WRITE_VIRTUAL_MEMORY: case COPY_FIRMWARE: case DOWNLOAD_FIRMWARE: diff --git a/drivers/media/usb/dvb-usb-v2/lmedm04.c b/drivers/media/usb/dvb-usb-v2/lmedm04.c index 5a7a9522d46d..1b6d4e4c52ca 100644 --- a/drivers/media/usb/dvb-usb-v2/lmedm04.c +++ b/drivers/media/usb/dvb-usb-v2/lmedm04.c @@ -336,6 +336,7 @@ static void lme2510_int_response(struct urb *lme_urb) st->signal_level = ibuf[5]; st->signal_sn = ibuf[4]; st->time_key = ibuf[7]; + break; default: break; } @@ -373,7 +374,7 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) struct lme2510_state *lme_int = adap_to_priv(adap); struct usb_host_endpoint *ep; - lme_int->lme_urb = usb_alloc_urb(0, GFP_ATOMIC); + lme_int->lme_urb = usb_alloc_urb(0, GFP_KERNEL); if (lme_int->lme_urb == NULL) return -ENOMEM; @@ -391,9 +392,9 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) ep = usb_pipe_endpoint(d->udev, lme_int->lme_urb->pipe); if (usb_endpoint_type(&ep->desc) == USB_ENDPOINT_XFER_BULK) - lme_int->lme_urb->pipe = usb_rcvbulkpipe(d->udev, 0xa), + lme_int->lme_urb->pipe = usb_rcvbulkpipe(d->udev, 0xa); - usb_submit_urb(lme_int->lme_urb, GFP_ATOMIC); + usb_submit_urb(lme_int->lme_urb, GFP_KERNEL); info("INT Interrupt Service Started"); return 0; @@ -751,20 +752,6 @@ static const char *lme_firmware_switch(struct dvb_usb_device *d, int cold) return fw_lme; } -static int lme2510_kill_urb(struct usb_data_stream *stream) -{ - int i; - - for (i = 0; i < stream->urbs_submitted; i++) { - deb_info(3, "killing URB no. %d.", i); - /* stop the URB */ - usb_kill_urb(stream->urb_list[i]); - } - stream->urbs_submitted = 0; - - return 0; -} - static struct tda10086_config tda10086_config = { .demod_address = 0x0e, .invert = 0, @@ -1198,11 +1185,6 @@ static int lme2510_get_rc_config(struct dvb_usb_device *d, static void lme2510_exit(struct dvb_usb_device *d) { struct lme2510_state *st = d->priv; - struct dvb_usb_adapter *adap = &d->adapter[0]; - - if (adap != NULL) { - lme2510_kill_urb(&adap->stream); - } if (st->lme_urb) { usb_kill_urb(st->lme_urb); diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 3952cc534b4a..97ed17a141bb 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -944,12 +944,6 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) if (dev->slave_demod) { struct i2c_board_info info = {}; - /* - * We continue on reduced mode, without DVB-T2/C, using master - * demod, when slave demod fails. - */ - ret = 0; - /* attach slave demodulator */ if (dev->slave_demod == SLAVE_DEMOD_MN88472) { struct mn88472_config mn88472_config = {}; @@ -964,14 +958,11 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) info.platform_data = &mn88472_config; request_module(info.type); client = i2c_new_client_device(&d->i2c_adap, &info); - if (!i2c_client_has_driver(client)) { - dev->slave_demod = SLAVE_DEMOD_NONE; + if (!i2c_client_has_driver(client)) goto err_slave_demod_failed; - } if (!try_module_get(client->dev.driver->owner)) { i2c_unregister_device(client); - dev->slave_demod = SLAVE_DEMOD_NONE; goto err_slave_demod_failed; } @@ -986,14 +977,11 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) info.platform_data = &mn88473_config; request_module(info.type); client = i2c_new_client_device(&d->i2c_adap, &info); - if (!i2c_client_has_driver(client)) { - dev->slave_demod = SLAVE_DEMOD_NONE; + if (!i2c_client_has_driver(client)) goto err_slave_demod_failed; - } if (!try_module_get(client->dev.driver->owner)) { i2c_unregister_device(client); - dev->slave_demod = SLAVE_DEMOD_NONE; goto err_slave_demod_failed; } @@ -1009,10 +997,8 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) adap->fe[1] = dvb_attach(cxd2841er_attach_t_c, &cxd2837er_config, &d->i2c_adap); - if (!adap->fe[1]) { - dev->slave_demod = SLAVE_DEMOD_NONE; + if (!adap->fe[1]) goto err_slave_demod_failed; - } adap->fe[1]->id = 1; dev->i2c_client_slave_demod = NULL; } else { @@ -1029,14 +1015,11 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) info.platform_data = &si2168_config; request_module(info.type); client = i2c_new_client_device(&d->i2c_adap, &info); - if (!i2c_client_has_driver(client)) { - dev->slave_demod = SLAVE_DEMOD_NONE; + if (!i2c_client_has_driver(client)) goto err_slave_demod_failed; - } if (!try_module_get(client->dev.driver->owner)) { i2c_unregister_device(client); - dev->slave_demod = SLAVE_DEMOD_NONE; goto err_slave_demod_failed; } @@ -1047,10 +1030,18 @@ static int rtl2832u_frontend_attach(struct dvb_usb_adapter *adap) } } return 0; -err_slave_demod_failed: + err: dev_dbg(&d->intf->dev, "failed=%d\n", ret); return ret; + +err_slave_demod_failed: + /* + * We continue on reduced mode, without DVB-T2/C, using master + * demod, when slave demod fails. + */ + dev->slave_demod = SLAVE_DEMOD_NONE; + return 0; } static int rtl28xxu_frontend_attach(struct dvb_usb_adapter *adap) diff --git a/drivers/media/usb/em28xx/Kconfig b/drivers/media/usb/em28xx/Kconfig index f2031a933e54..b3c472b8c5a9 100644 --- a/drivers/media/usb/em28xx/Kconfig +++ b/drivers/media/usb/em28xx/Kconfig @@ -67,6 +67,7 @@ config VIDEO_EM28XX_DVB select MEDIA_TUNER_XC2028 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_XC5000 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_MT2060 if MEDIA_SUBDRV_AUTOSELECT + select DVB_MXL692 if MEDIA_SUBDRV_AUTOSELECT help This adds support for DVB cards based on the Empiatech em28xx chips. @@ -77,5 +78,6 @@ config VIDEO_EM28XX_RC depends on VIDEO_EM28XX depends on !(RC_CORE=m && VIDEO_EM28XX=y) default VIDEO_EM28XX + select BITREVERSE help Enables Remote Controller support on em28xx driver. diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index 5144888ae36f..d6c8ae213914 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -549,6 +549,21 @@ static const struct em28xx_reg_seq hauppauge_dualhd_dvb[] = { {-1, -1, -1, -1}, }; +/* Hauppauge USB QuadHD */ +static struct em28xx_reg_seq hauppauge_usb_quadhd_atsc_reg_seq[] = { + {EM2874_R80_GPIO_P0_CTRL, 0xff, 0xff, 0}, + {0x0d, 0xff, 0xff, 200}, + {0x50, 0x04, 0xff, 300}, + {EM2874_R80_GPIO_P0_CTRL, 0xb0, 0xf0, 100}, /* demod 1 reset */ + {EM2874_R80_GPIO_P0_CTRL, 0xf0, 0xf0, 100}, + {EM2874_R80_GPIO_P0_CTRL, 0xd0, 0xf0, 100}, /* demod 2 reset */ + {EM2874_R80_GPIO_P0_CTRL, 0xf0, 0xf0, 100}, + {EM2874_R5F_TS_ENABLE, 0x44, 0xff, 50}, + {EM2874_R5D_TS1_PKT_SIZE, 0x05, 0xff, 50}, + {EM2874_R5E_TS2_PKT_SIZE, 0x05, 0xff, 50}, + {-1, -1, -1, -1}, +}; + /* * Button definitions */ @@ -644,6 +659,22 @@ static struct em28xx_led hauppauge_dualhd_leds[] = { {-1, 0, 0, 0}, }; +static struct em28xx_led hauppauge_usb_quadhd_leds[] = { + { + .role = EM28XX_LED_DIGITAL_CAPTURING, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = EM_GPIO_2, + .inverted = 1, + }, + { + .role = EM28XX_LED_DIGITAL_CAPTURING_TS2, + .gpio_reg = EM2874_R80_GPIO_P0_CTRL, + .gpio_mask = EM_GPIO_0, + .inverted = 1, + }, + {-1, 0, 0, 0}, +}; + /* * Board definitions */ @@ -2539,6 +2570,19 @@ const struct em28xx_board em28xx_boards[] = { .amux = EM28XX_AMUX_LINE_IN, } }, }, + /* 2040:826d Hauppauge USB QuadHD + * Empia 28274, Max Linear 692 ATSC combo demod/tuner + */ + [EM2874_BOARD_HAUPPAUGE_USB_QUADHD] = { + .name = "Hauppauge USB QuadHD ATSC", + .def_i2c_bus = 1, + .has_dual_ts = 1, + .has_dvb = 1, + .i2c_speed = EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ, + .tuner_type = TUNER_ABSENT, + .tuner_gpio = hauppauge_usb_quadhd_atsc_reg_seq, + .leds = hauppauge_usb_quadhd_leds, + }, }; EXPORT_SYMBOL_GPL(em28xx_boards); @@ -2672,6 +2716,8 @@ struct usb_device_id em28xx_id_table[] = { .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595 }, { USB_DEVICE(0x2040, 0x826d), .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595 }, + { USB_DEVICE(0x2040, 0x846d), + .driver_info = EM2874_BOARD_HAUPPAUGE_USB_QUADHD }, { USB_DEVICE(0x0438, 0xb002), .driver_info = EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 }, { USB_DEVICE(0x2001, 0xf112), diff --git a/drivers/media/usb/em28xx/em28xx-core.c b/drivers/media/usb/em28xx/em28xx-core.c index e6088b5d1b80..584fa400cd7d 100644 --- a/drivers/media/usb/em28xx/em28xx-core.c +++ b/drivers/media/usb/em28xx/em28xx-core.c @@ -698,8 +698,10 @@ int em28xx_capture_start(struct em28xx *dev, int start) if (dev->mode == EM28XX_ANALOG_MODE) led = em28xx_find_led(dev, EM28XX_LED_ANALOG_CAPTURING); - else + else if (dev->ts == PRIMARY_TS) led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING); + else + led = em28xx_find_led(dev, EM28XX_LED_DIGITAL_CAPTURING_TS2); if (led) em28xx_write_reg_bits(dev, led->gpio_reg, @@ -956,14 +958,10 @@ int em28xx_alloc_urbs(struct em28xx *dev, enum em28xx_mode mode, int xfer_bulk, usb_bufs->buf[i] = kzalloc(sb_size, GFP_KERNEL); if (!usb_bufs->buf[i]) { - em28xx_uninit_usb_xfer(dev, mode); - for (i--; i >= 0; i--) kfree(usb_bufs->buf[i]); - kfree(usb_bufs->buf); - usb_bufs->buf = NULL; - + em28xx_uninit_usb_xfer(dev, mode); return -ENOMEM; } diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c index fb9cbfa81a84..526424279637 100644 --- a/drivers/media/usb/em28xx/em28xx-dvb.c +++ b/drivers/media/usb/em28xx/em28xx-dvb.c @@ -62,6 +62,7 @@ #include "si2157.h" #include "tc90522.h" #include "qm1d1c0042.h" +#include "mxl692.h" MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@kernel.org>"); MODULE_LICENSE("GPL v2"); @@ -1459,6 +1460,26 @@ static int em28174_dvb_init_hauppauge_wintv_dualhd_01595(struct em28xx *dev) return 0; } +static int em2874_dvb_init_hauppauge_usb_quadhd(struct em28xx *dev) +{ + struct em28xx_dvb *dvb = dev->dvb; + struct mxl692_config mxl692_config = {}; + unsigned char addr; + + /* attach demod/tuner combo */ + mxl692_config.id = (dev->ts == PRIMARY_TS) ? 0 : 1; + mxl692_config.fe = &dvb->fe[0]; + addr = (dev->ts == PRIMARY_TS) ? 0x60 : 0x63; + + dvb->i2c_client_demod = dvb_module_probe("mxl692", NULL, + &dev->i2c_adap[dev->def_i2c_bus], + addr, &mxl692_config); + if (!dvb->i2c_client_demod) + return -ENODEV; + + return 0; +} + static int em28xx_dvb_init(struct em28xx *dev) { int result = 0, dvb_alt = 0; @@ -1945,6 +1966,11 @@ static int em28xx_dvb_init(struct em28xx *dev) if (result) goto out_free; break; + case EM2874_BOARD_HAUPPAUGE_USB_QUADHD: + result = em2874_dvb_init_hauppauge_usb_quadhd(dev); + if (result) + goto out_free; + break; default: dev_err(&dev->intf->dev, "The frontend of your DVB/ATSC card isn't supported yet\n"); diff --git a/drivers/media/usb/em28xx/em28xx-i2c.c b/drivers/media/usb/em28xx/em28xx-i2c.c index 592b98b3643a..255395959255 100644 --- a/drivers/media/usb/em28xx/em28xx-i2c.c +++ b/drivers/media/usb/em28xx/em28xx-i2c.c @@ -294,6 +294,10 @@ static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len) "reading from i2c device at 0x%x failed (error=%i)\n", addr, ret); return ret; + } else if (ret != len) { + dev_dbg(&dev->intf->dev, + "%i bytes read from i2c device at 0x%x requested, but %i bytes written\n", + ret, addr, len); } /* * NOTE: some devices with two i2c buses have the bad habit to return 0 @@ -329,7 +333,7 @@ static int em28xx_i2c_recv_bytes(struct em28xx *dev, u16 addr, u8 *buf, u16 len) } dev_warn(&dev->intf->dev, - "write to i2c device at 0x%x failed with unknown error (status=%i)\n", + "read from i2c device at 0x%x failed with unknown error (status=%i)\n", addr, ret); return -EIO; } diff --git a/drivers/media/usb/em28xx/em28xx.h b/drivers/media/usb/em28xx/em28xx.h index 55a46faaf7b7..6648e11f1271 100644 --- a/drivers/media/usb/em28xx/em28xx.h +++ b/drivers/media/usb/em28xx/em28xx.h @@ -152,6 +152,7 @@ #define EM2861_BOARD_MAGIX_VIDEOWANDLER2 103 #define EM28178_BOARD_PCTV_461E_V2 104 #define EM2860_BOARD_MYGICA_IGRABBER 105 +#define EM2874_BOARD_HAUPPAUGE_USB_QUADHD 106 /* Limits minimum and default number of buffers */ #define EM28XX_MIN_BUF 4 diff --git a/drivers/media/usb/pwc/pwc-if.c b/drivers/media/usb/pwc/pwc-if.c index 61869636ec61..5e3339cc31c0 100644 --- a/drivers/media/usb/pwc/pwc-if.c +++ b/drivers/media/usb/pwc/pwc-if.c @@ -155,16 +155,17 @@ static const struct video_device pwc_template = { /***************************************************************************/ /* Private functions */ -static void *pwc_alloc_urb_buffer(struct device *dev, +static void *pwc_alloc_urb_buffer(struct usb_device *dev, size_t size, dma_addr_t *dma_handle) { + struct device *dmadev = dev->bus->sysdev; void *buffer = kmalloc(size, GFP_KERNEL); if (!buffer) return NULL; - *dma_handle = dma_map_single(dev, buffer, size, DMA_FROM_DEVICE); - if (dma_mapping_error(dev, *dma_handle)) { + *dma_handle = dma_map_single(dmadev, buffer, size, DMA_FROM_DEVICE); + if (dma_mapping_error(dmadev, *dma_handle)) { kfree(buffer); return NULL; } @@ -172,12 +173,14 @@ static void *pwc_alloc_urb_buffer(struct device *dev, return buffer; } -static void pwc_free_urb_buffer(struct device *dev, +static void pwc_free_urb_buffer(struct usb_device *dev, size_t size, void *buffer, dma_addr_t dma_handle) { - dma_unmap_single(dev, dma_handle, size, DMA_FROM_DEVICE); + struct device *dmadev = dev->bus->sysdev; + + dma_unmap_single(dmadev, dma_handle, size, DMA_FROM_DEVICE); kfree(buffer); } @@ -282,6 +285,7 @@ static void pwc_frame_complete(struct pwc_device *pdev) static void pwc_isoc_handler(struct urb *urb) { struct pwc_device *pdev = (struct pwc_device *)urb->context; + struct device *dmadev = urb->dev->bus->sysdev; int i, fst, flen; unsigned char *iso_buf = NULL; @@ -328,7 +332,7 @@ static void pwc_isoc_handler(struct urb *urb) /* Reset ISOC error counter. We did get here, after all. */ pdev->visoc_errors = 0; - dma_sync_single_for_cpu(&urb->dev->dev, + dma_sync_single_for_cpu(dmadev, urb->transfer_dma, urb->transfer_buffer_length, DMA_FROM_DEVICE); @@ -379,7 +383,7 @@ static void pwc_isoc_handler(struct urb *urb) pdev->vlast_packet_size = flen; } - dma_sync_single_for_device(&urb->dev->dev, + dma_sync_single_for_device(dmadev, urb->transfer_dma, urb->transfer_buffer_length, DMA_FROM_DEVICE); @@ -461,7 +465,7 @@ retry: urb->pipe = usb_rcvisocpipe(udev, pdev->vendpoint); urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; urb->transfer_buffer_length = ISO_BUFFER_SIZE; - urb->transfer_buffer = pwc_alloc_urb_buffer(&udev->dev, + urb->transfer_buffer = pwc_alloc_urb_buffer(udev, urb->transfer_buffer_length, &urb->transfer_dma); if (urb->transfer_buffer == NULL) { @@ -524,7 +528,7 @@ static void pwc_iso_free(struct pwc_device *pdev) if (urb) { PWC_DEBUG_MEMORY("Freeing URB\n"); if (urb->transfer_buffer) - pwc_free_urb_buffer(&urb->dev->dev, + pwc_free_urb_buffer(urb->dev, urb->transfer_buffer_length, urb->transfer_buffer, urb->transfer_dma); diff --git a/drivers/media/usb/tm6000/tm6000-dvb.c b/drivers/media/usb/tm6000/tm6000-dvb.c index 19c90fa9e443..293a460f4616 100644 --- a/drivers/media/usb/tm6000/tm6000-dvb.c +++ b/drivers/media/usb/tm6000/tm6000-dvb.c @@ -141,6 +141,10 @@ static int tm6000_start_stream(struct tm6000_core *dev) if (ret < 0) { printk(KERN_ERR "tm6000: error %i in %s during pipe reset\n", ret, __func__); + + kfree(dvb->bulk_urb->transfer_buffer); + usb_free_urb(dvb->bulk_urb); + dvb->bulk_urb = NULL; return ret; } else printk(KERN_ERR "tm6000: pipe reset\n"); diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c index 011e69427b7c..b3dde98499f4 100644 --- a/drivers/media/usb/uvc/uvc_ctrl.c +++ b/drivers/media/usb/uvc/uvc_ctrl.c @@ -347,6 +347,14 @@ static const struct uvc_control_info uvc_ctrls[] = { | UVC_CTRL_FLAG_RESTORE | UVC_CTRL_FLAG_AUTO_UPDATE, }, + { + .entity = UVC_GUID_EXT_GPIO_CONTROLLER, + .selector = UVC_CT_PRIVACY_CONTROL, + .index = 0, + .size = 1, + .flags = UVC_CTRL_FLAG_GET_CUR + | UVC_CTRL_FLAG_AUTO_UPDATE, + }, }; static const struct uvc_menu_info power_line_frequency_controls[] = { @@ -735,6 +743,16 @@ static const struct uvc_control_mapping uvc_ctrl_mappings[] = { .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, }, + { + .id = V4L2_CID_PRIVACY, + .name = "Privacy", + .entity = UVC_GUID_EXT_GPIO_CONTROLLER, + .selector = UVC_CT_PRIVACY_CONTROL, + .size = 1, + .offset = 0, + .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, + .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, + }, }; /* ------------------------------------------------------------------------ @@ -826,31 +844,10 @@ static void uvc_set_le_value(struct uvc_control_mapping *mapping, * Terminal and unit management */ -static const u8 uvc_processing_guid[16] = UVC_GUID_UVC_PROCESSING; -static const u8 uvc_camera_guid[16] = UVC_GUID_UVC_CAMERA; -static const u8 uvc_media_transport_input_guid[16] = - UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT; - static int uvc_entity_match_guid(const struct uvc_entity *entity, - const u8 guid[16]) + const u8 guid[16]) { - switch (UVC_ENTITY_TYPE(entity)) { - case UVC_ITT_CAMERA: - return memcmp(uvc_camera_guid, guid, 16) == 0; - - case UVC_ITT_MEDIA_TRANSPORT_INPUT: - return memcmp(uvc_media_transport_input_guid, guid, 16) == 0; - - case UVC_VC_PROCESSING_UNIT: - return memcmp(uvc_processing_guid, guid, 16) == 0; - - case UVC_VC_EXTENSION_UNIT: - return memcmp(entity->extension.guidExtensionCode, - guid, 16) == 0; - - default: - return 0; - } + return memcmp(entity->guid, guid, sizeof(entity->guid)) == 0; } /* ------------------------------------------------------------------------ @@ -909,8 +906,8 @@ static struct uvc_control *uvc_find_control(struct uvc_video_chain *chain, } if (ctrl == NULL && !next) - uvc_trace(UVC_TRACE_CONTROL, "Control 0x%08x not found.\n", - v4l2_id); + uvc_dbg(chain->dev, CONTROL, "Control 0x%08x not found\n", + v4l2_id); return ctrl; } @@ -1001,10 +998,20 @@ static int __uvc_ctrl_get(struct uvc_video_chain *chain, return -EACCES; if (!ctrl->loaded) { - ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR, ctrl->entity->id, - chain->dev->intfnum, ctrl->info.selector, + if (ctrl->entity->get_cur) { + ret = ctrl->entity->get_cur(chain->dev, + ctrl->entity, + ctrl->info.selector, + uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), + ctrl->info.size); + } else { + ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR, + ctrl->entity->id, + chain->dev->intfnum, + ctrl->info.selector, uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), ctrl->info.size); + } if (ret < 0) return ret; @@ -1275,17 +1282,12 @@ static void uvc_ctrl_send_slave_event(struct uvc_video_chain *chain, uvc_ctrl_send_event(chain, handle, ctrl, mapping, val, changes); } -static void uvc_ctrl_status_event_work(struct work_struct *work) +void uvc_ctrl_status_event(struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { - struct uvc_device *dev = container_of(work, struct uvc_device, - async_ctrl.work); - struct uvc_ctrl_work *w = &dev->async_ctrl; - struct uvc_video_chain *chain = w->chain; struct uvc_control_mapping *mapping; - struct uvc_control *ctrl = w->ctrl; struct uvc_fh *handle; unsigned int i; - int ret; mutex_lock(&chain->ctrl_mutex); @@ -1293,7 +1295,7 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) ctrl->handle = NULL; list_for_each_entry(mapping, &ctrl->info.mappings, list) { - s32 value = __uvc_ctrl_get_value(mapping, w->data); + s32 value = __uvc_ctrl_get_value(mapping, data); /* * handle may be NULL here if the device sends auto-update @@ -1312,17 +1314,27 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) } mutex_unlock(&chain->ctrl_mutex); +} + +static void uvc_ctrl_status_event_work(struct work_struct *work) +{ + struct uvc_device *dev = container_of(work, struct uvc_device, + async_ctrl.work); + struct uvc_ctrl_work *w = &dev->async_ctrl; + int ret; + + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); /* Resubmit the URB. */ w->urb->interval = dev->int_ep->desc.bInterval; ret = usb_submit_urb(w->urb, GFP_KERNEL); if (ret < 0) - uvc_printk(KERN_ERR, "Failed to resubmit status URB (%d).\n", - ret); + dev_err(&dev->udev->dev, + "Failed to resubmit status URB (%d).\n", ret); } -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, - struct uvc_control *ctrl, const u8 *data) +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { struct uvc_device *dev = chain->dev; struct uvc_ctrl_work *w = &dev->async_ctrl; @@ -1708,8 +1720,12 @@ static int uvc_ctrl_get_flags(struct uvc_device *dev, if (data == NULL) return -ENOMEM; - ret = uvc_query_ctrl(dev, UVC_GET_INFO, ctrl->entity->id, dev->intfnum, - info->selector, data, 1); + if (ctrl->entity->get_info) + ret = ctrl->entity->get_info(dev, ctrl->entity, + ctrl->info.selector, data); + else + ret = uvc_query_ctrl(dev, UVC_GET_INFO, ctrl->entity->id, + dev->intfnum, info->selector, data, 1); if (!ret) info->flags |= (data[0] & UVC_CONTROL_CAP_GET ? UVC_CTRL_FLAG_GET_CUR : 0) @@ -1776,8 +1792,7 @@ static int uvc_ctrl_fill_xu_info(struct uvc_device *dev, if (data == NULL) return -ENOMEM; - memcpy(info->entity, ctrl->entity->extension.guidExtensionCode, - sizeof(info->entity)); + memcpy(info->entity, ctrl->entity->guid, sizeof(info->entity)); info->index = ctrl->index; info->selector = ctrl->index + 1; @@ -1785,9 +1800,9 @@ static int uvc_ctrl_fill_xu_info(struct uvc_device *dev, ret = uvc_query_ctrl(dev, UVC_GET_LEN, ctrl->entity->id, dev->intfnum, info->selector, data, 2); if (ret < 0) { - uvc_trace(UVC_TRACE_CONTROL, - "GET_LEN failed on control %pUl/%u (%d).\n", - info->entity, info->selector, ret); + uvc_dbg(dev, CONTROL, + "GET_LEN failed on control %pUl/%u (%d)\n", + info->entity, info->selector, ret); goto done; } @@ -1798,20 +1813,20 @@ static int uvc_ctrl_fill_xu_info(struct uvc_device *dev, ret = uvc_ctrl_get_flags(dev, ctrl, info); if (ret < 0) { - uvc_trace(UVC_TRACE_CONTROL, - "Failed to get flags for control %pUl/%u (%d).\n", - info->entity, info->selector, ret); + uvc_dbg(dev, CONTROL, + "Failed to get flags for control %pUl/%u (%d)\n", + info->entity, info->selector, ret); goto done; } uvc_ctrl_fixup_xu_info(dev, ctrl, info); - uvc_trace(UVC_TRACE_CONTROL, "XU control %pUl/%u queried: len %u, " - "flags { get %u set %u auto %u }.\n", - info->entity, info->selector, info->size, - (info->flags & UVC_CTRL_FLAG_GET_CUR) ? 1 : 0, - (info->flags & UVC_CTRL_FLAG_SET_CUR) ? 1 : 0, - (info->flags & UVC_CTRL_FLAG_AUTO_UPDATE) ? 1 : 0); + uvc_dbg(dev, CONTROL, + "XU control %pUl/%u queried: len %u, flags { get %u set %u auto %u }\n", + info->entity, info->selector, info->size, + (info->flags & UVC_CTRL_FLAG_GET_CUR) ? 1 : 0, + (info->flags & UVC_CTRL_FLAG_SET_CUR) ? 1 : 0, + (info->flags & UVC_CTRL_FLAG_AUTO_UPDATE) ? 1 : 0); done: kfree(data); @@ -1836,9 +1851,10 @@ static int uvc_ctrl_init_xu_ctrl(struct uvc_device *dev, ret = uvc_ctrl_add_info(dev, ctrl, &info); if (ret < 0) - uvc_trace(UVC_TRACE_CONTROL, "Failed to initialize control " - "%pUl/%u on device %s entity %u\n", info.entity, - info.selector, dev->udev->devpath, ctrl->entity->id); + uvc_dbg(dev, CONTROL, + "Failed to initialize control %pUl/%u on device %s entity %u\n", + info.entity, info.selector, dev->udev->devpath, + ctrl->entity->id); return ret; } @@ -1866,7 +1882,7 @@ int uvc_xu_ctrl_query(struct uvc_video_chain *chain, } if (!found) { - uvc_trace(UVC_TRACE_CONTROL, "Extension unit %u not found.\n", + uvc_dbg(chain->dev, CONTROL, "Extension unit %u not found\n", xqry->unit); return -ENOENT; } @@ -1882,8 +1898,8 @@ int uvc_xu_ctrl_query(struct uvc_video_chain *chain, } if (!found) { - uvc_trace(UVC_TRACE_CONTROL, "Control %pUl/%u not found.\n", - entity->extension.guidExtensionCode, xqry->selector); + uvc_dbg(chain->dev, CONTROL, "Control %pUl/%u not found\n", + entity->guid, xqry->selector); return -ENOENT; } @@ -1995,10 +2011,10 @@ int uvc_ctrl_restore_values(struct uvc_device *dev) if (!ctrl->initialized || !ctrl->modified || (ctrl->info.flags & UVC_CTRL_FLAG_RESTORE) == 0) continue; - - printk(KERN_INFO "restoring control %pUl/%u/%u\n", - ctrl->info.entity, ctrl->info.index, - ctrl->info.selector); + dev_info(&dev->udev->dev, + "restoring control %pUl/%u/%u\n", + ctrl->info.entity, ctrl->info.index, + ctrl->info.selector); ctrl->dirty = 1; } @@ -2031,9 +2047,9 @@ static int uvc_ctrl_add_info(struct uvc_device *dev, struct uvc_control *ctrl, ctrl->initialized = 1; - uvc_trace(UVC_TRACE_CONTROL, "Added control %pUl/%u to device %s " - "entity %u\n", ctrl->info.entity, ctrl->info.selector, - dev->udev->devpath, ctrl->entity->id); + uvc_dbg(dev, CONTROL, "Added control %pUl/%u to device %s entity %u\n", + ctrl->info.entity, ctrl->info.selector, dev->udev->devpath, + ctrl->entity->id); return 0; } @@ -2070,8 +2086,7 @@ static int __uvc_ctrl_add_mapping(struct uvc_device *dev, map->set = uvc_set_le_value; list_add_tail(&map->list, &ctrl->info.mappings); - uvc_trace(UVC_TRACE_CONTROL, - "Adding mapping '%s' to control %pUl/%u.\n", + uvc_dbg(dev, CONTROL, "Adding mapping '%s' to control %pUl/%u\n", map->name, ctrl->info.entity, ctrl->info.selector); return 0; @@ -2088,9 +2103,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, int ret; if (mapping->id & ~V4L2_CTRL_ID_MASK) { - uvc_trace(UVC_TRACE_CONTROL, "Can't add mapping '%s', control " - "id 0x%08x is invalid.\n", mapping->name, - mapping->id); + uvc_dbg(dev, CONTROL, + "Can't add mapping '%s', control id 0x%08x is invalid\n", + mapping->name, mapping->id); return -EINVAL; } @@ -2135,8 +2150,8 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, list_for_each_entry(map, &ctrl->info.mappings, list) { if (mapping->id == map->id) { - uvc_trace(UVC_TRACE_CONTROL, "Can't add mapping '%s', " - "control id 0x%08x already exists.\n", + uvc_dbg(dev, CONTROL, + "Can't add mapping '%s', control id 0x%08x already exists\n", mapping->name, mapping->id); ret = -EEXIST; goto done; @@ -2146,9 +2161,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, /* Prevent excess memory consumption */ if (atomic_inc_return(&dev->nmappings) > UVC_MAX_CONTROL_MAPPINGS) { atomic_dec(&dev->nmappings); - uvc_trace(UVC_TRACE_CONTROL, "Can't add mapping '%s', maximum " - "mappings count (%u) exceeded.\n", mapping->name, - UVC_MAX_CONTROL_MAPPINGS); + uvc_dbg(dev, CONTROL, + "Can't add mapping '%s', maximum mappings count (%u) exceeded\n", + mapping->name, UVC_MAX_CONTROL_MAPPINGS); ret = -ENOMEM; goto done; } @@ -2217,8 +2232,9 @@ static void uvc_ctrl_prune_entity(struct uvc_device *dev, !uvc_test_bit(controls, blacklist[i].index)) continue; - uvc_trace(UVC_TRACE_CONTROL, "%u/%u control is black listed, " - "removing it.\n", entity->id, blacklist[i].index); + uvc_dbg(dev, CONTROL, + "%u/%u control is black listed, removing it\n", + entity->id, blacklist[i].index); uvc_clear_bit(controls, blacklist[i].index); } @@ -2294,6 +2310,9 @@ int uvc_ctrl_init_device(struct uvc_device *dev) } else if (UVC_ENTITY_TYPE(entity) == UVC_ITT_CAMERA) { bmControls = entity->camera.bmControls; bControlSize = entity->camera.bControlSize; + } else if (UVC_ENTITY_TYPE(entity) == UVC_EXT_GPIO_UNIT) { + bmControls = entity->gpio.bmControls; + bControlSize = entity->gpio.bControlSize; } /* Remove bogus/blacklisted controls */ diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index ddb9eaa11be7..30ef2a3110f7 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -7,6 +7,7 @@ */ #include <linux/atomic.h> +#include <linux/gpio/consumer.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/module.h> @@ -31,7 +32,7 @@ unsigned int uvc_clock_param = CLOCK_MONOTONIC; unsigned int uvc_hw_timestamps_param; unsigned int uvc_no_drop_param; static unsigned int uvc_quirks_param = -1; -unsigned int uvc_trace_param; +unsigned int uvc_dbg_param; unsigned int uvc_timeout_param = UVC_CTRL_STREAMING_TIMEOUT; /* ------------------------------------------------------------------------ @@ -519,10 +520,10 @@ static int uvc_parse_format(struct uvc_device *dev, case UVC_VS_FORMAT_FRAME_BASED: n = buffer[2] == UVC_VS_FORMAT_UNCOMPRESSED ? 27 : 28; if (buflen < n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d FORMAT error\n", - dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d FORMAT error\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber); return -EINVAL; } @@ -534,8 +535,8 @@ static int uvc_parse_format(struct uvc_device *dev, sizeof(format->name)); format->fcc = fmtdesc->fcc; } else { - uvc_printk(KERN_INFO, "Unknown video format %pUl\n", - &buffer[5]); + dev_info(&streaming->intf->dev, + "Unknown video format %pUl\n", &buffer[5]); snprintf(format->name, sizeof(format->name), "%pUl\n", &buffer[5]); format->fcc = 0; @@ -583,10 +584,10 @@ static int uvc_parse_format(struct uvc_device *dev, case UVC_VS_FORMAT_MJPEG: if (buflen < 11) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d FORMAT error\n", - dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d FORMAT error\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber); return -EINVAL; } @@ -599,10 +600,10 @@ static int uvc_parse_format(struct uvc_device *dev, case UVC_VS_FORMAT_DV: if (buflen < 9) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d FORMAT error\n", - dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d FORMAT error\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber); return -EINVAL; } @@ -617,10 +618,10 @@ static int uvc_parse_format(struct uvc_device *dev, strscpy(format->name, "HD-DV", sizeof(format->name)); break; default: - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d: unknown DV format %u\n", - dev->udev->devnum, - alts->desc.bInterfaceNumber, buffer[8]); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d: unknown DV format %u\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber, buffer[8]); return -EINVAL; } @@ -646,14 +647,14 @@ static int uvc_parse_format(struct uvc_device *dev, case UVC_VS_FORMAT_STREAM_BASED: /* Not supported yet. */ default: - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d unsupported format %u\n", - dev->udev->devnum, alts->desc.bInterfaceNumber, - buffer[2]); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d unsupported format %u\n", + dev->udev->devnum, alts->desc.bInterfaceNumber, + buffer[2]); return -EINVAL; } - uvc_trace(UVC_TRACE_DESCR, "Found format %s.\n", format->name); + uvc_dbg(dev, DESCR, "Found format %s\n", format->name); buflen -= buffer[0]; buffer += buffer[0]; @@ -672,9 +673,10 @@ static int uvc_parse_format(struct uvc_device *dev, n = n ? n : 3; if (buflen < 26 + 4*n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d FRAME error\n", dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d FRAME error\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber); return -EINVAL; } @@ -736,10 +738,10 @@ static int uvc_parse_format(struct uvc_device *dev, frame->dwDefaultFrameInterval; } - uvc_trace(UVC_TRACE_DESCR, "- %ux%u (%u.%u fps)\n", + uvc_dbg(dev, DESCR, "- %ux%u (%u.%u fps)\n", frame->wWidth, frame->wHeight, - 10000000/frame->dwDefaultFrameInterval, - (100000000/frame->dwDefaultFrameInterval)%10); + 10000000 / frame->dwDefaultFrameInterval, + (100000000 / frame->dwDefaultFrameInterval) % 10); format->nframes++; buflen -= buffer[0]; @@ -755,10 +757,10 @@ static int uvc_parse_format(struct uvc_device *dev, if (buflen > 2 && buffer[1] == USB_DT_CS_INTERFACE && buffer[2] == UVC_VS_COLORFORMAT) { if (buflen < 6) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d COLORFORMAT error\n", - dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d COLORFORMAT error\n", + dev->udev->devnum, + alts->desc.bInterfaceNumber); return -EINVAL; } @@ -790,15 +792,17 @@ static int uvc_parse_streaming(struct uvc_device *dev, if (intf->cur_altsetting->desc.bInterfaceSubClass != UVC_SC_VIDEOSTREAMING) { - uvc_trace(UVC_TRACE_DESCR, "device %d interface %d isn't a " - "video streaming interface\n", dev->udev->devnum, + uvc_dbg(dev, DESCR, + "device %d interface %d isn't a video streaming interface\n", + dev->udev->devnum, intf->altsetting[0].desc.bInterfaceNumber); return -EINVAL; } if (usb_driver_claim_interface(&uvc_driver.driver, intf, dev)) { - uvc_trace(UVC_TRACE_DESCR, "device %d interface %d is already " - "claimed\n", dev->udev->devnum, + uvc_dbg(dev, DESCR, + "device %d interface %d is already claimed\n", + dev->udev->devnum, intf->altsetting[0].desc.bInterfaceNumber); return -EINVAL; } @@ -821,8 +825,9 @@ static int uvc_parse_streaming(struct uvc_device *dev, if (ep->extralen > 2 && ep->extra[1] == USB_DT_CS_INTERFACE) { - uvc_trace(UVC_TRACE_DESCR, "trying extra data " - "from endpoint %u.\n", i); + uvc_dbg(dev, DESCR, + "trying extra data from endpoint %u\n", + i); buffer = alts->endpoint[i].extra; buflen = alts->endpoint[i].extralen; break; @@ -837,8 +842,8 @@ static int uvc_parse_streaming(struct uvc_device *dev, } if (buflen <= 2) { - uvc_trace(UVC_TRACE_DESCR, "no class-specific streaming " - "interface descriptors found.\n"); + uvc_dbg(dev, DESCR, + "no class-specific streaming interface descriptors found\n"); goto error; } @@ -855,9 +860,9 @@ static int uvc_parse_streaming(struct uvc_device *dev, break; default: - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " - "%d HEADER descriptor not found.\n", dev->udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d HEADER descriptor not found\n", + dev->udev->devnum, alts->desc.bInterfaceNumber); goto error; } @@ -865,8 +870,8 @@ static int uvc_parse_streaming(struct uvc_device *dev, n = buflen >= size ? buffer[size-1] : 0; if (buflen < size + p*n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d HEADER descriptor is invalid.\n", + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d HEADER descriptor is invalid\n", dev->udev->devnum, alts->desc.bInterfaceNumber); goto error; } @@ -917,8 +922,8 @@ static int uvc_parse_streaming(struct uvc_device *dev, case UVC_VS_FORMAT_MPEG2TS: case UVC_VS_FORMAT_STREAM_BASED: - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " - "interface %d FORMAT %u is not supported.\n", + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d FORMAT %u is not supported\n", dev->udev->devnum, alts->desc.bInterfaceNumber, _buffer[2]); break; @@ -942,8 +947,8 @@ static int uvc_parse_streaming(struct uvc_device *dev, } if (nformats == 0) { - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " - "%d has no supported formats defined.\n", + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d has no supported formats defined\n", dev->udev->devnum, alts->desc.bInterfaceNumber); goto error; } @@ -991,8 +996,8 @@ static int uvc_parse_streaming(struct uvc_device *dev, } if (buflen) - uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " - "%d has %u bytes of trailing descriptor garbage.\n", + uvc_dbg(dev, DESCR, + "device %d videostreaming interface %d has %u bytes of trailing descriptor garbage\n", dev->udev->devnum, alts->desc.bInterfaceNumber, buflen); /* Parse the alternate settings to find the maximum bandwidth. */ @@ -1019,7 +1024,13 @@ error: return ret; } -static struct uvc_entity *uvc_alloc_entity(u16 type, u8 id, +static const u8 uvc_camera_guid[16] = UVC_GUID_UVC_CAMERA; +static const u8 uvc_gpio_guid[16] = UVC_GUID_EXT_GPIO_CONTROLLER; +static const u8 uvc_media_transport_input_guid[16] = + UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT; +static const u8 uvc_processing_guid[16] = UVC_GUID_UVC_PROCESSING; + +static struct uvc_entity *uvc_alloc_entity(u16 type, u16 id, unsigned int num_pads, unsigned int extra_size) { struct uvc_entity *entity; @@ -1028,7 +1039,10 @@ static struct uvc_entity *uvc_alloc_entity(u16 type, u8 id, unsigned int i; extra_size = roundup(extra_size, sizeof(*entity->pads)); - num_inputs = (type & UVC_TERM_OUTPUT) ? num_pads : num_pads - 1; + if (num_pads) + num_inputs = type & UVC_TERM_OUTPUT ? num_pads : num_pads - 1; + else + num_inputs = 0; size = sizeof(*entity) + extra_size + sizeof(*entity->pads) * num_pads + num_inputs; entity = kzalloc(size, GFP_KERNEL); @@ -1038,13 +1052,32 @@ static struct uvc_entity *uvc_alloc_entity(u16 type, u8 id, entity->id = id; entity->type = type; + /* + * Set the GUID for standard entity types. For extension units, the GUID + * is initialized by the caller. + */ + switch (type) { + case UVC_EXT_GPIO_UNIT: + memcpy(entity->guid, uvc_gpio_guid, 16); + break; + case UVC_ITT_CAMERA: + memcpy(entity->guid, uvc_camera_guid, 16); + break; + case UVC_ITT_MEDIA_TRANSPORT_INPUT: + memcpy(entity->guid, uvc_media_transport_input_guid, 16); + break; + case UVC_VC_PROCESSING_UNIT: + memcpy(entity->guid, uvc_processing_guid, 16); + break; + } + entity->num_links = 0; entity->num_pads = num_pads; entity->pads = ((void *)(entity + 1)) + extra_size; for (i = 0; i < num_inputs; ++i) entity->pads[i].flags = MEDIA_PAD_FL_SINK; - if (!UVC_ENTITY_IS_OTERM(entity)) + if (!UVC_ENTITY_IS_OTERM(entity) && num_pads) entity->pads[num_pads-1].flags = MEDIA_PAD_FL_SOURCE; entity->bNrInPins = num_inputs; @@ -1098,8 +1131,8 @@ static int uvc_parse_vendor_control(struct uvc_device *dev, n = buflen >= 25 + p ? buffer[22+p] : 0; if (buflen < 25 + p + 2*n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d EXTENSION_UNIT error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d EXTENSION_UNIT error\n", udev->devnum, alts->desc.bInterfaceNumber); break; } @@ -1109,7 +1142,7 @@ static int uvc_parse_vendor_control(struct uvc_device *dev, if (unit == NULL) return -ENOMEM; - memcpy(unit->extension.guidExtensionCode, &buffer[4], 16); + memcpy(unit->guid, &buffer[4], 16); unit->extension.bNumControls = buffer[20]; memcpy(unit->baSourceID, &buffer[22], p); unit->extension.bControlSize = buffer[22+p]; @@ -1147,9 +1180,9 @@ static int uvc_parse_standard_control(struct uvc_device *dev, n = buflen >= 12 ? buffer[11] : 0; if (buflen < 12 + n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d HEADER error\n", udev->devnum, - alts->desc.bInterfaceNumber); + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d HEADER error\n", + udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1160,8 +1193,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, for (i = 0; i < n; ++i) { intf = usb_ifnum_to_if(udev, buffer[12+i]); if (intf == NULL) { - uvc_trace(UVC_TRACE_DESCR, "device %d " - "interface %d doesn't exists\n", + uvc_dbg(dev, DESCR, + "device %d interface %d doesn't exists\n", udev->devnum, i); continue; } @@ -1172,8 +1205,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, case UVC_VC_INPUT_TERMINAL: if (buflen < 8) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d INPUT_TERMINAL error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d INPUT_TERMINAL error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1191,10 +1224,9 @@ static int uvc_parse_standard_control(struct uvc_device *dev, */ type = get_unaligned_le16(&buffer[4]); if ((type & 0x7f00) == 0 || (type & 0x8000) != 0) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d INPUT_TERMINAL %d has invalid " - "type 0x%04x, skipping\n", udev->devnum, - alts->desc.bInterfaceNumber, + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d INPUT_TERMINAL %d has invalid type 0x%04x, skipping\n", + udev->devnum, alts->desc.bInterfaceNumber, buffer[3], type); return 0; } @@ -1214,8 +1246,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, } if (buflen < len + n + p) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d INPUT_TERMINAL error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d INPUT_TERMINAL error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1261,8 +1293,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, case UVC_VC_OUTPUT_TERMINAL: if (buflen < 9) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d OUTPUT_TERMINAL error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d OUTPUT_TERMINAL error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1272,10 +1304,10 @@ static int uvc_parse_standard_control(struct uvc_device *dev, */ type = get_unaligned_le16(&buffer[4]); if ((type & 0xff00) == 0) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d OUTPUT_TERMINAL %d has invalid " - "type 0x%04x, skipping\n", udev->devnum, - alts->desc.bInterfaceNumber, buffer[3], type); + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d OUTPUT_TERMINAL %d has invalid type 0x%04x, skipping\n", + udev->devnum, alts->desc.bInterfaceNumber, + buffer[3], type); return 0; } @@ -1299,8 +1331,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, p = buflen >= 5 ? buffer[4] : 0; if (buflen < 5 || buflen < 6 + p) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d SELECTOR_UNIT error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d SELECTOR_UNIT error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1325,8 +1357,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, p = dev->uvc_version >= 0x0110 ? 10 : 9; if (buflen < p + n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d PROCESSING_UNIT error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d PROCESSING_UNIT error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1358,8 +1390,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, n = buflen >= 24 + p ? buffer[22+p] : 0; if (buflen < 24 + p + n) { - uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " - "interface %d EXTENSION_UNIT error\n", + uvc_dbg(dev, DESCR, + "device %d videocontrol interface %d EXTENSION_UNIT error\n", udev->devnum, alts->desc.bInterfaceNumber); return -EINVAL; } @@ -1368,7 +1400,7 @@ static int uvc_parse_standard_control(struct uvc_device *dev, if (unit == NULL) return -ENOMEM; - memcpy(unit->extension.guidExtensionCode, &buffer[4], 16); + memcpy(unit->guid, &buffer[4], 16); unit->extension.bNumControls = buffer[20]; memcpy(unit->baSourceID, &buffer[22], p); unit->extension.bControlSize = buffer[22+p]; @@ -1385,8 +1417,9 @@ static int uvc_parse_standard_control(struct uvc_device *dev, break; default: - uvc_trace(UVC_TRACE_DESCR, "Found an unknown CS_INTERFACE " - "descriptor (%u)\n", buffer[2]); + uvc_dbg(dev, DESCR, + "Found an unknown CS_INTERFACE descriptor (%u)\n", + buffer[2]); break; } @@ -1431,8 +1464,9 @@ next_descriptor: if (usb_endpoint_is_int_in(desc) && le16_to_cpu(desc->wMaxPacketSize) >= 8 && desc->bInterval != 0) { - uvc_trace(UVC_TRACE_DESCR, "Found a Status endpoint " - "(addr %02x).\n", desc->bEndpointAddress); + uvc_dbg(dev, DESCR, + "Found a Status endpoint (addr %02x)\n", + desc->bEndpointAddress); dev->int_ep = ep; } } @@ -1440,6 +1474,108 @@ next_descriptor: return 0; } +/* ----------------------------------------------------------------------------- + * Privacy GPIO + */ + +static void uvc_gpio_event(struct uvc_device *dev) +{ + struct uvc_entity *unit = dev->gpio_unit; + struct uvc_video_chain *chain; + u8 new_val; + + if (!unit) + return; + + new_val = gpiod_get_value_cansleep(unit->gpio.gpio_privacy); + + /* GPIO entities are always on the first chain. */ + chain = list_first_entry(&dev->chains, struct uvc_video_chain, list); + uvc_ctrl_status_event(chain, unit->controls, &new_val); +} + +static int uvc_gpio_get_cur(struct uvc_device *dev, struct uvc_entity *entity, + u8 cs, void *data, u16 size) +{ + if (cs != UVC_CT_PRIVACY_CONTROL || size < 1) + return -EINVAL; + + *(u8 *)data = gpiod_get_value_cansleep(entity->gpio.gpio_privacy); + + return 0; +} + +static int uvc_gpio_get_info(struct uvc_device *dev, struct uvc_entity *entity, + u8 cs, u8 *caps) +{ + if (cs != UVC_CT_PRIVACY_CONTROL) + return -EINVAL; + + *caps = UVC_CONTROL_CAP_GET | UVC_CONTROL_CAP_AUTOUPDATE; + return 0; +} + +static irqreturn_t uvc_gpio_irq(int irq, void *data) +{ + struct uvc_device *dev = data; + + uvc_gpio_event(dev); + return IRQ_HANDLED; +} + +static int uvc_gpio_parse(struct uvc_device *dev) +{ + struct uvc_entity *unit; + struct gpio_desc *gpio_privacy; + int irq; + + gpio_privacy = devm_gpiod_get_optional(&dev->udev->dev, "privacy", + GPIOD_IN); + if (IS_ERR_OR_NULL(gpio_privacy)) + return PTR_ERR_OR_ZERO(gpio_privacy); + + unit = uvc_alloc_entity(UVC_EXT_GPIO_UNIT, UVC_EXT_GPIO_UNIT_ID, 0, 1); + if (!unit) + return -ENOMEM; + + irq = gpiod_to_irq(gpio_privacy); + if (irq < 0) { + if (irq != EPROBE_DEFER) + dev_err(&dev->udev->dev, + "No IRQ for privacy GPIO (%d)\n", irq); + return irq; + } + + unit->gpio.gpio_privacy = gpio_privacy; + unit->gpio.irq = irq; + unit->gpio.bControlSize = 1; + unit->gpio.bmControls = (u8 *)unit + sizeof(*unit); + unit->gpio.bmControls[0] = 1; + unit->get_cur = uvc_gpio_get_cur; + unit->get_info = uvc_gpio_get_info; + strscpy(unit->name, "GPIO", sizeof(unit->name)); + + list_add_tail(&unit->list, &dev->entities); + + dev->gpio_unit = unit; + + return 0; +} + +static int uvc_gpio_init_irq(struct uvc_device *dev) +{ + struct uvc_entity *unit = dev->gpio_unit; + + if (!unit || unit->gpio.irq < 0) + return 0; + + return devm_request_threaded_irq(&dev->udev->dev, unit->gpio.irq, NULL, + uvc_gpio_irq, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING, + "uvc_privacy_gpio", dev); +} + /* ------------------------------------------------------------------------ * UVC device scan */ @@ -1475,24 +1611,23 @@ static int uvc_scan_chain_entity(struct uvc_video_chain *chain, { switch (UVC_ENTITY_TYPE(entity)) { case UVC_VC_EXTENSION_UNIT: - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- XU %d", entity->id); + uvc_dbg_cont(PROBE, " <- XU %d", entity->id); if (entity->bNrInPins != 1) { - uvc_trace(UVC_TRACE_DESCR, "Extension unit %d has more " - "than 1 input pin.\n", entity->id); + uvc_dbg(chain->dev, DESCR, + "Extension unit %d has more than 1 input pin\n", + entity->id); return -1; } break; case UVC_VC_PROCESSING_UNIT: - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- PU %d", entity->id); + uvc_dbg_cont(PROBE, " <- PU %d", entity->id); if (chain->processing != NULL) { - uvc_trace(UVC_TRACE_DESCR, "Found multiple " - "Processing Units in chain.\n"); + uvc_dbg(chain->dev, DESCR, + "Found multiple Processing Units in chain\n"); return -1; } @@ -1500,16 +1635,15 @@ static int uvc_scan_chain_entity(struct uvc_video_chain *chain, break; case UVC_VC_SELECTOR_UNIT: - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- SU %d", entity->id); + uvc_dbg_cont(PROBE, " <- SU %d", entity->id); /* Single-input selector units are ignored. */ if (entity->bNrInPins == 1) break; if (chain->selector != NULL) { - uvc_trace(UVC_TRACE_DESCR, "Found multiple Selector " - "Units in chain.\n"); + uvc_dbg(chain->dev, DESCR, + "Found multiple Selector Units in chain\n"); return -1; } @@ -1519,33 +1653,29 @@ static int uvc_scan_chain_entity(struct uvc_video_chain *chain, case UVC_ITT_VENDOR_SPECIFIC: case UVC_ITT_CAMERA: case UVC_ITT_MEDIA_TRANSPORT_INPUT: - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- IT %d\n", entity->id); + uvc_dbg_cont(PROBE, " <- IT %d\n", entity->id); break; case UVC_OTT_VENDOR_SPECIFIC: case UVC_OTT_DISPLAY: case UVC_OTT_MEDIA_TRANSPORT_OUTPUT: - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " OT %d", entity->id); + uvc_dbg_cont(PROBE, " OT %d", entity->id); break; case UVC_TT_STREAMING: - if (UVC_ENTITY_IS_ITERM(entity)) { - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- IT %d\n", entity->id); - } else { - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " OT %d", entity->id); - } + if (UVC_ENTITY_IS_ITERM(entity)) + uvc_dbg_cont(PROBE, " <- IT %d\n", entity->id); + else + uvc_dbg_cont(PROBE, " OT %d", entity->id); break; default: - uvc_trace(UVC_TRACE_DESCR, "Unsupported entity type " - "0x%04x found in chain.\n", UVC_ENTITY_TYPE(entity)); + uvc_dbg(chain->dev, DESCR, + "Unsupported entity type 0x%04x found in chain\n", + UVC_ENTITY_TYPE(entity)); return -1; } @@ -1571,28 +1701,27 @@ static int uvc_scan_chain_forward(struct uvc_video_chain *chain, if (forward == prev) continue; if (forward->chain.next || forward->chain.prev) { - uvc_trace(UVC_TRACE_DESCR, "Found reference to " - "entity %d already in chain.\n", forward->id); + uvc_dbg(chain->dev, DESCR, + "Found reference to entity %d already in chain\n", + forward->id); return -EINVAL; } switch (UVC_ENTITY_TYPE(forward)) { case UVC_VC_EXTENSION_UNIT: if (forward->bNrInPins != 1) { - uvc_trace(UVC_TRACE_DESCR, "Extension unit %d " - "has more than 1 input pin.\n", - entity->id); + uvc_dbg(chain->dev, DESCR, + "Extension unit %d has more than 1 input pin\n", + entity->id); return -EINVAL; } list_add_tail(&forward->chain, &chain->entities); - if (uvc_trace_param & UVC_TRACE_PROBE) { - if (!found) - printk(KERN_CONT " (->"); + if (!found) + uvc_dbg_cont(PROBE, " (->"); - printk(KERN_CONT " XU %d", forward->id); - found = 1; - } + uvc_dbg_cont(PROBE, " XU %d", forward->id); + found = 1; break; case UVC_OTT_VENDOR_SPECIFIC: @@ -1600,24 +1729,23 @@ static int uvc_scan_chain_forward(struct uvc_video_chain *chain, case UVC_OTT_MEDIA_TRANSPORT_OUTPUT: case UVC_TT_STREAMING: if (UVC_ENTITY_IS_ITERM(forward)) { - uvc_trace(UVC_TRACE_DESCR, "Unsupported input " - "terminal %u.\n", forward->id); + uvc_dbg(chain->dev, DESCR, + "Unsupported input terminal %u\n", + forward->id); return -EINVAL; } list_add_tail(&forward->chain, &chain->entities); - if (uvc_trace_param & UVC_TRACE_PROBE) { - if (!found) - printk(KERN_CONT " (->"); + if (!found) + uvc_dbg_cont(PROBE, " (->"); - printk(KERN_CONT " OT %d", forward->id); - found = 1; - } + uvc_dbg_cont(PROBE, " OT %d", forward->id); + found = 1; break; } } if (found) - printk(KERN_CONT ")"); + uvc_dbg_cont(PROBE, ")"); return 0; } @@ -1642,36 +1770,33 @@ static int uvc_scan_chain_backward(struct uvc_video_chain *chain, break; } - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " <- IT"); + uvc_dbg_cont(PROBE, " <- IT"); chain->selector = entity; for (i = 0; i < entity->bNrInPins; ++i) { id = entity->baSourceID[i]; term = uvc_entity_by_id(chain->dev, id); if (term == NULL || !UVC_ENTITY_IS_ITERM(term)) { - uvc_trace(UVC_TRACE_DESCR, "Selector unit %d " - "input %d isn't connected to an " - "input terminal\n", entity->id, i); + uvc_dbg(chain->dev, DESCR, + "Selector unit %d input %d isn't connected to an input terminal\n", + entity->id, i); return -1; } if (term->chain.next || term->chain.prev) { - uvc_trace(UVC_TRACE_DESCR, "Found reference to " - "entity %d already in chain.\n", + uvc_dbg(chain->dev, DESCR, + "Found reference to entity %d already in chain\n", term->id); return -EINVAL; } - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT " %d", term->id); + uvc_dbg_cont(PROBE, " %d", term->id); list_add_tail(&term->chain, &chain->entities); uvc_scan_chain_forward(chain, term, entity); } - if (uvc_trace_param & UVC_TRACE_PROBE) - printk(KERN_CONT "\n"); + uvc_dbg_cont(PROBE, "\n"); id = 0; break; @@ -1694,8 +1819,8 @@ static int uvc_scan_chain_backward(struct uvc_video_chain *chain, entity = uvc_entity_by_id(chain->dev, id); if (entity == NULL) { - uvc_trace(UVC_TRACE_DESCR, "Found reference to " - "unknown entity %d.\n", id); + uvc_dbg(chain->dev, DESCR, + "Found reference to unknown entity %d\n", id); return -EINVAL; } @@ -1708,7 +1833,7 @@ static int uvc_scan_chain(struct uvc_video_chain *chain, { struct uvc_entity *entity, *prev; - uvc_trace(UVC_TRACE_PROBE, "Scanning UVC chain:"); + uvc_dbg(chain->dev, PROBE, "Scanning UVC chain:"); entity = term; prev = NULL; @@ -1716,8 +1841,9 @@ static int uvc_scan_chain(struct uvc_video_chain *chain, while (entity != NULL) { /* Entity must not be part of an existing chain */ if (entity->chain.next || entity->chain.prev) { - uvc_trace(UVC_TRACE_DESCR, "Found reference to " - "entity %d already in chain.\n", entity->id); + uvc_dbg(chain->dev, DESCR, + "Found reference to entity %d already in chain\n", + entity->id); return -EINVAL; } @@ -1871,9 +1997,8 @@ static int uvc_scan_fallback(struct uvc_device *dev) list_add_tail(&chain->list, &dev->chains); - uvc_trace(UVC_TRACE_PROBE, - "Found a video chain by fallback heuristic (%s).\n", - uvc_print_chain(chain)); + uvc_dbg(dev, PROBE, "Found a video chain by fallback heuristic (%s)\n", + uvc_print_chain(chain)); return 0; @@ -1915,8 +2040,8 @@ static int uvc_scan_device(struct uvc_device *dev) continue; } - uvc_trace(UVC_TRACE_PROBE, "Found a valid video chain (%s).\n", - uvc_print_chain(chain)); + uvc_dbg(dev, PROBE, "Found a valid video chain (%s)\n", + uvc_print_chain(chain)); list_add_tail(&chain->list, &dev->chains); } @@ -1925,10 +2050,17 @@ static int uvc_scan_device(struct uvc_device *dev) uvc_scan_fallback(dev); if (list_empty(&dev->chains)) { - uvc_printk(KERN_INFO, "No valid video chain found.\n"); + dev_info(&dev->udev->dev, "No valid video chain found.\n"); return -1; } + /* Add GPIO entity to the first chain. */ + if (dev->gpio_unit) { + chain = list_first_entry(&dev->chains, + struct uvc_video_chain, list); + list_add_tail(&dev->gpio_unit->chain, &chain->entities); + } + return 0; } @@ -2077,8 +2209,9 @@ int uvc_register_video_device(struct uvc_device *dev, ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); if (ret < 0) { - uvc_printk(KERN_ERR, "Failed to register %s device (%d).\n", - v4l2_type_names[type], ret); + dev_err(&stream->intf->dev, + "Failed to register %s device (%d).\n", + v4l2_type_names[type], ret); return ret; } @@ -2094,8 +2227,8 @@ static int uvc_register_video(struct uvc_device *dev, /* Initialize the streaming interface with default parameters. */ ret = uvc_video_init(stream); if (ret < 0) { - uvc_printk(KERN_ERR, "Failed to initialize the device (%d).\n", - ret); + dev_err(&stream->intf->dev, + "Failed to initialize the device (%d).\n", ret); return ret; } @@ -2129,8 +2262,9 @@ static int uvc_register_terms(struct uvc_device *dev, stream = uvc_stream_by_id(dev, term->id); if (stream == NULL) { - uvc_printk(KERN_INFO, "No streaming interface found " - "for terminal %u.", term->id); + dev_info(&dev->udev->dev, + "No streaming interface found for terminal %u.", + term->id); continue; } @@ -2163,8 +2297,8 @@ static int uvc_register_chains(struct uvc_device *dev) #ifdef CONFIG_MEDIA_CONTROLLER ret = uvc_mc_register_entities(chain); if (ret < 0) - uvc_printk(KERN_INFO, - "Failed to register entities (%d).\n", ret); + dev_info(&dev->udev->dev, + "Failed to register entities (%d).\n", ret); #endif } @@ -2187,14 +2321,6 @@ static int uvc_probe(struct usb_interface *intf, int function; int ret; - if (id->idVendor && id->idProduct) - uvc_trace(UVC_TRACE_PROBE, "Probing known UVC device %s " - "(%04x:%04x)\n", udev->devpath, id->idVendor, - id->idProduct); - else - uvc_trace(UVC_TRACE_PROBE, "Probing generic UVC device %s\n", - udev->devpath); - /* Allocate memory for the device and initialize it. */ dev = kzalloc(sizeof(*dev), GFP_KERNEL); if (dev == NULL) @@ -2214,6 +2340,13 @@ static int uvc_probe(struct usb_interface *intf, dev->quirks = uvc_quirks_param == -1 ? dev->info->quirks : uvc_quirks_param; + if (id->idVendor && id->idProduct) + uvc_dbg(dev, PROBE, "Probing known UVC device %s (%04x:%04x)\n", + udev->devpath, id->idVendor, id->idProduct); + else + uvc_dbg(dev, PROBE, "Probing generic UVC device %s\n", + udev->devpath); + if (udev->product != NULL) strscpy(dev->name, udev->product, sizeof(dev->name)); else @@ -2256,22 +2389,34 @@ static int uvc_probe(struct usb_interface *intf, /* Parse the Video Class control descriptor. */ if (uvc_parse_control(dev) < 0) { - uvc_trace(UVC_TRACE_PROBE, "Unable to parse UVC " - "descriptors.\n"); + uvc_dbg(dev, PROBE, "Unable to parse UVC descriptors\n"); + goto error; + } + + /* Parse the associated GPIOs. */ + if (uvc_gpio_parse(dev) < 0) { + uvc_dbg(dev, PROBE, "Unable to parse UVC GPIOs\n"); goto error; } - uvc_printk(KERN_INFO, "Found UVC %u.%02x device %s (%04x:%04x)\n", - dev->uvc_version >> 8, dev->uvc_version & 0xff, - udev->product ? udev->product : "<unnamed>", - le16_to_cpu(udev->descriptor.idVendor), - le16_to_cpu(udev->descriptor.idProduct)); + dev_info(&dev->udev->dev, "Found UVC %u.%02x device %s (%04x:%04x)\n", + dev->uvc_version >> 8, dev->uvc_version & 0xff, + udev->product ? udev->product : "<unnamed>", + le16_to_cpu(udev->descriptor.idVendor), + le16_to_cpu(udev->descriptor.idProduct)); if (dev->quirks != dev->info->quirks) { - uvc_printk(KERN_INFO, "Forcing device quirks to 0x%x by module " - "parameter for testing purpose.\n", dev->quirks); - uvc_printk(KERN_INFO, "Please report required quirks to the " - "linux-uvc-devel mailing list.\n"); + dev_info(&dev->udev->dev, + "Forcing device quirks to 0x%x by module parameter for testing purpose.\n", + dev->quirks); + dev_info(&dev->udev->dev, + "Please report required quirks to the linux-uvc-devel mailing list.\n"); + } + + if (dev->info->uvc_version) { + dev->uvc_version = dev->info->uvc_version; + dev_info(&dev->udev->dev, "Forcing UVC version to %u.%02x\n", + dev->uvc_version >> 8, dev->uvc_version & 0xff); } /* Register the V4L2 device. */ @@ -2300,12 +2445,19 @@ static int uvc_probe(struct usb_interface *intf, /* Initialize the interrupt URB. */ if ((ret = uvc_status_init(dev)) < 0) { - uvc_printk(KERN_INFO, "Unable to initialize the status " - "endpoint (%d), status interrupt will not be " - "supported.\n", ret); + dev_info(&dev->udev->dev, + "Unable to initialize the status endpoint (%d), status interrupt will not be supported.\n", + ret); } - uvc_trace(UVC_TRACE_PROBE, "UVC device initialized.\n"); + ret = uvc_gpio_init_irq(dev); + if (ret < 0) { + dev_err(&dev->udev->dev, + "Unable to request privacy GPIO IRQ (%d)\n", ret); + goto error; + } + + uvc_dbg(dev, PROBE, "UVC device initialized\n"); usb_enable_autosuspend(udev); return 0; @@ -2337,7 +2489,7 @@ static int uvc_suspend(struct usb_interface *intf, pm_message_t message) struct uvc_device *dev = usb_get_intfdata(intf); struct uvc_streaming *stream; - uvc_trace(UVC_TRACE_SUSPEND, "Suspending interface %u\n", + uvc_dbg(dev, SUSPEND, "Suspending interface %u\n", intf->cur_altsetting->desc.bInterfaceNumber); /* Controls are cached on the fly so they don't need to be saved. */ @@ -2355,8 +2507,8 @@ static int uvc_suspend(struct usb_interface *intf, pm_message_t message) return uvc_video_suspend(stream); } - uvc_trace(UVC_TRACE_SUSPEND, "Suspend: video streaming USB interface " - "mismatch.\n"); + uvc_dbg(dev, SUSPEND, + "Suspend: video streaming USB interface mismatch\n"); return -EINVAL; } @@ -2366,7 +2518,7 @@ static int __uvc_resume(struct usb_interface *intf, int reset) struct uvc_streaming *stream; int ret = 0; - uvc_trace(UVC_TRACE_SUSPEND, "Resuming interface %u\n", + uvc_dbg(dev, SUSPEND, "Resuming interface %u\n", intf->cur_altsetting->desc.bInterfaceNumber); if (intf->cur_altsetting->desc.bInterfaceSubClass == @@ -2395,8 +2547,8 @@ static int __uvc_resume(struct usb_interface *intf, int reset) } } - uvc_trace(UVC_TRACE_SUSPEND, "Resume: video streaming USB interface " - "mismatch.\n"); + uvc_dbg(dev, SUSPEND, + "Resume: video streaming USB interface mismatch\n"); return -EINVAL; } @@ -2446,7 +2598,7 @@ module_param_named(nodrop, uvc_no_drop_param, uint, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(nodrop, "Don't drop incomplete frames"); module_param_named(quirks, uvc_quirks_param, uint, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(quirks, "Forced device quirks"); -module_param_named(trace, uvc_trace_param, uint, S_IRUGO|S_IWUSR); +module_param_named(trace, uvc_dbg_param, uint, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(trace, "Trace level bitmask"); module_param_named(timeout, uvc_timeout_param, uint, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(timeout, "Streaming control requests timeout"); @@ -2923,6 +3075,17 @@ static const struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = (kernel_ulong_t)&uvc_quirk_probe_minmax }, + /* Shenzhen Aoni Electronic Co.,Ltd 2K FHD camera */ + { .match_flags = USB_DEVICE_ID_MATCH_DEVICE + | USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x1bcf, + .idProduct = 0x0b40, + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 0, + .driver_info = (kernel_ulong_t)&(const struct uvc_device_info){ + .uvc_version = 0x010a, + } }, /* SiGma Micro USB Web Camera */ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO, @@ -3002,7 +3165,6 @@ static int __init uvc_init(void) return ret; } - printk(KERN_INFO DRIVER_DESC " (" DRIVER_VERSION ")\n"); return 0; } diff --git a/drivers/media/usb/uvc/uvc_entity.c b/drivers/media/usb/uvc/uvc_entity.c index ca3a9c2eec27..7c4d2f93d351 100644 --- a/drivers/media/usb/uvc/uvc_entity.c +++ b/drivers/media/usb/uvc/uvc_entity.c @@ -105,6 +105,7 @@ static int uvc_mc_init_entity(struct uvc_video_chain *chain, case UVC_OTT_DISPLAY: case UVC_OTT_MEDIA_TRANSPORT_OUTPUT: case UVC_EXTERNAL_VENDOR_SPECIFIC: + case UVC_EXT_GPIO_UNIT: default: function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; break; @@ -139,8 +140,9 @@ int uvc_mc_register_entities(struct uvc_video_chain *chain) list_for_each_entry(entity, &chain->entities, chain) { ret = uvc_mc_init_entity(chain, entity); if (ret < 0) { - uvc_printk(KERN_INFO, "Failed to initialize entity for " - "entity %u\n", entity->id); + dev_info(&chain->dev->udev->dev, + "Failed to initialize entity for entity %u\n", + entity->id); return ret; } } @@ -148,8 +150,9 @@ int uvc_mc_register_entities(struct uvc_video_chain *chain) list_for_each_entry(entity, &chain->entities, chain) { ret = uvc_mc_create_links(chain, entity); if (ret < 0) { - uvc_printk(KERN_INFO, "Failed to create links for " - "entity %u\n", entity->id); + dev_info(&chain->dev->udev->dev, + "Failed to create links for entity %u\n", + entity->id); return ret; } } diff --git a/drivers/media/usb/uvc/uvc_isight.c b/drivers/media/usb/uvc/uvc_isight.c index 135fd7fe6852..2578d6ee4829 100644 --- a/drivers/media/usb/uvc/uvc_isight.c +++ b/drivers/media/usb/uvc/uvc_isight.c @@ -40,6 +40,7 @@ static int isight_decode(struct uvc_video_queue *queue, struct uvc_buffer *buf, 0xde, 0xad, 0xfa, 0xce }; + struct uvc_streaming *stream = uvc_queue_to_stream(queue); unsigned int maxlen, nbytes; u8 *mem; int is_header = 0; @@ -49,15 +50,15 @@ static int isight_decode(struct uvc_video_queue *queue, struct uvc_buffer *buf, if ((len >= 14 && memcmp(&data[2], hdr, 12) == 0) || (len >= 15 && memcmp(&data[3], hdr, 12) == 0)) { - uvc_trace(UVC_TRACE_FRAME, "iSight header found\n"); + uvc_dbg(stream->dev, FRAME, "iSight header found\n"); is_header = 1; } /* Synchronize to the input stream by waiting for a header packet. */ if (buf->state != UVC_BUF_STATE_ACTIVE) { if (!is_header) { - uvc_trace(UVC_TRACE_FRAME, "Dropping packet (out of " - "sync).\n"); + uvc_dbg(stream->dev, FRAME, + "Dropping packet (out of sync)\n"); return 0; } @@ -85,8 +86,8 @@ static int isight_decode(struct uvc_video_queue *queue, struct uvc_buffer *buf, buf->bytesused += nbytes; if (len > maxlen || buf->bytesused == buf->length) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete " - "(overflow).\n"); + uvc_dbg(stream->dev, FRAME, + "Frame complete (overflow)\n"); buf->state = UVC_BUF_STATE_DONE; } } @@ -103,9 +104,9 @@ void uvc_video_decode_isight(struct uvc_urb *uvc_urb, struct uvc_buffer *buf, for (i = 0; i < urb->number_of_packets; ++i) { if (urb->iso_frame_desc[i].status < 0) { - uvc_trace(UVC_TRACE_FRAME, "USB isochronous frame " - "lost (%d).\n", - urb->iso_frame_desc[i].status); + uvc_dbg(stream->dev, FRAME, + "USB isochronous frame lost (%d)\n", + urb->iso_frame_desc[i].status); } /* Decode the payload packet. diff --git a/drivers/media/usb/uvc/uvc_queue.c b/drivers/media/usb/uvc/uvc_queue.c index cd60c6c1749e..21a907d32bb7 100644 --- a/drivers/media/usb/uvc/uvc_queue.c +++ b/drivers/media/usb/uvc/uvc_queue.c @@ -32,12 +32,6 @@ * the driver. */ -static inline struct uvc_streaming * -uvc_queue_to_stream(struct uvc_video_queue *queue) -{ - return container_of(queue, struct uvc_streaming, queue); -} - static inline struct uvc_buffer *uvc_vbuf_to_buffer(struct vb2_v4l2_buffer *buf) { return container_of(buf, struct uvc_buffer, buf); @@ -109,7 +103,8 @@ static int uvc_buffer_prepare(struct vb2_buffer *vb) if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) { - uvc_trace(UVC_TRACE_CAPTURE, "[E] Bytes used out of bounds.\n"); + uvc_dbg(uvc_queue_to_stream(queue)->dev, CAPTURE, + "[E] Bytes used out of bounds\n"); return -EINVAL; } diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c index 2bdb0ff203f8..753c8226db70 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c @@ -93,22 +93,21 @@ static void uvc_event_streaming(struct uvc_device *dev, struct uvc_streaming_status *status, int len) { if (len < 3) { - uvc_trace(UVC_TRACE_STATUS, "Invalid streaming status event " - "received.\n"); + uvc_dbg(dev, STATUS, + "Invalid streaming status event received\n"); return; } if (status->bEvent == 0) { if (len < 4) return; - uvc_trace(UVC_TRACE_STATUS, "Button (intf %u) %s len %d\n", - status->bOriginator, - status->bValue[0] ? "pressed" : "released", len); + uvc_dbg(dev, STATUS, "Button (intf %u) %s len %d\n", + status->bOriginator, + status->bValue[0] ? "pressed" : "released", len); uvc_input_report_key(dev, KEY_CAMERA, status->bValue[0]); } else { - uvc_trace(UVC_TRACE_STATUS, - "Stream %u error event %02x len %d.\n", - status->bOriginator, status->bEvent, len); + uvc_dbg(dev, STATUS, "Stream %u error event %02x len %d\n", + status->bOriginator, status->bEvent, len); } } @@ -163,14 +162,13 @@ static bool uvc_event_control(struct urb *urb, if (len < 6 || status->bEvent != 0 || status->bAttribute >= ARRAY_SIZE(attrs)) { - uvc_trace(UVC_TRACE_STATUS, "Invalid control status event " - "received.\n"); + uvc_dbg(dev, STATUS, "Invalid control status event received\n"); return false; } - uvc_trace(UVC_TRACE_STATUS, "Control %u/%u %s change len %d.\n", - status->bOriginator, status->bSelector, - attrs[status->bAttribute], len); + uvc_dbg(dev, STATUS, "Control %u/%u %s change len %d\n", + status->bOriginator, status->bSelector, + attrs[status->bAttribute], len); /* Find the control. */ ctrl = uvc_event_find_ctrl(dev, status, &chain); @@ -179,7 +177,8 @@ static bool uvc_event_control(struct urb *urb, switch (status->bAttribute) { case UVC_CTRL_VALUE_CHANGE: - return uvc_ctrl_status_event(urb, chain, ctrl, status->bValue); + return uvc_ctrl_status_event_async(urb, chain, ctrl, + status->bValue); case UVC_CTRL_INFO_CHANGE: case UVC_CTRL_FAILURE_CHANGE: @@ -208,8 +207,9 @@ static void uvc_status_complete(struct urb *urb) return; default: - uvc_printk(KERN_WARNING, "Non-zero status (%d) in status " - "completion handler.\n", urb->status); + dev_warn(&dev->udev->dev, + "Non-zero status (%d) in status completion handler.\n", + urb->status); return; } @@ -235,18 +235,18 @@ static void uvc_status_complete(struct urb *urb) } default: - uvc_trace(UVC_TRACE_STATUS, "Unknown status event " - "type %u.\n", dev->status[0]); + uvc_dbg(dev, STATUS, "Unknown status event type %u\n", + dev->status[0]); break; } } /* Resubmit the URB. */ urb->interval = dev->int_ep->desc.bInterval; - if ((ret = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { - uvc_printk(KERN_ERR, "Failed to resubmit status URB (%d).\n", - ret); - } + ret = usb_submit_urb(urb, GFP_ATOMIC); + if (ret < 0) + dev_err(&dev->udev->dev, + "Failed to resubmit status URB (%d).\n", ret); } int uvc_status_init(struct uvc_device *dev) diff --git a/drivers/media/usb/uvc/uvc_v4l2.c b/drivers/media/usb/uvc/uvc_v4l2.c index fa06bfa174ad..252136cc885c 100644 --- a/drivers/media/usb/uvc/uvc_v4l2.c +++ b/drivers/media/usb/uvc/uvc_v4l2.c @@ -75,8 +75,8 @@ static int uvc_ioctl_ctrl_map(struct uvc_video_chain *chain, break; default: - uvc_trace(UVC_TRACE_CONTROL, "Unsupported V4L2 control type " - "%u.\n", xmap->v4l2_type); + uvc_dbg(chain->dev, CONTROL, + "Unsupported V4L2 control type %u\n", xmap->v4l2_type); ret = -ENOTTY; goto free_map; } @@ -164,10 +164,10 @@ static int uvc_v4l2_try_format(struct uvc_streaming *stream, return -EINVAL; fcc = (u8 *)&fmt->fmt.pix.pixelformat; - uvc_trace(UVC_TRACE_FORMAT, "Trying format 0x%08x (%c%c%c%c): %ux%u.\n", - fmt->fmt.pix.pixelformat, - fcc[0], fcc[1], fcc[2], fcc[3], - fmt->fmt.pix.width, fmt->fmt.pix.height); + uvc_dbg(stream->dev, FORMAT, "Trying format 0x%08x (%c%c%c%c): %ux%u\n", + fmt->fmt.pix.pixelformat, + fcc[0], fcc[1], fcc[2], fcc[3], + fmt->fmt.pix.width, fmt->fmt.pix.height); /* Check if the hardware supports the requested format, use the default * format otherwise. @@ -207,16 +207,17 @@ static int uvc_v4l2_try_format(struct uvc_streaming *stream, } if (frame == NULL) { - uvc_trace(UVC_TRACE_FORMAT, "Unsupported size %ux%u.\n", - fmt->fmt.pix.width, fmt->fmt.pix.height); + uvc_dbg(stream->dev, FORMAT, "Unsupported size %ux%u\n", + fmt->fmt.pix.width, fmt->fmt.pix.height); return -EINVAL; } /* Use the default frame interval. */ interval = frame->dwDefaultFrameInterval; - uvc_trace(UVC_TRACE_FORMAT, "Using default frame interval %u.%u us " - "(%u.%u fps).\n", interval/10, interval%10, 10000000/interval, - (100000000/interval)%10); + uvc_dbg(stream->dev, FORMAT, + "Using default frame interval %u.%u us (%u.%u fps)\n", + interval / 10, interval % 10, 10000000 / interval, + (100000000 / interval) % 10); /* Set the format index, frame index and frame interval. */ memset(probe, 0, sizeof(*probe)); @@ -248,7 +249,9 @@ static int uvc_v4l2_try_format(struct uvc_streaming *stream, goto done; /* After the probe, update fmt with the values returned from - * negotiation with the device. + * negotiation with the device. Some devices return invalid bFormatIndex + * and bFrameIndex values, in which case we can only assume they have + * accepted the requested format as-is. */ for (i = 0; i < stream->nformats; ++i) { if (probe->bFormatIndex == stream->format[i].index) { @@ -257,11 +260,10 @@ static int uvc_v4l2_try_format(struct uvc_streaming *stream, } } - if (i == stream->nformats) { - uvc_trace(UVC_TRACE_FORMAT, "Unknown bFormatIndex %u\n", - probe->bFormatIndex); - return -EINVAL; - } + if (i == stream->nformats) + uvc_dbg(stream->dev, FORMAT, + "Unknown bFormatIndex %u, using default\n", + probe->bFormatIndex); for (i = 0; i < format->nframes; ++i) { if (probe->bFrameIndex == format->frame[i].bFrameIndex) { @@ -270,11 +272,10 @@ static int uvc_v4l2_try_format(struct uvc_streaming *stream, } } - if (i == format->nframes) { - uvc_trace(UVC_TRACE_FORMAT, "Unknown bFrameIndex %u\n", - probe->bFrameIndex); - return -EINVAL; - } + if (i == format->nframes) + uvc_dbg(stream->dev, FORMAT, + "Unknown bFrameIndex %u, using default\n", + probe->bFrameIndex); fmt->fmt.pix.width = frame->wWidth; fmt->fmt.pix.height = frame->wHeight; @@ -416,7 +417,7 @@ static int uvc_v4l2_set_streamparm(struct uvc_streaming *stream, interval = uvc_fraction_to_interval(timeperframe.numerator, timeperframe.denominator); - uvc_trace(UVC_TRACE_FORMAT, "Setting frame interval to %u/%u (%u).\n", + uvc_dbg(stream->dev, FORMAT, "Setting frame interval to %u/%u (%u)\n", timeperframe.numerator, timeperframe.denominator, interval); mutex_lock(&stream->mutex); @@ -545,8 +546,8 @@ static int uvc_v4l2_open(struct file *file) struct uvc_fh *handle; int ret = 0; - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_open\n"); stream = video_drvdata(file); + uvc_dbg(stream->dev, CALLS, "%s\n", __func__); ret = usb_autopm_get_interface(stream->dev->intf); if (ret < 0) @@ -588,7 +589,7 @@ static int uvc_v4l2_release(struct file *file) struct uvc_fh *handle = file->private_data; struct uvc_streaming *stream = handle->stream; - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_release\n"); + uvc_dbg(stream->dev, CALLS, "%s\n", __func__); /* Only free resources if this is a privileged handle. */ if (uvc_has_privileges(handle)) @@ -1461,7 +1462,10 @@ static long uvc_v4l2_compat_ioctl32(struct file *file, static ssize_t uvc_v4l2_read(struct file *file, char __user *data, size_t count, loff_t *ppos) { - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_read: not implemented.\n"); + struct uvc_fh *handle = file->private_data; + struct uvc_streaming *stream = handle->stream; + + uvc_dbg(stream->dev, CALLS, "%s: not implemented\n", __func__); return -EINVAL; } @@ -1470,7 +1474,7 @@ static int uvc_v4l2_mmap(struct file *file, struct vm_area_struct *vma) struct uvc_fh *handle = file->private_data; struct uvc_streaming *stream = handle->stream; - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_mmap\n"); + uvc_dbg(stream->dev, CALLS, "%s\n", __func__); return uvc_queue_mmap(&stream->queue, vma); } @@ -1480,7 +1484,7 @@ static __poll_t uvc_v4l2_poll(struct file *file, poll_table *wait) struct uvc_fh *handle = file->private_data; struct uvc_streaming *stream = handle->stream; - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_poll\n"); + uvc_dbg(stream->dev, CALLS, "%s\n", __func__); return uvc_queue_poll(&stream->queue, file, wait); } @@ -1493,7 +1497,7 @@ static unsigned long uvc_v4l2_get_unmapped_area(struct file *file, struct uvc_fh *handle = file->private_data; struct uvc_streaming *stream = handle->stream; - uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_get_unmapped_area\n"); + uvc_dbg(stream->dev, CALLS, "%s\n", __func__); return uvc_queue_get_unmapped_area(&stream->queue, pgoff); } diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index a6a441d92b94..f2f565281e63 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -76,9 +76,9 @@ int uvc_query_ctrl(struct uvc_device *dev, u8 query, u8 unit, if (likely(ret == size)) return 0; - uvc_printk(KERN_ERR, - "Failed to query (%s) UVC control %u on unit %u: %d (exp. %u).\n", - uvc_query_name(query), cs, unit, ret, size); + dev_err(&dev->udev->dev, + "Failed to query (%s) UVC control %u on unit %u: %d (exp. %u).\n", + uvc_query_name(query), cs, unit, ret, size); if (ret != -EPIPE) return ret; @@ -95,7 +95,7 @@ int uvc_query_ctrl(struct uvc_device *dev, u8 query, u8 unit, if (ret != 1) return ret < 0 ? ret : -EPIPE; - uvc_trace(UVC_TRACE_CONTROL, "Control error %u\n", error); + uvc_dbg(dev, CONTROL, "Control error %u\n", error); switch (error) { case 0: @@ -254,9 +254,9 @@ static int uvc_get_video_ctrl(struct uvc_streaming *stream, ret = -EIO; goto out; } else if (ret != size) { - uvc_printk(KERN_ERR, "Failed to query (%u) UVC %s control : " - "%d (exp. %u).\n", query, probe ? "probe" : "commit", - ret, size); + dev_err(&stream->intf->dev, + "Failed to query (%u) UVC %s control : %d (exp. %u).\n", + query, probe ? "probe" : "commit", ret, size); ret = -EIO; goto out; } @@ -334,9 +334,9 @@ static int uvc_set_video_ctrl(struct uvc_streaming *stream, probe ? UVC_VS_PROBE_CONTROL : UVC_VS_COMMIT_CONTROL, data, size, uvc_timeout_param); if (ret != size) { - uvc_printk(KERN_ERR, "Failed to set UVC %s control : " - "%d (exp. %u).\n", probe ? "probe" : "commit", - ret, size); + dev_err(&stream->intf->dev, + "Failed to set UVC %s control : %d (exp. %u).\n", + probe ? "probe" : "commit", ret, size); ret = -EIO; } @@ -705,12 +705,12 @@ void uvc_video_clock_update(struct uvc_streaming *stream, sof = y; - uvc_trace(UVC_TRACE_CLOCK, "%s: PTS %u y %llu.%06llu SOF %u.%06llu " - "(x1 %u x2 %u y1 %u y2 %u SOF offset %u)\n", - stream->dev->name, buf->pts, - y >> 16, div_u64((y & 0xffff) * 1000000, 65536), - sof >> 16, div_u64(((u64)sof & 0xffff) * 1000000LLU, 65536), - x1, x2, y1, y2, clock->sof_offset); + uvc_dbg(stream->dev, CLOCK, + "%s: PTS %u y %llu.%06llu SOF %u.%06llu (x1 %u x2 %u y1 %u y2 %u SOF offset %u)\n", + stream->dev->name, buf->pts, + y >> 16, div_u64((y & 0xffff) * 1000000, 65536), + sof >> 16, div_u64(((u64)sof & 0xffff) * 1000000LLU, 65536), + x1, x2, y1, y2, clock->sof_offset); /* Second step, SOF to host clock conversion. */ x1 = (uvc_video_clock_host_sof(first) + 2048) << 16; @@ -740,13 +740,13 @@ void uvc_video_clock_update(struct uvc_streaming *stream, timestamp = ktime_to_ns(first->host_time) + y - y1; - uvc_trace(UVC_TRACE_CLOCK, "%s: SOF %u.%06llu y %llu ts %llu " - "buf ts %llu (x1 %u/%u/%u x2 %u/%u/%u y1 %u y2 %u)\n", - stream->dev->name, - sof >> 16, div_u64(((u64)sof & 0xffff) * 1000000LLU, 65536), - y, timestamp, vbuf->vb2_buf.timestamp, - x1, first->host_sof, first->dev_sof, - x2, last->host_sof, last->dev_sof, y1, y2); + uvc_dbg(stream->dev, CLOCK, + "%s: SOF %u.%06llu y %llu ts %llu buf ts %llu (x1 %u/%u/%u x2 %u/%u/%u y1 %u y2 %u)\n", + stream->dev->name, + sof >> 16, div_u64(((u64)sof & 0xffff) * 1000000LLU, 65536), + y, timestamp, vbuf->vb2_buf.timestamp, + x1, first->host_sof, first->dev_sof, + x2, last->host_sof, last->dev_sof, y1, y2); /* Update the V4L2 buffer. */ vbuf->vb2_buf.timestamp = timestamp; @@ -875,16 +875,15 @@ static void uvc_video_stats_update(struct uvc_streaming *stream) { struct uvc_stats_frame *frame = &stream->stats.frame; - uvc_trace(UVC_TRACE_STATS, "frame %u stats: %u/%u/%u packets, " - "%u/%u/%u pts (%searly %sinitial), %u/%u scr, " - "last pts/stc/sof %u/%u/%u\n", - stream->sequence, frame->first_data, - frame->nb_packets - frame->nb_empty, frame->nb_packets, - frame->nb_pts_diffs, frame->last_pts_diff, frame->nb_pts, - frame->has_early_pts ? "" : "!", - frame->has_initial_pts ? "" : "!", - frame->nb_scr_diffs, frame->nb_scr, - frame->pts, frame->scr_stc, frame->scr_sof); + uvc_dbg(stream->dev, STATS, + "frame %u stats: %u/%u/%u packets, %u/%u/%u pts (%searly %sinitial), %u/%u scr, last pts/stc/sof %u/%u/%u\n", + stream->sequence, frame->first_data, + frame->nb_packets - frame->nb_empty, frame->nb_packets, + frame->nb_pts_diffs, frame->last_pts_diff, frame->nb_pts, + frame->has_early_pts ? "" : "!", + frame->has_initial_pts ? "" : "!", + frame->nb_scr_diffs, frame->nb_scr, + frame->pts, frame->scr_stc, frame->scr_sof); stream->stats.stream.nb_frames++; stream->stats.stream.nb_packets += stream->stats.frame.nb_packets; @@ -1039,8 +1038,8 @@ static int uvc_video_decode_start(struct uvc_streaming *stream, /* Mark the buffer as bad if the error bit is set. */ if (data[1] & UVC_STREAM_ERR) { - uvc_trace(UVC_TRACE_FRAME, "Marking buffer as bad (error bit " - "set).\n"); + uvc_dbg(stream->dev, FRAME, + "Marking buffer as bad (error bit set)\n"); buf->error = 1; } @@ -1054,8 +1053,8 @@ static int uvc_video_decode_start(struct uvc_streaming *stream, */ if (buf->state != UVC_BUF_STATE_ACTIVE) { if (fid == stream->last_fid) { - uvc_trace(UVC_TRACE_FRAME, "Dropping payload (out of " - "sync).\n"); + uvc_dbg(stream->dev, FRAME, + "Dropping payload (out of sync)\n"); if ((stream->dev->quirks & UVC_QUIRK_STREAM_NO_FID) && (data[1] & UVC_STREAM_EOF)) stream->last_fid ^= UVC_STREAM_FID; @@ -1086,8 +1085,8 @@ static int uvc_video_decode_start(struct uvc_streaming *stream, * previous payload had the EOF bit set. */ if (fid != stream->last_fid && buf->bytesused != 0) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete (FID bit " - "toggled).\n"); + uvc_dbg(stream->dev, FRAME, + "Frame complete (FID bit toggled)\n"); buf->state = UVC_BUF_STATE_READY; return -EAGAIN; } @@ -1120,8 +1119,8 @@ static void uvc_video_copy_data_work(struct work_struct *work) ret = usb_submit_urb(uvc_urb->urb, GFP_KERNEL); if (ret < 0) - uvc_printk(KERN_ERR, "Failed to resubmit video URB (%d).\n", - ret); + dev_err(&uvc_urb->stream->intf->dev, + "Failed to resubmit video URB (%d).\n", ret); } static void uvc_video_decode_data(struct uvc_urb *uvc_urb, @@ -1148,7 +1147,8 @@ static void uvc_video_decode_data(struct uvc_urb *uvc_urb, /* Complete the current frame if the buffer size was exceeded. */ if (len > maxlen) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n"); + uvc_dbg(uvc_urb->stream->dev, FRAME, + "Frame complete (overflow)\n"); buf->error = 1; buf->state = UVC_BUF_STATE_READY; } @@ -1161,9 +1161,9 @@ static void uvc_video_decode_end(struct uvc_streaming *stream, { /* Mark the buffer as done if the EOF marker is set. */ if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) { - uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n"); + uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n"); if (data[0] == len) - uvc_trace(UVC_TRACE_FRAME, "EOF in empty payload.\n"); + uvc_dbg(stream->dev, FRAME, "EOF in empty payload\n"); buf->state = UVC_BUF_STATE_READY; if (stream->dev->quirks & UVC_QUIRK_STREAM_NO_FID) stream->last_fid ^= UVC_STREAM_FID; @@ -1279,13 +1279,13 @@ static void uvc_video_decode_meta(struct uvc_streaming *stream, memcpy(&meta->length, mem, length); meta_buf->bytesused += length + sizeof(meta->ns) + sizeof(meta->sof); - uvc_trace(UVC_TRACE_FRAME, - "%s(): t-sys %lluns, SOF %u, len %u, flags 0x%x, PTS %u, STC %u frame SOF %u\n", - __func__, ktime_to_ns(time), meta->sof, meta->length, - meta->flags, - has_pts ? *(u32 *)meta->buf : 0, - has_scr ? *(u32 *)scr : 0, - has_scr ? *(u32 *)(scr + 4) & 0x7ff : 0); + uvc_dbg(stream->dev, FRAME, + "%s(): t-sys %lluns, SOF %u, len %u, flags 0x%x, PTS %u, STC %u frame SOF %u\n", + __func__, ktime_to_ns(time), meta->sof, meta->length, + meta->flags, + has_pts ? *(u32 *)meta->buf : 0, + has_scr ? *(u32 *)scr : 0, + has_scr ? *(u32 *)(scr + 4) & 0x7ff : 0); } /* ------------------------------------------------------------------------ @@ -1339,8 +1339,9 @@ static void uvc_video_decode_isoc(struct uvc_urb *uvc_urb, for (i = 0; i < urb->number_of_packets; ++i) { if (urb->iso_frame_desc[i].status < 0) { - uvc_trace(UVC_TRACE_FRAME, "USB isochronous frame " - "lost (%d).\n", urb->iso_frame_desc[i].status); + uvc_dbg(stream->dev, FRAME, + "USB isochronous frame lost (%d)\n", + urb->iso_frame_desc[i].status); /* Mark the buffer as faulty. */ if (buf != NULL) buf->error = 1; @@ -1507,8 +1508,9 @@ static void uvc_video_complete(struct urb *urb) break; default: - uvc_printk(KERN_WARNING, "Non-zero status (%d) in video " - "completion handler.\n", urb->status); + dev_warn(&stream->intf->dev, + "Non-zero status (%d) in video completion handler.\n", + urb->status); fallthrough; case -ENOENT: /* usb_poison_urb() called. */ if (stream->frozen) @@ -1545,9 +1547,8 @@ static void uvc_video_complete(struct urb *urb) if (!uvc_urb->async_operations) { ret = usb_submit_urb(uvc_urb->urb, GFP_ATOMIC); if (ret < 0) - uvc_printk(KERN_ERR, - "Failed to resubmit video URB (%d).\n", - ret); + dev_err(&stream->intf->dev, + "Failed to resubmit video URB (%d).\n", ret); return; } @@ -1628,15 +1629,16 @@ static int uvc_alloc_urb_buffers(struct uvc_streaming *stream, } if (i == UVC_URBS) { - uvc_trace(UVC_TRACE_VIDEO, "Allocated %u URB buffers " - "of %ux%u bytes each.\n", UVC_URBS, npackets, - psize); + uvc_dbg(stream->dev, VIDEO, + "Allocated %u URB buffers of %ux%u bytes each\n", + UVC_URBS, npackets, psize); return npackets; } } - uvc_trace(UVC_TRACE_VIDEO, "Failed to allocate URB buffers (%u bytes " - "per packet).\n", psize); + uvc_dbg(stream->dev, VIDEO, + "Failed to allocate URB buffers (%u bytes per packet)\n", + psize); return 0; } @@ -1835,12 +1837,13 @@ static int uvc_video_start_transfer(struct uvc_streaming *stream, bandwidth = stream->ctrl.dwMaxPayloadTransferSize; if (bandwidth == 0) { - uvc_trace(UVC_TRACE_VIDEO, "Device requested null " - "bandwidth, defaulting to lowest.\n"); + uvc_dbg(stream->dev, VIDEO, + "Device requested null bandwidth, defaulting to lowest\n"); bandwidth = 1; } else { - uvc_trace(UVC_TRACE_VIDEO, "Device requested %u " - "B/frame bandwidth.\n", bandwidth); + uvc_dbg(stream->dev, VIDEO, + "Device requested %u B/frame bandwidth\n", + bandwidth); } for (i = 0; i < intf->num_altsetting; ++i) { @@ -1863,13 +1866,14 @@ static int uvc_video_start_transfer(struct uvc_streaming *stream, } if (best_ep == NULL) { - uvc_trace(UVC_TRACE_VIDEO, "No fast enough alt setting " - "for requested bandwidth.\n"); + uvc_dbg(stream->dev, VIDEO, + "No fast enough alt setting for requested bandwidth\n"); return -EIO; } - uvc_trace(UVC_TRACE_VIDEO, "Selecting alternate setting %u " - "(%u B/frame bandwidth).\n", altsetting, best_psize); + uvc_dbg(stream->dev, VIDEO, + "Selecting alternate setting %u (%u B/frame bandwidth)\n", + altsetting, best_psize); ret = usb_set_interface(stream->dev->udev, intfnum, altsetting); if (ret < 0) @@ -1893,8 +1897,9 @@ static int uvc_video_start_transfer(struct uvc_streaming *stream, for_each_uvc_urb(uvc_urb, stream) { ret = usb_submit_urb(uvc_urb->urb, gfp_flags); if (ret < 0) { - uvc_printk(KERN_ERR, "Failed to submit URB %u (%d).\n", - uvc_urb_index(uvc_urb), ret); + dev_err(&stream->intf->dev, + "Failed to submit URB %u (%d).\n", + uvc_urb_index(uvc_urb), ret); uvc_video_stop_transfer(stream, 1); return ret; } @@ -1989,7 +1994,8 @@ int uvc_video_init(struct uvc_streaming *stream) int ret; if (stream->nformats == 0) { - uvc_printk(KERN_INFO, "No supported video formats found.\n"); + dev_info(&stream->intf->dev, + "No supported video formats found.\n"); return -EINVAL; } @@ -2029,8 +2035,8 @@ int uvc_video_init(struct uvc_streaming *stream) } if (format->nframes == 0) { - uvc_printk(KERN_INFO, "No frame descriptor found for the " - "default format.\n"); + dev_info(&stream->intf->dev, + "No frame descriptor found for the default format.\n"); return -EINVAL; } @@ -2064,8 +2070,8 @@ int uvc_video_init(struct uvc_streaming *stream) if (stream->intf->num_altsetting == 1) stream->decode = uvc_video_encode_bulk; else { - uvc_printk(KERN_INFO, "Isochronous endpoints are not " - "supported for video output devices.\n"); + dev_info(&stream->intf->dev, + "Isochronous endpoints are not supported for video output devices.\n"); return -EINVAL; } } diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index a3dfacf069c4..97df5ecd66c9 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -6,6 +6,7 @@ #error "The uvcvideo.h header is deprecated, use linux/uvcvideo.h instead." #endif /* __KERNEL__ */ +#include <linux/atomic.h> #include <linux/kernel.h> #include <linux/poll.h> #include <linux/usb.h> @@ -37,6 +38,8 @@ (UVC_ENTITY_IS_TERM(entity) && \ ((entity)->type & 0x8000) == UVC_TERM_OUTPUT) +#define UVC_EXT_GPIO_UNIT 0x7ffe +#define UVC_EXT_GPIO_UNIT_ID 0x100 /* ------------------------------------------------------------------------ * GUIDs @@ -56,6 +59,9 @@ #define UVC_GUID_UVC_SELECTOR \ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02} +#define UVC_GUID_EXT_GPIO_CONTROLLER \ + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03} #define UVC_GUID_FORMAT_MJPEG \ { 'M', 'J', 'P', 'G', 0x00, 0x00, 0x10, 0x00, \ @@ -212,6 +218,7 @@ * Structures. */ +struct gpio_desc; struct uvc_device; /* TODO: Put the most frequently accessed fields at the beginning of @@ -301,9 +308,15 @@ struct uvc_entity { * chain. */ unsigned int flags; - u8 id; + /* + * Entities exposed by the UVC device use IDs 0-255, extra entities + * implemented by the driver (such as the GPIO entity) use IDs 256 and + * up. + */ + u16 id; u16 type; char name[64]; + u8 guid[16]; /* Media controller-related fields. */ struct video_device *vdev; @@ -342,17 +355,28 @@ struct uvc_entity { } selector; struct { - u8 guidExtensionCode[16]; u8 bNumControls; u8 bControlSize; u8 *bmControls; u8 *bmControlsType; } extension; + + struct { + u8 bControlSize; + u8 *bmControls; + struct gpio_desc *gpio_privacy; + int irq; + } gpio; }; u8 bNrInPins; u8 *baSourceID; + int (*get_info)(struct uvc_device *dev, struct uvc_entity *entity, + u8 cs, u8 *caps); + int (*get_cur)(struct uvc_device *dev, struct uvc_entity *entity, + u8 cs, void *data, u16 size); + unsigned int ncontrols; struct uvc_control *controls; }; @@ -635,6 +659,7 @@ static inline u32 uvc_urb_index(const struct uvc_urb *uvc_urb) struct uvc_device_info { u32 quirks; u32 meta_format; + u16 uvc_version; }; struct uvc_device { @@ -680,6 +705,8 @@ struct uvc_device { struct uvc_control *ctrl; const void *data; } async_ctrl; + + struct uvc_entity *gpio_unit; }; enum uvc_handle_state { @@ -702,18 +729,18 @@ struct uvc_driver { * Debugging, printing and logging */ -#define UVC_TRACE_PROBE (1 << 0) -#define UVC_TRACE_DESCR (1 << 1) -#define UVC_TRACE_CONTROL (1 << 2) -#define UVC_TRACE_FORMAT (1 << 3) -#define UVC_TRACE_CAPTURE (1 << 4) -#define UVC_TRACE_CALLS (1 << 5) -#define UVC_TRACE_FRAME (1 << 7) -#define UVC_TRACE_SUSPEND (1 << 8) -#define UVC_TRACE_STATUS (1 << 9) -#define UVC_TRACE_VIDEO (1 << 10) -#define UVC_TRACE_STATS (1 << 11) -#define UVC_TRACE_CLOCK (1 << 12) +#define UVC_DBG_PROBE (1 << 0) +#define UVC_DBG_DESCR (1 << 1) +#define UVC_DBG_CONTROL (1 << 2) +#define UVC_DBG_FORMAT (1 << 3) +#define UVC_DBG_CAPTURE (1 << 4) +#define UVC_DBG_CALLS (1 << 5) +#define UVC_DBG_FRAME (1 << 7) +#define UVC_DBG_SUSPEND (1 << 8) +#define UVC_DBG_STATUS (1 << 9) +#define UVC_DBG_VIDEO (1 << 10) +#define UVC_DBG_STATS (1 << 11) +#define UVC_DBG_CLOCK (1 << 12) #define UVC_WARN_MINMAX 0 #define UVC_WARN_PROBE_DEF 1 @@ -721,24 +748,28 @@ struct uvc_driver { extern unsigned int uvc_clock_param; extern unsigned int uvc_no_drop_param; -extern unsigned int uvc_trace_param; +extern unsigned int uvc_dbg_param; extern unsigned int uvc_timeout_param; extern unsigned int uvc_hw_timestamps_param; -#define uvc_trace(flag, msg...) \ - do { \ - if (uvc_trace_param & flag) \ - printk(KERN_DEBUG "uvcvideo: " msg); \ - } while (0) - -#define uvc_warn_once(dev, warn, msg...) \ - do { \ - if (!test_and_set_bit(warn, &dev->warnings)) \ - printk(KERN_INFO "uvcvideo: " msg); \ - } while (0) - -#define uvc_printk(level, msg...) \ - printk(level "uvcvideo: " msg) +#define uvc_dbg(_dev, flag, fmt, ...) \ +do { \ + if (uvc_dbg_param & UVC_DBG_##flag) \ + dev_printk(KERN_DEBUG, &(_dev)->udev->dev, fmt, \ + ##__VA_ARGS__); \ +} while (0) + +#define uvc_dbg_cont(flag, fmt, ...) \ +do { \ + if (uvc_dbg_param & UVC_DBG_##flag) \ + pr_cont(fmt, ##__VA_ARGS__); \ +} while (0) + +#define uvc_warn_once(_dev, warn, fmt, ...) \ +do { \ + if (!test_and_set_bit(warn, &(_dev)->warnings)) \ + dev_info(&(_dev)->udev->dev, fmt, ##__VA_ARGS__); \ +} while (0) /* -------------------------------------------------------------------------- * Internal functions. @@ -787,6 +818,12 @@ static inline int uvc_queue_streaming(struct uvc_video_queue *queue) return vb2_is_streaming(&queue->queue); } +static inline struct uvc_streaming * +uvc_queue_to_stream(struct uvc_video_queue *queue) +{ + return container_of(queue, struct uvc_streaming, queue); +} + /* V4L2 interface */ extern const struct v4l2_ioctl_ops uvc_ioctl_ops; extern const struct v4l2_file_operations uvc_fops; @@ -838,7 +875,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, int uvc_ctrl_init_device(struct uvc_device *dev); void uvc_ctrl_cleanup_device(struct uvc_device *dev); int uvc_ctrl_restore_values(struct uvc_device *dev); -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data); +void uvc_ctrl_status_event(struct uvc_video_chain *chain, struct uvc_control *ctrl, const u8 *data); int uvc_ctrl_begin(struct uvc_video_chain *chain); diff --git a/drivers/media/usb/zr364xx/zr364xx.c b/drivers/media/usb/zr364xx/zr364xx.c index 1e1c6b4d1874..d29b861367ea 100644 --- a/drivers/media/usb/zr364xx/zr364xx.c +++ b/drivers/media/usb/zr364xx/zr364xx.c @@ -1181,15 +1181,11 @@ out: return err; } -static void zr364xx_release(struct v4l2_device *v4l2_dev) +static void zr364xx_board_uninit(struct zr364xx_camera *cam) { - struct zr364xx_camera *cam = - container_of(v4l2_dev, struct zr364xx_camera, v4l2_dev); unsigned long i; - v4l2_device_unregister(&cam->v4l2_dev); - - videobuf_mmap_free(&cam->vb_vidq); + zr364xx_stop_readpipe(cam); /* release sys buffers */ for (i = 0; i < FRAMES; i++) { @@ -1200,9 +1196,19 @@ static void zr364xx_release(struct v4l2_device *v4l2_dev) cam->buffer.frame[i].lpvbits = NULL; } - v4l2_ctrl_handler_free(&cam->ctrl_handler); /* release transfer buffer */ kfree(cam->pipe->transfer_buffer); +} + +static void zr364xx_release(struct v4l2_device *v4l2_dev) +{ + struct zr364xx_camera *cam = + container_of(v4l2_dev, struct zr364xx_camera, v4l2_dev); + + videobuf_mmap_free(&cam->vb_vidq); + v4l2_ctrl_handler_free(&cam->ctrl_handler); + zr364xx_board_uninit(cam); + v4l2_device_unregister(&cam->v4l2_dev); kfree(cam); } @@ -1376,11 +1382,14 @@ static int zr364xx_board_init(struct zr364xx_camera *cam) /* start read pipe */ err = zr364xx_start_readpipe(cam); if (err) - goto err_free; + goto err_free_frames; DBG(": board initialized\n"); return 0; +err_free_frames: + for (i = 0; i < FRAMES; i++) + vfree(cam->buffer.frame[i].lpvbits); err_free: kfree(cam->pipe->transfer_buffer); cam->pipe->transfer_buffer = NULL; @@ -1409,12 +1418,10 @@ static int zr364xx_probe(struct usb_interface *intf, if (!cam) return -ENOMEM; - cam->v4l2_dev.release = zr364xx_release; err = v4l2_device_register(&intf->dev, &cam->v4l2_dev); if (err < 0) { dev_err(&udev->dev, "couldn't register v4l2_device\n"); - kfree(cam); - return err; + goto free_cam; } hdl = &cam->ctrl_handler; v4l2_ctrl_handler_init(hdl, 1); @@ -1423,7 +1430,7 @@ static int zr364xx_probe(struct usb_interface *intf, if (hdl->error) { err = hdl->error; dev_err(&udev->dev, "couldn't register control\n"); - goto fail; + goto unregister; } /* save the init method used by this camera */ cam->method = id->driver_info; @@ -1496,7 +1503,7 @@ static int zr364xx_probe(struct usb_interface *intf, if (!cam->read_endpoint) { err = -ENOMEM; dev_err(&intf->dev, "Could not find bulk-in endpoint\n"); - goto fail; + goto unregister; } /* v4l */ @@ -1507,10 +1514,11 @@ static int zr364xx_probe(struct usb_interface *intf, /* load zr364xx board specific */ err = zr364xx_board_init(cam); - if (!err) - err = v4l2_ctrl_handler_setup(hdl); if (err) - goto fail; + goto unregister; + err = v4l2_ctrl_handler_setup(hdl); + if (err) + goto board_uninit; spin_lock_init(&cam->slock); @@ -1525,16 +1533,21 @@ static int zr364xx_probe(struct usb_interface *intf, err = video_register_device(&cam->vdev, VFL_TYPE_VIDEO, -1); if (err) { dev_err(&udev->dev, "video_register_device failed\n"); - goto fail; + goto free_handler; } + cam->v4l2_dev.release = zr364xx_release; dev_info(&udev->dev, DRIVER_DESC " controlling device %s\n", video_device_node_name(&cam->vdev)); return 0; -fail: +free_handler: v4l2_ctrl_handler_free(hdl); +board_uninit: + zr364xx_board_uninit(cam); +unregister: v4l2_device_unregister(&cam->v4l2_dev); +free_cam: kfree(cam); return err; } diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile index 2ef0c7c958a2..e4cd589b99a5 100644 --- a/drivers/media/v4l2-core/Makefile +++ b/drivers/media/v4l2-core/Makefile @@ -6,7 +6,7 @@ tuner-objs := tuner-core.o videodev-objs := v4l2-dev.o v4l2-ioctl.o v4l2-device.o v4l2-fh.o \ - v4l2-event.o v4l2-ctrls.o v4l2-subdev.o v4l2-clk.o \ + v4l2-event.o v4l2-ctrls.o v4l2-subdev.o \ v4l2-async.o v4l2-common.o videodev-$(CONFIG_COMPAT) += v4l2-compat-ioctl32.o videodev-$(CONFIG_TRACEPOINTS) += v4l2-trace.o diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c index e3ab003a6c85..e638aa8aecb7 100644 --- a/drivers/media/v4l2-core/v4l2-async.c +++ b/drivers/media/v4l2-core/v4l2-async.c @@ -5,6 +5,7 @@ * Copyright (C) 2012-2013, Guennadi Liakhovetski <g.liakhovetski@gmx.de> */ +#include <linux/debugfs.h> #include <linux/device.h> #include <linux/err.h> #include <linux/i2c.h> @@ -14,6 +15,7 @@ #include <linux/mutex.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/types.h> @@ -64,12 +66,6 @@ static bool match_i2c(struct v4l2_async_notifier *notifier, #endif } -static bool match_devname(struct v4l2_async_notifier *notifier, - struct v4l2_subdev *sd, struct v4l2_async_subdev *asd) -{ - return !strcmp(asd->match.device_name, dev_name(sd->dev)); -} - static bool match_fwnode(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, struct v4l2_async_subdev *asd) { @@ -88,6 +84,14 @@ static bool match_fwnode(struct v4l2_async_notifier *notifier, return true; /* + * Check the same situation for any possible secondary assigned to the + * subdev's fwnode + */ + if (!IS_ERR_OR_NULL(sd->fwnode->secondary) && + sd->fwnode->secondary == asd->match.fwnode) + return true; + + /* * Otherwise, check if the sd fwnode and the asd fwnode refer to an * endpoint or a device. If they're of the same type, there's no match. * Technically speaking this checks if the nodes refer to a connected @@ -139,16 +143,6 @@ static bool match_fwnode(struct v4l2_async_notifier *notifier, return true; } -static bool match_custom(struct v4l2_async_notifier *notifier, - struct v4l2_subdev *sd, struct v4l2_async_subdev *asd) -{ - if (!asd->match.custom.match) - /* Match always */ - return true; - - return asd->match.custom.match(sd->dev, asd); -} - static LIST_HEAD(subdev_list); static LIST_HEAD(notifier_list); static DEFINE_MUTEX(list_lock); @@ -164,12 +158,6 @@ v4l2_async_find_match(struct v4l2_async_notifier *notifier, list_for_each_entry(asd, ¬ifier->waiting, list) { /* bus_type has been verified valid before */ switch (asd->match_type) { - case V4L2_ASYNC_MATCH_CUSTOM: - match = match_custom; - break; - case V4L2_ASYNC_MATCH_DEVNAME: - match = match_devname; - break; case V4L2_ASYNC_MATCH_I2C: match = match_i2c; break; @@ -198,9 +186,6 @@ static bool asd_equal(struct v4l2_async_subdev *asd_x, return false; switch (asd_x->match_type) { - case V4L2_ASYNC_MATCH_DEVNAME: - return strcmp(asd_x->match.device_name, - asd_y->match.device_name) == 0; case V4L2_ASYNC_MATCH_I2C: return asd_x->match.i2c.adapter_id == asd_y->match.i2c.adapter_id && @@ -467,8 +452,6 @@ static int v4l2_async_notifier_asd_valid(struct v4l2_async_notifier *notifier, return -EINVAL; switch (asd->match_type) { - case V4L2_ASYNC_MATCH_CUSTOM: - case V4L2_ASYNC_MATCH_DEVNAME: case V4L2_ASYNC_MATCH_I2C: case V4L2_ASYNC_MATCH_FWNODE: if (v4l2_async_notifier_has_async_subdev(notifier, asd, @@ -628,7 +611,7 @@ void v4l2_async_notifier_cleanup(struct v4l2_async_notifier *notifier) } EXPORT_SYMBOL_GPL(v4l2_async_notifier_cleanup); -int v4l2_async_notifier_add_subdev(struct v4l2_async_notifier *notifier, +int __v4l2_async_notifier_add_subdev(struct v4l2_async_notifier *notifier, struct v4l2_async_subdev *asd) { int ret; @@ -645,12 +628,12 @@ unlock: mutex_unlock(&list_lock); return ret; } -EXPORT_SYMBOL_GPL(v4l2_async_notifier_add_subdev); +EXPORT_SYMBOL_GPL(__v4l2_async_notifier_add_subdev); struct v4l2_async_subdev * -v4l2_async_notifier_add_fwnode_subdev(struct v4l2_async_notifier *notifier, - struct fwnode_handle *fwnode, - unsigned int asd_struct_size) +__v4l2_async_notifier_add_fwnode_subdev(struct v4l2_async_notifier *notifier, + struct fwnode_handle *fwnode, + unsigned int asd_struct_size) { struct v4l2_async_subdev *asd; int ret; @@ -662,7 +645,7 @@ v4l2_async_notifier_add_fwnode_subdev(struct v4l2_async_notifier *notifier, asd->match_type = V4L2_ASYNC_MATCH_FWNODE; asd->match.fwnode = fwnode_handle_get(fwnode); - ret = v4l2_async_notifier_add_subdev(notifier, asd); + ret = __v4l2_async_notifier_add_subdev(notifier, asd); if (ret) { fwnode_handle_put(fwnode); kfree(asd); @@ -671,35 +654,35 @@ v4l2_async_notifier_add_fwnode_subdev(struct v4l2_async_notifier *notifier, return asd; } -EXPORT_SYMBOL_GPL(v4l2_async_notifier_add_fwnode_subdev); +EXPORT_SYMBOL_GPL(__v4l2_async_notifier_add_fwnode_subdev); -int -v4l2_async_notifier_add_fwnode_remote_subdev(struct v4l2_async_notifier *notif, - struct fwnode_handle *endpoint, - struct v4l2_async_subdev *asd) +struct v4l2_async_subdev * +__v4l2_async_notifier_add_fwnode_remote_subdev(struct v4l2_async_notifier *notif, + struct fwnode_handle *endpoint, + unsigned int asd_struct_size) { + struct v4l2_async_subdev *asd; struct fwnode_handle *remote; - int ret; remote = fwnode_graph_get_remote_port_parent(endpoint); if (!remote) - return -ENOTCONN; - - asd->match_type = V4L2_ASYNC_MATCH_FWNODE; - asd->match.fwnode = remote; + return ERR_PTR(-ENOTCONN); - ret = v4l2_async_notifier_add_subdev(notif, asd); - if (ret) - fwnode_handle_put(remote); - - return ret; + asd = __v4l2_async_notifier_add_fwnode_subdev(notif, remote, + asd_struct_size); + /* + * Calling __v4l2_async_notifier_add_fwnode_subdev grabs a refcount, + * so drop the one we got in fwnode_graph_get_remote_port_parent. + */ + fwnode_handle_put(remote); + return asd; } -EXPORT_SYMBOL_GPL(v4l2_async_notifier_add_fwnode_remote_subdev); +EXPORT_SYMBOL_GPL(__v4l2_async_notifier_add_fwnode_remote_subdev); struct v4l2_async_subdev * -v4l2_async_notifier_add_i2c_subdev(struct v4l2_async_notifier *notifier, - int adapter_id, unsigned short address, - unsigned int asd_struct_size) +__v4l2_async_notifier_add_i2c_subdev(struct v4l2_async_notifier *notifier, + int adapter_id, unsigned short address, + unsigned int asd_struct_size) { struct v4l2_async_subdev *asd; int ret; @@ -712,7 +695,7 @@ v4l2_async_notifier_add_i2c_subdev(struct v4l2_async_notifier *notifier, asd->match.i2c.adapter_id = adapter_id; asd->match.i2c.address = address; - ret = v4l2_async_notifier_add_subdev(notifier, asd); + ret = __v4l2_async_notifier_add_subdev(notifier, asd); if (ret) { kfree(asd); return ERR_PTR(ret); @@ -720,32 +703,7 @@ v4l2_async_notifier_add_i2c_subdev(struct v4l2_async_notifier *notifier, return asd; } -EXPORT_SYMBOL_GPL(v4l2_async_notifier_add_i2c_subdev); - -struct v4l2_async_subdev * -v4l2_async_notifier_add_devname_subdev(struct v4l2_async_notifier *notifier, - const char *device_name, - unsigned int asd_struct_size) -{ - struct v4l2_async_subdev *asd; - int ret; - - asd = kzalloc(asd_struct_size, GFP_KERNEL); - if (!asd) - return ERR_PTR(-ENOMEM); - - asd->match_type = V4L2_ASYNC_MATCH_DEVNAME; - asd->match.device_name = device_name; - - ret = v4l2_async_notifier_add_subdev(notifier, asd); - if (ret) { - kfree(asd); - return ERR_PTR(ret); - } - - return asd; -} -EXPORT_SYMBOL_GPL(v4l2_async_notifier_add_devname_subdev); +EXPORT_SYMBOL_GPL(__v4l2_async_notifier_add_i2c_subdev); int v4l2_async_register_subdev(struct v4l2_subdev *sd) { @@ -817,6 +775,9 @@ EXPORT_SYMBOL(v4l2_async_register_subdev); void v4l2_async_unregister_subdev(struct v4l2_subdev *sd) { + if (!sd->async_list.next) + return; + mutex_lock(&list_lock); __v4l2_async_notifier_unregister(sd->subdev_notifier); @@ -837,3 +798,64 @@ void v4l2_async_unregister_subdev(struct v4l2_subdev *sd) mutex_unlock(&list_lock); } EXPORT_SYMBOL(v4l2_async_unregister_subdev); + +static void print_waiting_subdev(struct seq_file *s, + struct v4l2_async_subdev *asd) +{ + switch (asd->match_type) { + case V4L2_ASYNC_MATCH_I2C: + seq_printf(s, " [i2c] dev=%d-%04x\n", asd->match.i2c.adapter_id, + asd->match.i2c.address); + break; + case V4L2_ASYNC_MATCH_FWNODE: { + struct fwnode_handle *devnode, *fwnode = asd->match.fwnode; + + devnode = fwnode_graph_is_endpoint(fwnode) ? + fwnode_graph_get_port_parent(fwnode) : + fwnode_handle_get(fwnode); + + seq_printf(s, " [fwnode] dev=%s, node=%pfw\n", + devnode->dev ? dev_name(devnode->dev) : "nil", + fwnode); + + fwnode_handle_put(devnode); + break; + } + } +} + +static const char * +v4l2_async_notifier_name(struct v4l2_async_notifier *notifier) +{ + if (notifier->v4l2_dev) + return notifier->v4l2_dev->name; + else if (notifier->sd) + return notifier->sd->name; + else + return "nil"; +} + +static int pending_subdevs_show(struct seq_file *s, void *data) +{ + struct v4l2_async_notifier *notif; + struct v4l2_async_subdev *asd; + + mutex_lock(&list_lock); + + list_for_each_entry(notif, ¬ifier_list, list) { + seq_printf(s, "%s:\n", v4l2_async_notifier_name(notif)); + list_for_each_entry(asd, ¬if->waiting, list) + print_waiting_subdev(s, asd); + } + + mutex_unlock(&list_lock); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pending_subdevs); + +void v4l2_async_debug_init(struct dentry *debugfs_dir) +{ + debugfs_create_file("pending_async_subdevices", 0444, debugfs_dir, NULL, + &pending_subdevs_fops); +} diff --git a/drivers/media/v4l2-core/v4l2-clk.c b/drivers/media/v4l2-core/v4l2-clk.c deleted file mode 100644 index 91274eee6977..000000000000 --- a/drivers/media/v4l2-core/v4l2-clk.c +++ /dev/null @@ -1,321 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * V4L2 clock service - * - * Copyright (C) 2012-2013, Guennadi Liakhovetski <g.liakhovetski@gmx.de> - */ - -#include <linux/atomic.h> -#include <linux/clk.h> -#include <linux/device.h> -#include <linux/errno.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/mutex.h> -#include <linux/of.h> -#include <linux/slab.h> -#include <linux/string.h> - -#include <media/v4l2-clk.h> -#include <media/v4l2-subdev.h> - -static DEFINE_MUTEX(clk_lock); -static LIST_HEAD(clk_list); - -static struct v4l2_clk *v4l2_clk_find(const char *dev_id) -{ - struct v4l2_clk *clk; - - list_for_each_entry(clk, &clk_list, list) - if (!strcmp(dev_id, clk->dev_id)) - return clk; - - return ERR_PTR(-ENODEV); -} - -struct v4l2_clk *v4l2_clk_get(struct device *dev, const char *id) -{ - struct v4l2_clk *clk; - struct clk *ccf_clk = clk_get(dev, id); - char clk_name[V4L2_CLK_NAME_SIZE]; - - if (PTR_ERR(ccf_clk) == -EPROBE_DEFER) - return ERR_PTR(-EPROBE_DEFER); - - if (!IS_ERR_OR_NULL(ccf_clk)) { - clk = kzalloc(sizeof(*clk), GFP_KERNEL); - if (!clk) { - clk_put(ccf_clk); - return ERR_PTR(-ENOMEM); - } - clk->clk = ccf_clk; - - return clk; - } - - mutex_lock(&clk_lock); - clk = v4l2_clk_find(dev_name(dev)); - - /* if dev_name is not found, try use the OF name to find again */ - if (PTR_ERR(clk) == -ENODEV && dev->of_node) { - v4l2_clk_name_of(clk_name, sizeof(clk_name), dev->of_node); - clk = v4l2_clk_find(clk_name); - } - - if (!IS_ERR(clk)) - atomic_inc(&clk->use_count); - mutex_unlock(&clk_lock); - - return clk; -} -EXPORT_SYMBOL(v4l2_clk_get); - -void v4l2_clk_put(struct v4l2_clk *clk) -{ - struct v4l2_clk *tmp; - - if (IS_ERR(clk)) - return; - - if (clk->clk) { - clk_put(clk->clk); - kfree(clk); - return; - } - - mutex_lock(&clk_lock); - - list_for_each_entry(tmp, &clk_list, list) - if (tmp == clk) - atomic_dec(&clk->use_count); - - mutex_unlock(&clk_lock); -} -EXPORT_SYMBOL(v4l2_clk_put); - -static int v4l2_clk_lock_driver(struct v4l2_clk *clk) -{ - struct v4l2_clk *tmp; - int ret = -ENODEV; - - mutex_lock(&clk_lock); - - list_for_each_entry(tmp, &clk_list, list) - if (tmp == clk) { - ret = !try_module_get(clk->ops->owner); - if (ret) - ret = -EFAULT; - break; - } - - mutex_unlock(&clk_lock); - - return ret; -} - -static void v4l2_clk_unlock_driver(struct v4l2_clk *clk) -{ - module_put(clk->ops->owner); -} - -int v4l2_clk_enable(struct v4l2_clk *clk) -{ - int ret; - - if (clk->clk) - return clk_prepare_enable(clk->clk); - - ret = v4l2_clk_lock_driver(clk); - if (ret < 0) - return ret; - - mutex_lock(&clk->lock); - - if (++clk->enable == 1 && clk->ops->enable) { - ret = clk->ops->enable(clk); - if (ret < 0) - clk->enable--; - } - - mutex_unlock(&clk->lock); - - return ret; -} -EXPORT_SYMBOL(v4l2_clk_enable); - -/* - * You might Oops if you try to disabled a disabled clock, because then the - * driver isn't locked and could have been unloaded by now, so, don't do that - */ -void v4l2_clk_disable(struct v4l2_clk *clk) -{ - int enable; - - if (clk->clk) - return clk_disable_unprepare(clk->clk); - - mutex_lock(&clk->lock); - - enable = --clk->enable; - if (WARN(enable < 0, "Unbalanced %s() on %s!\n", __func__, - clk->dev_id)) - clk->enable++; - else if (!enable && clk->ops->disable) - clk->ops->disable(clk); - - mutex_unlock(&clk->lock); - - v4l2_clk_unlock_driver(clk); -} -EXPORT_SYMBOL(v4l2_clk_disable); - -unsigned long v4l2_clk_get_rate(struct v4l2_clk *clk) -{ - int ret; - - if (clk->clk) - return clk_get_rate(clk->clk); - - ret = v4l2_clk_lock_driver(clk); - if (ret < 0) - return ret; - - mutex_lock(&clk->lock); - if (!clk->ops->get_rate) - ret = -ENOSYS; - else - ret = clk->ops->get_rate(clk); - mutex_unlock(&clk->lock); - - v4l2_clk_unlock_driver(clk); - - return ret; -} -EXPORT_SYMBOL(v4l2_clk_get_rate); - -int v4l2_clk_set_rate(struct v4l2_clk *clk, unsigned long rate) -{ - int ret; - - if (clk->clk) { - long r = clk_round_rate(clk->clk, rate); - if (r < 0) - return r; - return clk_set_rate(clk->clk, r); - } - - ret = v4l2_clk_lock_driver(clk); - - if (ret < 0) - return ret; - - mutex_lock(&clk->lock); - if (!clk->ops->set_rate) - ret = -ENOSYS; - else - ret = clk->ops->set_rate(clk, rate); - mutex_unlock(&clk->lock); - - v4l2_clk_unlock_driver(clk); - - return ret; -} -EXPORT_SYMBOL(v4l2_clk_set_rate); - -struct v4l2_clk *v4l2_clk_register(const struct v4l2_clk_ops *ops, - const char *dev_id, - void *priv) -{ - struct v4l2_clk *clk; - int ret; - - if (!ops || !dev_id) - return ERR_PTR(-EINVAL); - - clk = kzalloc(sizeof(struct v4l2_clk), GFP_KERNEL); - if (!clk) - return ERR_PTR(-ENOMEM); - - clk->dev_id = kstrdup(dev_id, GFP_KERNEL); - if (!clk->dev_id) { - ret = -ENOMEM; - goto ealloc; - } - clk->ops = ops; - clk->priv = priv; - atomic_set(&clk->use_count, 0); - mutex_init(&clk->lock); - - mutex_lock(&clk_lock); - if (!IS_ERR(v4l2_clk_find(dev_id))) { - mutex_unlock(&clk_lock); - ret = -EEXIST; - goto eexist; - } - list_add_tail(&clk->list, &clk_list); - mutex_unlock(&clk_lock); - - return clk; - -eexist: -ealloc: - kfree(clk->dev_id); - kfree(clk); - return ERR_PTR(ret); -} -EXPORT_SYMBOL(v4l2_clk_register); - -void v4l2_clk_unregister(struct v4l2_clk *clk) -{ - if (WARN(atomic_read(&clk->use_count), - "%s(): Refusing to unregister ref-counted %s clock!\n", - __func__, clk->dev_id)) - return; - - mutex_lock(&clk_lock); - list_del(&clk->list); - mutex_unlock(&clk_lock); - - kfree(clk->dev_id); - kfree(clk); -} -EXPORT_SYMBOL(v4l2_clk_unregister); - -struct v4l2_clk_fixed { - unsigned long rate; - struct v4l2_clk_ops ops; -}; - -static unsigned long fixed_get_rate(struct v4l2_clk *clk) -{ - struct v4l2_clk_fixed *priv = clk->priv; - return priv->rate; -} - -struct v4l2_clk *__v4l2_clk_register_fixed(const char *dev_id, - unsigned long rate, struct module *owner) -{ - struct v4l2_clk *clk; - struct v4l2_clk_fixed *priv = kzalloc(sizeof(*priv), GFP_KERNEL); - - if (!priv) - return ERR_PTR(-ENOMEM); - - priv->rate = rate; - priv->ops.get_rate = fixed_get_rate; - priv->ops.owner = owner; - - clk = v4l2_clk_register(&priv->ops, dev_id, priv); - if (IS_ERR(clk)) - kfree(priv); - - return clk; -} -EXPORT_SYMBOL(__v4l2_clk_register_fixed); - -void v4l2_clk_unregister_fixed(struct v4l2_clk *clk) -{ - kfree(clk->priv); - v4l2_clk_unregister(clk); -} -EXPORT_SYMBOL(v4l2_clk_unregister_fixed); diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 5cbe0ffbf501..016cf6204cbb 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c +++ b/drivers/media/v4l2-core/v4l2-ctrls.c @@ -920,6 +920,15 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: return "H264 B-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: return "H264 B-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR: return "H264 Hierarchical Lay 0 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR: return "H264 Hierarchical Lay 1 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR: return "H264 Hierarchical Lay 2 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR: return "H264 Hierarchical Lay 3 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR: return "H264 Hierarchical Lay 4 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR: return "H264 Hierarchical Lay 5 Bitrate"; + case V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR: return "H264 Hierarchical Lay 6 Bitrate"; case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; @@ -941,6 +950,7 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE: return "Vertical MV Search Range"; case V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER: return "Repeat Sequence Header"; case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME: return "Force Key Frame"; + case V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID: return "Base Layer Priority ID"; case V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS: return "MPEG-2 Slice Parameters"; case V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION: return "MPEG-2 Quantization Matrices"; case V4L2_CID_FWHT_I_FRAME_QP: return "FWHT I-Frame QP Value"; @@ -969,6 +979,12 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: return "HEVC B-Frame QP Value"; case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: return "HEVC Minimum QP Value"; case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: return "HEVC Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: return "HEVC I-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: return "HEVC I-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: return "HEVC P-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: return "HEVC P-Frame Maximum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: return "HEVC B-Frame Minimum QP Value"; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: return "HEVC B-Frame Maximum QP Value"; case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: return "HEVC Profile"; case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: return "HEVC Level"; case V4L2_CID_MPEG_VIDEO_HEVC_TIER: return "HEVC Tier"; @@ -2165,7 +2181,8 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_INTEGER_MENU: if (ptr.p_s32[idx] < ctrl->minimum || ptr.p_s32[idx] > ctrl->maximum) return -ERANGE; - if (ctrl->menu_skip_mask & (1ULL << ptr.p_s32[idx])) + if (ptr.p_s32[idx] < BITS_PER_LONG_LONG && + (ctrl->menu_skip_mask & BIT_ULL(ptr.p_s32[idx]))) return -EINVAL; if (ctrl->type == V4L2_CTRL_TYPE_MENU && ctrl->qmenu[ptr.p_s32[idx]][0] == '\0') diff --git a/drivers/media/v4l2-core/v4l2-dev.c b/drivers/media/v4l2-core/v4l2-dev.c index a593ea0598b5..b6a72d297775 100644 --- a/drivers/media/v4l2-core/v4l2-dev.c +++ b/drivers/media/v4l2-core/v4l2-dev.c @@ -14,6 +14,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include <linux/debugfs.h> #include <linux/module.h> #include <linux/types.h> #include <linux/kernel.h> @@ -28,6 +29,7 @@ #include <media/v4l2-common.h> #include <media/v4l2-device.h> #include <media/v4l2-ioctl.h> +#include <media/v4l2-event.h> #define VIDEO_NUM_DEVICES 256 #define VIDEO_NAME "video4linux" @@ -37,6 +39,7 @@ __func__, ##arg); \ } while (0) +static struct dentry *v4l2_debugfs_dir; /* * sysfs stuff @@ -338,12 +341,14 @@ static ssize_t v4l2_write(struct file *filp, const char __user *buf, static __poll_t v4l2_poll(struct file *filp, struct poll_table_struct *poll) { struct video_device *vdev = video_devdata(filp); - __poll_t res = EPOLLERR | EPOLLHUP; + __poll_t res = EPOLLERR | EPOLLHUP | EPOLLPRI; - if (!vdev->fops->poll) - return DEFAULT_POLLMASK; - if (video_is_registered(vdev)) - res = vdev->fops->poll(filp, poll); + if (video_is_registered(vdev)) { + if (!vdev->fops->poll) + res = DEFAULT_POLLMASK; + else + res = vdev->fops->poll(filp, poll); + } if (vdev->dev_debug & V4L2_DEV_DEBUG_POLL) dprintk("%s: poll: %08x\n", video_device_node_name(vdev), res); @@ -1086,6 +1091,8 @@ void video_unregister_device(struct video_device *vdev) */ clear_bit(V4L2_FL_REGISTERED, &vdev->flags); mutex_unlock(&videodev_lock); + if (test_bit(V4L2_FL_USES_V4L2_FH, &vdev->flags)) + v4l2_event_wake_all(vdev); device_unregister(&vdev->dev); } EXPORT_SYMBOL(video_unregister_device); @@ -1113,6 +1120,8 @@ static int __init videodev_init(void) return -EIO; } + v4l2_debugfs_dir = debugfs_create_dir("video4linux", NULL); + v4l2_async_debug_init(v4l2_debugfs_dir); return 0; } @@ -1120,6 +1129,7 @@ static void __exit videodev_exit(void) { dev_t dev = MKDEV(VIDEO_MAJOR, 0); + debugfs_remove_recursive(v4l2_debugfs_dir); class_unregister(&video_class); unregister_chrdev_region(dev, VIDEO_NUM_DEVICES); } diff --git a/drivers/media/v4l2-core/v4l2-event.c b/drivers/media/v4l2-core/v4l2-event.c index 290c6b213179..caad58bde326 100644 --- a/drivers/media/v4l2-core/v4l2-event.c +++ b/drivers/media/v4l2-core/v4l2-event.c @@ -187,6 +187,23 @@ int v4l2_event_pending(struct v4l2_fh *fh) } EXPORT_SYMBOL_GPL(v4l2_event_pending); +void v4l2_event_wake_all(struct video_device *vdev) +{ + struct v4l2_fh *fh; + unsigned long flags; + + if (!vdev) + return; + + spin_lock_irqsave(&vdev->fh_lock, flags); + + list_for_each_entry(fh, &vdev->fh_list, list) + wake_up_all(&fh->wait); + + spin_unlock_irqrestore(&vdev->fh_lock, flags); +} +EXPORT_SYMBOL_GPL(v4l2_event_wake_all); + static void __v4l2_event_unsubscribe(struct v4l2_subscribed_event *sev) { struct v4l2_fh *fh = sev->fh; diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 5353e37eb950..2283ff3b8e1d 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -28,17 +28,6 @@ #include <media/v4l2-fwnode.h> #include <media/v4l2-subdev.h> -enum v4l2_fwnode_bus_type { - V4L2_FWNODE_BUS_TYPE_GUESS = 0, - V4L2_FWNODE_BUS_TYPE_CSI2_CPHY, - V4L2_FWNODE_BUS_TYPE_CSI1, - V4L2_FWNODE_BUS_TYPE_CCP2, - V4L2_FWNODE_BUS_TYPE_CSI2_DPHY, - V4L2_FWNODE_BUS_TYPE_PARALLEL, - V4L2_FWNODE_BUS_TYPE_BT656, - NR_OF_V4L2_FWNODE_BUS_TYPE, -}; - static const struct v4l2_fwnode_bus_conv { enum v4l2_fwnode_bus_type fwnode_bus_type; enum v4l2_mbus_type mbus_type; @@ -833,7 +822,7 @@ v4l2_async_notifier_fwnode_parse_endpoint(struct device *dev, if (ret < 0) goto out_err; - ret = v4l2_async_notifier_add_subdev(notifier, asd); + ret = __v4l2_async_notifier_add_subdev(notifier, asd); if (ret < 0) { /* not an error if asd already exists */ if (ret == -EEXIST) @@ -955,7 +944,7 @@ static int v4l2_fwnode_reference_parse(struct device *dev, asd = v4l2_async_notifier_add_fwnode_subdev(notifier, args.fwnode, - sizeof(*asd)); + struct v4l2_async_subdev); fwnode_handle_put(args.fwnode); if (IS_ERR(asd)) { /* not an error if asd already exists */ @@ -1255,7 +1244,7 @@ v4l2_fwnode_reference_parse_int_props(struct device *dev, struct v4l2_async_subdev *asd; asd = v4l2_async_notifier_add_fwnode_subdev(notifier, fwnode, - sizeof(*asd)); + struct v4l2_async_subdev); fwnode_handle_put(fwnode); if (IS_ERR(asd)) { ret = PTR_ERR(asd); diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 3198abdd538c..31d1342e61e8 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -518,9 +518,9 @@ static void v4l_print_create_buffers(const void *arg, bool write_only) { const struct v4l2_create_buffers *p = arg; - pr_cont("index=%d, count=%d, memory=%s, ", - p->index, p->count, - prt_names(p->memory, v4l2_memory_names)); + pr_cont("index=%d, count=%d, memory=%s, capabilities=0x%08x, ", + p->index, p->count, prt_names(p->memory, v4l2_memory_names), + p->capabilities); v4l_print_format(&p->format, write_only); } @@ -3283,7 +3283,7 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg, v4l2_kioctl func) { char sbuf[128]; - void *mbuf = NULL; + void *mbuf = NULL, *array_buf = NULL; void *parg = (void *)arg; long err = -EINVAL; bool has_array_args; @@ -3300,7 +3300,7 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg, parg = sbuf; } else { /* too big to allocate from stack */ - mbuf = kvmalloc(ioc_size, GFP_KERNEL); + mbuf = kmalloc(ioc_size, GFP_KERNEL); if (NULL == mbuf) return -ENOMEM; parg = mbuf; @@ -3318,27 +3318,21 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg, has_array_args = err; if (has_array_args) { - /* - * When adding new types of array args, make sure that the - * parent argument to ioctl (which contains the pointer to the - * array) fits into sbuf (so that mbuf will still remain - * unused up to here). - */ - mbuf = kvmalloc(array_size, GFP_KERNEL); + array_buf = kvmalloc(array_size, GFP_KERNEL); err = -ENOMEM; - if (NULL == mbuf) + if (array_buf == NULL) goto out_array_args; err = -EFAULT; if (in_compat_syscall()) - err = v4l2_compat_get_array_args(file, mbuf, user_ptr, - array_size, orig_cmd, - parg); + err = v4l2_compat_get_array_args(file, array_buf, + user_ptr, array_size, + orig_cmd, parg); else - err = copy_from_user(mbuf, user_ptr, array_size) ? + err = copy_from_user(array_buf, user_ptr, array_size) ? -EFAULT : 0; if (err) goto out_array_args; - *kernel_ptr = mbuf; + *kernel_ptr = array_buf; } /* Handles IOCTL */ @@ -3360,12 +3354,13 @@ video_usercopy(struct file *file, unsigned int orig_cmd, unsigned long arg, if (in_compat_syscall()) { int put_err; - put_err = v4l2_compat_put_array_args(file, user_ptr, mbuf, - array_size, orig_cmd, - parg); + put_err = v4l2_compat_put_array_args(file, user_ptr, + array_buf, + array_size, + orig_cmd, parg); if (put_err) err = put_err; - } else if (copy_to_user(user_ptr, mbuf, array_size)) { + } else if (copy_to_user(user_ptr, array_buf, array_size)) { err = -EFAULT; } goto out_array_args; @@ -3381,7 +3376,8 @@ out_array_args: if (video_put_user((void __user *)arg, parg, cmd, orig_cmd)) err = -EFAULT; out: - kvfree(mbuf); + kvfree(array_buf); + kfree(mbuf); return err; } diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c index b221b4e438a1..e7f4bf5bc8dd 100644 --- a/drivers/media/v4l2-core/v4l2-mem2mem.c +++ b/drivers/media/v4l2-core/v4l2-mem2mem.c @@ -887,9 +887,6 @@ static __poll_t v4l2_m2m_poll_for_data(struct file *file, src_q = v4l2_m2m_get_src_vq(m2m_ctx); dst_q = v4l2_m2m_get_dst_vq(m2m_ctx); - poll_wait(file, &src_q->done_wq, wait); - poll_wait(file, &dst_q->done_wq, wait); - /* * There has to be at least one buffer queued on each queued_list, which * means either in driver already or waiting for driver to claim it @@ -922,9 +919,21 @@ __poll_t v4l2_m2m_poll(struct file *file, struct v4l2_m2m_ctx *m2m_ctx, struct poll_table_struct *wait) { struct video_device *vfd = video_devdata(file); + struct vb2_queue *src_q = v4l2_m2m_get_src_vq(m2m_ctx); + struct vb2_queue *dst_q = v4l2_m2m_get_dst_vq(m2m_ctx); __poll_t req_events = poll_requested_events(wait); __poll_t rc = 0; + /* + * poll_wait() MUST be called on the first invocation on all the + * potential queues of interest, even if we are not interested in their + * events during this first call. Failure to do so will result in + * queue's events to be ignored because the poll_table won't be capable + * of adding new wait queues thereafter. + */ + poll_wait(file, &src_q->done_wq, wait); + poll_wait(file, &dst_q->done_wq, wait); + if (req_events & (EPOLLOUT | EPOLLWRNORM | EPOLLIN | EPOLLRDNORM)) rc = v4l2_m2m_poll_for_data(file, m2m_ctx, wait); diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig index e8996b1c3b35..ca59986b20f8 100644 --- a/drivers/staging/media/Kconfig +++ b/drivers/staging/media/Kconfig @@ -20,8 +20,6 @@ menuconfig STAGING_MEDIA if STAGING_MEDIA && MEDIA_SUPPORT # Please keep them in alphabetic order -source "drivers/staging/media/allegro-dvt/Kconfig" - source "drivers/staging/media/atomisp/Kconfig" source "drivers/staging/media/hantro/Kconfig" diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile index 24b5873ff760..716929a1a313 100644 --- a/drivers/staging/media/Makefile +++ b/drivers/staging/media/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro-dvt/ obj-$(CONFIG_INTEL_ATOMISP) += atomisp/ obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/ obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/ diff --git a/drivers/staging/media/allegro-dvt/Kconfig b/drivers/staging/media/allegro-dvt/Kconfig deleted file mode 100644 index 6b7107d9995c..000000000000 --- a/drivers/staging/media/allegro-dvt/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config VIDEO_ALLEGRO_DVT - tristate "Allegro DVT Video IP Core" - depends on VIDEO_DEV && VIDEO_V4L2 - depends on ARCH_ZYNQMP || COMPILE_TEST - select V4L2_MEM2MEM_DEV - select VIDEOBUF2_DMA_CONTIG - select REGMAP - select REGMAP_MMIO - help - Support for the encoder video IP core by Allegro DVT. This core is - found for example on the Xilinx ZynqMP SoC in the EV family and is - called VCU in the reference manual. - - To compile this driver as a module, choose M here: the module - will be called allegro. diff --git a/drivers/staging/media/allegro-dvt/Makefile b/drivers/staging/media/allegro-dvt/Makefile deleted file mode 100644 index 8e306dcdc55c..000000000000 --- a/drivers/staging/media/allegro-dvt/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -allegro-objs := allegro-core.o nal-h264.o allegro-mail.o - -obj-$(CONFIG_VIDEO_ALLEGRO_DVT) += allegro.o diff --git a/drivers/staging/media/allegro-dvt/TODO b/drivers/staging/media/allegro-dvt/TODO deleted file mode 100644 index 99e19be0e45a..000000000000 --- a/drivers/staging/media/allegro-dvt/TODO +++ /dev/null @@ -1,4 +0,0 @@ -TODO: - -- This driver is waiting for the stateful encoder spec and corresponding - v4l2-compliance tests to be finalized. diff --git a/drivers/staging/media/atomisp/pci/atomisp_subdev.c b/drivers/staging/media/atomisp/pci/atomisp_subdev.c index b666cb23e5ca..2ef5f44e4b6b 100644 --- a/drivers/staging/media/atomisp/pci/atomisp_subdev.c +++ b/drivers/staging/media/atomisp/pci/atomisp_subdev.c @@ -349,12 +349,20 @@ static int isp_subdev_get_selection(struct v4l2_subdev *sd, return 0; } -static char *atomisp_pad_str[] = { "ATOMISP_SUBDEV_PAD_SINK", - "ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE", - "ATOMISP_SUBDEV_PAD_SOURCE_VF", - "ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW", - "ATOMISP_SUBDEV_PAD_SOURCE_VIDEO" - }; +static const char *atomisp_pad_str(unsigned int pad) +{ + static const char *const pad_str[] = { + "ATOMISP_SUBDEV_PAD_SINK", + "ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE", + "ATOMISP_SUBDEV_PAD_SOURCE_VF", + "ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW", + "ATOMISP_SUBDEV_PAD_SOURCE_VIDEO", + }; + + if (pad >= ARRAY_SIZE(pad_str)) + return "ATOMISP_INVALID_PAD"; + return pad_str[pad]; +} int atomisp_subdev_set_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, @@ -378,7 +386,7 @@ int atomisp_subdev_set_selection(struct v4l2_subdev *sd, dev_dbg(isp->dev, "sel: pad %s tgt %s l %d t %d w %d h %d which %s f 0x%8.8x\n", - atomisp_pad_str[pad], target == V4L2_SEL_TGT_CROP + atomisp_pad_str(pad), target == V4L2_SEL_TGT_CROP ? "V4L2_SEL_TGT_CROP" : "V4L2_SEL_TGT_COMPOSE", r->left, r->top, r->width, r->height, which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" @@ -612,7 +620,7 @@ void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, enum atomisp_input_stream_id stream_id; dev_dbg(isp->dev, "ffmt: pad %s w %d h %d code 0x%8.8x which %s\n", - atomisp_pad_str[pad], ffmt->width, ffmt->height, ffmt->code, + atomisp_pad_str(pad), ffmt->width, ffmt->height, ffmt->code, which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" : "V4L2_SUBDEV_FORMAT_ACTIVE"); diff --git a/drivers/staging/media/atomisp/pci/ia_css_firmware.h b/drivers/staging/media/atomisp/pci/ia_css_firmware.h index edab72256494..e5e2f6fb37e0 100644 --- a/drivers/staging/media/atomisp/pci/ia_css_firmware.h +++ b/drivers/staging/media/atomisp/pci/ia_css_firmware.h @@ -20,6 +20,7 @@ * This file contains firmware loading/unloading support functionality */ +#include <linux/device.h> #include "ia_css_err.h" #include "ia_css_env.h" diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c index b4813cd50daa..4a18da6bf0c1 100644 --- a/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c @@ -368,6 +368,7 @@ static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor( break; case IA_CSS_CSI2_COMPRESSION_TYPE_2: predictor = MIPI_PREDICTOR_TYPE2 - 1; + break; default: break; } diff --git a/drivers/staging/media/atomisp/pci/sh_css_params.c b/drivers/staging/media/atomisp/pci/sh_css_params.c index 24fc497bd491..9fad28b97201 100644 --- a/drivers/staging/media/atomisp/pci/sh_css_params.c +++ b/drivers/staging/media/atomisp/pci/sh_css_params.c @@ -949,7 +949,7 @@ sh_css_set_black_frame(struct ia_css_stream *stream, params = stream->isp_params_configs; height = raw_black_frame->info.res.height; - width = raw_black_frame->info.padded_width, + width = raw_black_frame->info.padded_width; ptr = raw_black_frame->data + raw_black_frame->planes.raw.offset; @@ -1442,8 +1442,8 @@ static int sh_css_params_default_morph_table( IA_CSS_ENTER_PRIVATE(""); - step = (ISP_VEC_NELEMS / 16) * 128, - width = binary->morph_tbl_width, + step = (ISP_VEC_NELEMS / 16) * 128; + width = binary->morph_tbl_width; height = binary->morph_tbl_height; tab = ia_css_morph_table_allocate(width, height); diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c index f5fbdbc4ffdb..1bc118e375a1 100644 --- a/drivers/staging/media/hantro/hantro_v4l2.c +++ b/drivers/staging/media/hantro/hantro_v4l2.c @@ -316,7 +316,7 @@ hantro_reset_fmt(struct v4l2_pix_format_mplane *fmt, fmt->pixelformat = vpu_fmt->fourcc; fmt->field = V4L2_FIELD_NONE; - fmt->colorspace = V4L2_COLORSPACE_JPEG, + fmt->colorspace = V4L2_COLORSPACE_JPEG; fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; fmt->quantization = V4L2_QUANTIZATION_DEFAULT; fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT; diff --git a/drivers/staging/media/imx/Kconfig b/drivers/staging/media/imx/Kconfig index f555aac8a9d5..15322dc3124a 100644 --- a/drivers/staging/media/imx/Kconfig +++ b/drivers/staging/media/imx/Kconfig @@ -2,7 +2,7 @@ config VIDEO_IMX_MEDIA tristate "i.MX5/6 V4L2 media core driver" depends on ARCH_MXC || COMPILE_TEST - depends on VIDEO_V4L2 && IMX_IPUV3_CORE + depends on VIDEO_V4L2 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API depends on HAS_DMA @@ -14,21 +14,22 @@ config VIDEO_IMX_MEDIA driver for the i.MX5/6 SOC. if VIDEO_IMX_MEDIA -menu "i.MX5/6/7 Media Sub devices" +menu "i.MX5/6/7/8 Media Sub devices" config VIDEO_IMX_CSI tristate "i.MX5/6 Camera Sensor Interface driver" depends on VIDEO_IMX_MEDIA && VIDEO_DEV && I2C + depends on IMX_IPUV3_CORE default y help A video4linux camera sensor interface driver for i.MX5/6. config VIDEO_IMX7_CSI - tristate "i.MX6UL/L / i.MX7 Camera Sensor Interface driver" + tristate "i.MX6UL/L / i.MX7 / i.MX8M Camera Sensor Interface driver" depends on VIDEO_IMX_MEDIA && VIDEO_DEV && I2C default y help Enable support for video4linux camera sensor interface driver for - i.MX6UL/L or i.MX7. + i.MX6UL/L, i.MX7 or i.MX8M. endmenu endif diff --git a/drivers/staging/media/imx/Makefile b/drivers/staging/media/imx/Makefile index 9bd9e873ba7c..69cc5da04a2e 100644 --- a/drivers/staging/media/imx/Makefile +++ b/drivers/staging/media/imx/Makefile @@ -8,9 +8,9 @@ imx-media-common-objs := imx-media-capture.o imx-media-dev-common.o \ imx6-media-csi-objs := imx-media-csi.o imx-media-fim.o -obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx6-media.o obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx-media-common.o +obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-media.o obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-media-csi.o obj-$(CONFIG_VIDEO_IMX_CSI) += imx6-mipi-csi2.o diff --git a/drivers/staging/media/imx/imx-media-capture.c b/drivers/staging/media/imx/imx-media-capture.c index c1931eb2540e..e10ce103a5b4 100644 --- a/drivers/staging/media/imx/imx-media-capture.c +++ b/drivers/staging/media/imx/imx-media-capture.c @@ -816,14 +816,8 @@ void imx_media_capture_device_unregister(struct imx_media_video_dev *vdev) struct capture_priv *priv = to_capture_priv(vdev); struct video_device *vfd = priv->vdev.vfd; - mutex_lock(&priv->mutex); - - if (video_is_registered(vfd)) { - video_unregister_device(vfd); - media_entity_cleanup(&vfd->entity); - } - - mutex_unlock(&priv->mutex); + media_entity_cleanup(&vfd->entity); + video_unregister_device(vfd); } EXPORT_SYMBOL_GPL(imx_media_capture_device_unregister); diff --git a/drivers/staging/media/imx/imx-media-csc-scaler.c b/drivers/staging/media/imx/imx-media-csc-scaler.c index fab1155a5958..63a0204502a8 100644 --- a/drivers/staging/media/imx/imx-media-csc-scaler.c +++ b/drivers/staging/media/imx/imx-media-csc-scaler.c @@ -869,11 +869,7 @@ void imx_media_csc_scaler_device_unregister(struct imx_media_video_dev *vdev) struct ipu_csc_scaler_priv *priv = vdev_to_priv(vdev); struct video_device *vfd = priv->vdev.vfd; - mutex_lock(&priv->mutex); - video_unregister_device(vfd); - - mutex_unlock(&priv->mutex); } struct imx_media_video_dev * diff --git a/drivers/staging/media/imx/imx-media-csi.c b/drivers/staging/media/imx/imx-media-csi.c index db77fef07654..ef5add079774 100644 --- a/drivers/staging/media/imx/imx-media-csi.c +++ b/drivers/staging/media/imx/imx-media-csi.c @@ -1922,19 +1922,13 @@ static int imx_csi_async_register(struct csi_priv *priv) port, 0, FWNODE_GRAPH_ENDPOINT_NEXT); if (ep) { - asd = kzalloc(sizeof(*asd), GFP_KERNEL); - if (!asd) { - fwnode_handle_put(ep); - return -ENOMEM; - } - - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &priv->notifier, ep, asd); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &priv->notifier, ep, struct v4l2_async_subdev); fwnode_handle_put(ep); - if (ret) { - kfree(asd); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); /* OK if asd already exists */ if (ret != -EEXIST) return ret; diff --git a/drivers/staging/media/imx/imx-media-dev.c b/drivers/staging/media/imx/imx-media-dev.c index 6d2205461e56..338b8bd0bb07 100644 --- a/drivers/staging/media/imx/imx-media-dev.c +++ b/drivers/staging/media/imx/imx-media-dev.c @@ -53,6 +53,7 @@ static int imx6_media_probe_complete(struct v4l2_async_notifier *notifier) imxmd->m2m_vdev = imx_media_csc_scaler_device_init(imxmd); if (IS_ERR(imxmd->m2m_vdev)) { ret = PTR_ERR(imxmd->m2m_vdev); + imxmd->m2m_vdev = NULL; goto unlock; } @@ -107,10 +108,14 @@ static int imx_media_remove(struct platform_device *pdev) v4l2_info(&imxmd->v4l2_dev, "Removing imx-media\n"); + if (imxmd->m2m_vdev) { + imx_media_csc_scaler_device_unregister(imxmd->m2m_vdev); + imxmd->m2m_vdev = NULL; + } + v4l2_async_notifier_unregister(&imxmd->notifier); imx_media_unregister_ipu_internal_subdevs(imxmd); v4l2_async_notifier_cleanup(&imxmd->notifier); - imx_media_csc_scaler_device_unregister(imxmd->m2m_vdev); media_device_unregister(&imxmd->md); v4l2_device_unregister(&imxmd->v4l2_dev); media_device_cleanup(&imxmd->md); diff --git a/drivers/staging/media/imx/imx-media-of.c b/drivers/staging/media/imx/imx-media-of.c index 82e13e972e23..b677cf0e0c84 100644 --- a/drivers/staging/media/imx/imx-media-of.c +++ b/drivers/staging/media/imx/imx-media-of.c @@ -31,7 +31,7 @@ int imx_media_of_add_csi(struct imx_media_dev *imxmd, /* add CSI fwnode to async notifier */ asd = v4l2_async_notifier_add_fwnode_subdev(&imxmd->notifier, of_fwnode_handle(csi_np), - sizeof(*asd)); + struct v4l2_async_subdev); if (IS_ERR(asd)) { ret = PTR_ERR(asd); if (ret == -EEXIST) diff --git a/drivers/staging/media/imx/imx6-mipi-csi2.c b/drivers/staging/media/imx/imx6-mipi-csi2.c index 94d87d27d389..4f8fcc91aaae 100644 --- a/drivers/staging/media/imx/imx6-mipi-csi2.c +++ b/drivers/staging/media/imx/imx6-mipi-csi2.c @@ -42,7 +42,10 @@ struct csi2_dev { struct clk *pllref_clk; struct clk *pix_clk; /* what is this? */ void __iomem *base; - struct v4l2_fwnode_bus_mipi_csi2 bus; + + struct v4l2_subdev *remote; + unsigned int remote_pad; + unsigned short data_lanes; /* lock to protect all members below */ struct mutex lock; @@ -138,10 +141,8 @@ static void csi2_enable(struct csi2_dev *csi2, bool enable) } } -static void csi2_set_lanes(struct csi2_dev *csi2) +static void csi2_set_lanes(struct csi2_dev *csi2, unsigned int lanes) { - int lanes = csi2->bus.num_data_lanes; - writel(lanes - 1, csi2->base + CSI2_N_LANES); } @@ -250,13 +251,12 @@ static int __maybe_unused csi2_dphy_wait_ulp(struct csi2_dev *csi2) } /* Waits for low-power LP-11 state on data and clock lanes. */ -static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2) +static void csi2_dphy_wait_stopstate(struct csi2_dev *csi2, unsigned int lanes) { u32 mask, reg; int ret; - mask = PHY_STOPSTATECLK | (((1 << csi2->bus.num_data_lanes) - 1) << - PHY_STOPSTATEDATA_BIT); + mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT); ret = readl_poll_timeout(csi2->base + CSI2_PHY_STATE, reg, (reg & mask) == mask, 0, 500000); @@ -300,8 +300,65 @@ static void csi2ipu_gasket_init(struct csi2_dev *csi2) writel(reg, csi2->base + CSI2IPU_GASKET); } +static int csi2_get_active_lanes(struct csi2_dev *csi2, unsigned int *lanes) +{ + struct v4l2_mbus_config mbus_config = { 0 }; + unsigned int num_lanes = UINT_MAX; + int ret; + + *lanes = csi2->data_lanes; + + ret = v4l2_subdev_call(csi2->remote, pad, get_mbus_config, + csi2->remote_pad, &mbus_config); + if (ret == -ENOIOCTLCMD) { + dev_dbg(csi2->dev, "No remote mbus configuration available\n"); + return 0; + } + + if (ret) { + dev_err(csi2->dev, "Failed to get remote mbus configuration\n"); + return ret; + } + + if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) { + dev_err(csi2->dev, "Unsupported media bus type %u\n", + mbus_config.type); + return -EINVAL; + } + + switch (mbus_config.flags & V4L2_MBUS_CSI2_LANES) { + case V4L2_MBUS_CSI2_1_LANE: + num_lanes = 1; + break; + case V4L2_MBUS_CSI2_2_LANE: + num_lanes = 2; + break; + case V4L2_MBUS_CSI2_3_LANE: + num_lanes = 3; + break; + case V4L2_MBUS_CSI2_4_LANE: + num_lanes = 4; + break; + default: + num_lanes = csi2->data_lanes; + break; + } + + if (num_lanes > csi2->data_lanes) { + dev_err(csi2->dev, + "Unsupported mbus config: too many data lanes %u\n", + num_lanes); + return -EINVAL; + } + + *lanes = num_lanes; + + return 0; +} + static int csi2_start(struct csi2_dev *csi2) { + unsigned int lanes; int ret; ret = clk_prepare_enable(csi2->pix_clk); @@ -316,12 +373,16 @@ static int csi2_start(struct csi2_dev *csi2) if (ret) goto err_disable_clk; + ret = csi2_get_active_lanes(csi2, &lanes); + if (ret) + goto err_disable_clk; + /* Step 4 */ - csi2_set_lanes(csi2); + csi2_set_lanes(csi2, lanes); csi2_enable(csi2, true); /* Step 5 */ - csi2_dphy_wait_stopstate(csi2); + csi2_dphy_wait_stopstate(csi2, lanes); /* Step 6 */ ret = v4l2_subdev_call(csi2->src_sd, video, s_stream, 1); @@ -544,12 +605,35 @@ static int csi2_notify_bound(struct v4l2_async_notifier *notifier, { struct csi2_dev *csi2 = notifier_to_dev(notifier); struct media_pad *sink = &csi2->sd.entity.pads[CSI2_SINK_PAD]; + int pad; + + pad = media_entity_get_fwnode_pad(&sd->entity, asd->match.fwnode, + MEDIA_PAD_FL_SOURCE); + if (pad < 0) { + dev_err(csi2->dev, "Failed to find pad for %s\n", sd->name); + return pad; + } + + csi2->remote = sd; + csi2->remote_pad = pad; + + dev_dbg(csi2->dev, "Bound %s pad: %d\n", sd->name, pad); return v4l2_create_fwnode_links_to_pad(sd, sink); } +static void csi2_notify_unbind(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *sd, + struct v4l2_async_subdev *asd) +{ + struct csi2_dev *csi2 = notifier_to_dev(notifier); + + csi2->remote = NULL; +} + static const struct v4l2_async_notifier_operations csi2_notify_ops = { .bound = csi2_notify_bound, + .unbind = csi2_notify_unbind, }; static int csi2_async_register(struct csi2_dev *csi2) @@ -557,7 +641,7 @@ static int csi2_async_register(struct csi2_dev *csi2) struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY, }; - struct v4l2_async_subdev *asd = NULL; + struct v4l2_async_subdev *asd; struct fwnode_handle *ep; int ret; @@ -572,24 +656,18 @@ static int csi2_async_register(struct csi2_dev *csi2) if (ret) goto err_parse; - csi2->bus = vep.bus.mipi_csi2; - - dev_dbg(csi2->dev, "data lanes: %d\n", csi2->bus.num_data_lanes); - dev_dbg(csi2->dev, "flags: 0x%08x\n", csi2->bus.flags); + csi2->data_lanes = vep.bus.mipi_csi2.num_data_lanes; - asd = kzalloc(sizeof(*asd), GFP_KERNEL); - if (!asd) { - ret = -ENOMEM; - goto err_parse; - } - - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &csi2->notifier, ep, asd); - if (ret) - goto err_parse; + dev_dbg(csi2->dev, "data lanes: %d\n", vep.bus.mipi_csi2.num_data_lanes); + dev_dbg(csi2->dev, "flags: 0x%08x\n", vep.bus.mipi_csi2.flags); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &csi2->notifier, ep, struct v4l2_async_subdev); fwnode_handle_put(ep); + if (IS_ERR(asd)) + return PTR_ERR(asd); + csi2->notifier.ops = &csi2_notify_ops; ret = v4l2_async_subdev_notifier_register(&csi2->sd, @@ -601,7 +679,6 @@ static int csi2_async_register(struct csi2_dev *csi2) err_parse: fwnode_handle_put(ep); - kfree(asd); return ret; } diff --git a/drivers/staging/media/imx/imx7-media-csi.c b/drivers/staging/media/imx/imx7-media-csi.c index a3f3df901704..3046f880c014 100644 --- a/drivers/staging/media/imx/imx7-media-csi.c +++ b/drivers/staging/media/imx/imx7-media-csi.c @@ -499,6 +499,7 @@ static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd, struct v4l2_subdev_format *sink_fmt) { struct imx7_csi *csi = v4l2_get_subdevdata(sd); + struct media_entity *src; struct media_pad *pad; int ret; @@ -509,11 +510,21 @@ static int imx7_csi_pad_link_validate(struct v4l2_subdev *sd, if (!csi->src_sd) return -EPIPE; + src = &csi->src_sd->entity; + /* - * find the entity that is selected by the CSI mux. This is needed + * if the source is neither a CSI MUX or CSI-2 get the one directly + * upstream from this CSI + */ + if (src->function != MEDIA_ENT_F_VID_IF_BRIDGE && + src->function != MEDIA_ENT_F_VID_MUX) + src = &csi->sd.entity; + + /* + * find the entity that is selected by the source. This is needed * to distinguish between a parallel or CSI-2 pipeline. */ - pad = imx_media_pipeline_pad(&csi->src_sd->entity, 0, 0, true); + pad = imx_media_pipeline_pad(src, 0, 0, true); if (!pad) return -ENODEV; @@ -1164,12 +1175,12 @@ static int imx7_csi_notify_bound(struct v4l2_async_notifier *notifier, struct imx7_csi *csi = imx7_csi_notifier_to_dev(notifier); struct media_pad *sink = &csi->sd.entity.pads[IMX7_CSI_PAD_SINK]; - /* The bound subdev must always be the CSI mux */ - if (WARN_ON(sd->entity.function != MEDIA_ENT_F_VID_MUX)) - return -ENXIO; - - /* Mark it as such via its group id */ - sd->grp_id = IMX_MEDIA_GRP_ID_CSI_MUX; + /* + * If the subdev is a video mux, it must be one of the CSI + * muxes. Mark it as such via its group id. + */ + if (sd->entity.function == MEDIA_ENT_F_VID_MUX) + sd->grp_id = IMX_MEDIA_GRP_ID_CSI_MUX; return v4l2_create_fwnode_links_to_pad(sd, sink); } @@ -1180,7 +1191,7 @@ static const struct v4l2_async_notifier_operations imx7_csi_notify_ops = { static int imx7_csi_async_register(struct imx7_csi *csi) { - struct v4l2_async_subdev *asd = NULL; + struct v4l2_async_subdev *asd; struct fwnode_handle *ep; int ret; @@ -1189,19 +1200,13 @@ static int imx7_csi_async_register(struct imx7_csi *csi) ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0, FWNODE_GRAPH_ENDPOINT_NEXT); if (ep) { - asd = kzalloc(sizeof(*asd), GFP_KERNEL); - if (!asd) { - fwnode_handle_put(ep); - return -ENOMEM; - } - - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &csi->notifier, ep, asd); + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &csi->notifier, ep, struct v4l2_async_subdev); fwnode_handle_put(ep); - if (ret) { - kfree(asd); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); /* OK if asd already exists */ if (ret != -EEXIST) return ret; diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c index 7612993cc1d6..a01a7364b4b9 100644 --- a/drivers/staging/media/imx/imx7-mipi-csis.c +++ b/drivers/staging/media/imx/imx7-mipi-csis.c @@ -1004,7 +1004,7 @@ static int mipi_csis_async_register(struct csi_state *state) struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY, }; - struct v4l2_async_subdev *asd = NULL; + struct v4l2_async_subdev *asd; struct fwnode_handle *ep; int ret; @@ -1024,17 +1024,13 @@ static int mipi_csis_async_register(struct csi_state *state) dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes); dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags); - asd = kzalloc(sizeof(*asd), GFP_KERNEL); - if (!asd) { - ret = -ENOMEM; + asd = v4l2_async_notifier_add_fwnode_remote_subdev( + &state->notifier, ep, struct v4l2_async_subdev); + if (IS_ERR(asd)) { + ret = PTR_ERR(asd); goto err_parse; } - ret = v4l2_async_notifier_add_fwnode_remote_subdev( - &state->notifier, ep, asd); - if (ret) - goto err_parse; - fwnode_handle_put(ep); state->notifier.ops = &mipi_csis_notify_ops; @@ -1048,7 +1044,6 @@ static int mipi_csis_async_register(struct csi_state *state) err_parse: fwnode_handle_put(ep); - kfree(asd); return ret; } diff --git a/drivers/staging/media/ipu3/ipu3-v4l2.c b/drivers/staging/media/ipu3/ipu3-v4l2.c index 4dc8d9165f63..60aa02eb7d2a 100644 --- a/drivers/staging/media/ipu3/ipu3-v4l2.c +++ b/drivers/staging/media/ipu3/ipu3-v4l2.c @@ -773,9 +773,6 @@ static int imgu_try_fmt(struct file *file, void *fh, struct v4l2_format *f) pixm->pixelformat = fmt->fourcc; - memset(pixm->plane_fmt[0].reserved, 0, - sizeof(pixm->plane_fmt[0].reserved)); - return 0; } diff --git a/drivers/staging/media/omap4iss/iss.c b/drivers/staging/media/omap4iss/iss.c index e06ea7ea1e50..dae9073e7d3c 100644 --- a/drivers/staging/media/omap4iss/iss.c +++ b/drivers/staging/media/omap4iss/iss.c @@ -1349,4 +1349,3 @@ module_platform_driver(iss_driver); MODULE_DESCRIPTION("TI OMAP4 ISS driver"); MODULE_AUTHOR("Sergio Aguirre <sergio.a.aguirre@gmail.com>"); MODULE_LICENSE("GPL"); -MODULE_VERSION(ISS_VIDEO_DRIVER_VERSION); diff --git a/drivers/staging/media/omap4iss/iss_video.h b/drivers/staging/media/omap4iss/iss_video.h index 8b3dd92021e1..526281bf0051 100644 --- a/drivers/staging/media/omap4iss/iss_video.h +++ b/drivers/staging/media/omap4iss/iss_video.h @@ -18,7 +18,6 @@ #include <media/videobuf2-dma-contig.h> #define ISS_VIDEO_DRIVER_NAME "issvideo" -#define ISS_VIDEO_DRIVER_VERSION "0.0.2" struct iss_device; struct iss_video; diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c index aa4f8c287618..d3eb81ee8dc2 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -143,7 +143,7 @@ static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, memset(f, 0, sizeof(*f)); f->fmt.pix_mp.pixelformat = fourcc; f->fmt.pix_mp.field = V4L2_FIELD_NONE; - f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709, + f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index ddad5d274ee8..7bd9291c8d5f 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -34,56 +34,48 @@ static const struct cedrus_control cedrus_controls[] = { .id = V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS, }, .codec = CEDRUS_CODEC_MPEG2, - .required = true, }, { .cfg = { .id = V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION, }, .codec = CEDRUS_CODEC_MPEG2, - .required = false, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, }, .codec = CEDRUS_CODEC_H264, - .required = true, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_SLICE_PARAMS, }, .codec = CEDRUS_CODEC_H264, - .required = true, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_SPS, }, .codec = CEDRUS_CODEC_H264, - .required = true, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_PPS, }, .codec = CEDRUS_CODEC_H264, - .required = true, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, }, .codec = CEDRUS_CODEC_H264, - .required = false, }, { .cfg = { .id = V4L2_CID_STATELESS_H264_PRED_WEIGHTS, }, .codec = CEDRUS_CODEC_H264, - .required = false, }, { .cfg = { @@ -92,7 +84,6 @@ static const struct cedrus_control cedrus_controls[] = { .def = V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED, }, .codec = CEDRUS_CODEC_H264, - .required = false, }, { .cfg = { @@ -101,7 +92,6 @@ static const struct cedrus_control cedrus_controls[] = { .def = V4L2_STATELESS_H264_START_CODE_NONE, }, .codec = CEDRUS_CODEC_H264, - .required = false, }, /* * We only expose supported profiles information, @@ -120,28 +110,24 @@ static const struct cedrus_control cedrus_controls[] = { BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), }, .codec = CEDRUS_CODEC_H264, - .required = false, }, { .cfg = { .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, }, .codec = CEDRUS_CODEC_H265, - .required = true, }, { .cfg = { .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, }, .codec = CEDRUS_CODEC_H265, - .required = true, }, { .cfg = { .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, }, .codec = CEDRUS_CODEC_H265, - .required = true, }, { .cfg = { @@ -150,7 +136,6 @@ static const struct cedrus_control cedrus_controls[] = { .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, }, .codec = CEDRUS_CODEC_H265, - .required = false, }, { .cfg = { @@ -159,14 +144,12 @@ static const struct cedrus_control cedrus_controls[] = { .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE, }, .codec = CEDRUS_CODEC_H265, - .required = false, }, { .cfg = { .id = V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER, }, .codec = CEDRUS_CODEC_VP8, - .required = true, }, }; @@ -227,12 +210,8 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, struct cedrus_ctx *ctx) static int cedrus_request_validate(struct media_request *req) { struct media_request_object *obj; - struct v4l2_ctrl_handler *parent_hdl, *hdl; struct cedrus_ctx *ctx = NULL; - struct v4l2_ctrl *ctrl_test; unsigned int count; - unsigned int i; - int ret = 0; list_for_each_entry(obj, &req->objects, list) { struct vb2_buffer *vb; @@ -259,34 +238,6 @@ static int cedrus_request_validate(struct media_request *req) return -EINVAL; } - parent_hdl = &ctx->hdl; - - hdl = v4l2_ctrl_request_hdl_find(req, parent_hdl); - if (!hdl) { - v4l2_info(&ctx->dev->v4l2_dev, "Missing codec control(s)\n"); - return -ENOENT; - } - - for (i = 0; i < CEDRUS_CONTROLS_COUNT; i++) { - if (cedrus_controls[i].codec != ctx->current_codec || - !cedrus_controls[i].required) - continue; - - ctrl_test = v4l2_ctrl_request_hdl_ctrl_find(hdl, - cedrus_controls[i].cfg.id); - if (!ctrl_test) { - v4l2_info(&ctx->dev->v4l2_dev, - "Missing required codec control\n"); - ret = -ENOENT; - break; - } - } - - v4l2_ctrl_request_hdl_put(hdl); - - if (ret) - return ret; - return vb2_request_validate(req); } diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index c96077aaef49..251a6a660351 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -56,7 +56,6 @@ enum cedrus_h264_pic_type { struct cedrus_control { struct v4l2_ctrl_config cfg; enum cedrus_codec codec; - unsigned char required:1; }; struct cedrus_h264_run { diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index a19c85c57fca..033a6935c26d 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -253,13 +253,14 @@ static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) } void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 csi_port_num, u8 *clk_settle_time, u8 *ths_settle_time) { struct tegra_csi *csi = csi_chan->csi; unsigned int cil_clk_mhz; unsigned int pix_clk_mhz; - int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + int clk_idx = (csi_port_num >> 1) + 1; cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; @@ -410,7 +411,7 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, unsigned int num_pads) { struct tegra_csi_channel *chan; - int ret = 0; + int ret = 0, i; chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) @@ -418,8 +419,21 @@ static int tegra_csi_channel_alloc(struct tegra_csi *csi, list_add_tail(&chan->list, &csi->csi_chans); chan->csi = csi; - chan->csi_port_num = port_num; - chan->numlanes = lanes; + /* + * Each CSI brick has maximum of 4 lanes. + * For lanes more than 4, use multiple of immediate CSI bricks as gang. + */ + if (lanes <= CSI_LANES_PER_BRICK) { + chan->numlanes = lanes; + chan->numgangports = 1; + } else { + chan->numlanes = CSI_LANES_PER_BRICK; + chan->numgangports = lanes / CSI_LANES_PER_BRICK; + } + + for (i = 0; i < chan->numgangports; i++) + chan->csi_port_nums[i] = port_num + i * CSI_PORTS_PER_BRICK; + chan->of_node = node; chan->numpads = num_pads; if (num_pads & 0x2) { @@ -500,7 +514,14 @@ static int tegra_csi_channels_alloc(struct tegra_csi *csi) } lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; - if (!lanes || ((lanes & (lanes - 1)) != 0)) { + /* + * Each CSI brick has maximum 4 data lanes. + * For lanes more than 4, validate lanes to be multiple of 4 + * so multiple of consecutive CSI bricks can be ganged up for + * streaming. + */ + if (!lanes || ((lanes & (lanes - 1)) != 0) || + (lanes > CSI_LANES_PER_BRICK && ((portno & 1) != 0))) { dev_err(csi->dev, "invalid data-lanes %d for %pOF\n", lanes, channel); ret = -EINVAL; @@ -544,7 +565,7 @@ static int tegra_csi_channel_init(struct tegra_csi_channel *chan) subdev->dev = csi->dev; if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", - chan->csi_port_num); + chan->csi_port_nums[0]); else snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", kbasename(chan->of_node->full_name)); @@ -596,7 +617,7 @@ static int tegra_csi_channels_init(struct tegra_csi *csi) if (ret) { dev_err(csi->dev, "failed to initialize channel-%d: %d\n", - chan->csi_port_num, ret); + chan->csi_port_nums[0], ret); return ret; } } diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index c65ff73b1cdc..386f7c664259 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -17,6 +17,10 @@ * CILB. */ #define CSI_PORTS_PER_BRICK 2 +#define CSI_LANES_PER_BRICK 4 + +/* Maximum 2 CSI x4 ports can be ganged up for streaming */ +#define GANG_PORTS_MAX 2 /* each CSI channel can have one sink and one source pads */ #define TEGRA_CSI_PADS_NUM 2 @@ -43,8 +47,10 @@ struct tegra_csi; * @numpads: number of pads. * @csi: Tegra CSI device structure * @of_node: csi device tree node - * @numlanes: number of lanes used per port/channel - * @csi_port_num: CSI channel port number + * @numgangports: number of immediate ports ganged up to meet the + * channel bus-width + * @numlanes: number of lanes used per port + * @csi_port_nums: CSI channel port numbers * @pg_mode: test pattern generator mode for channel * @format: active format of the channel * @framerate: active framerate for TPG @@ -60,8 +66,9 @@ struct tegra_csi_channel { unsigned int numpads; struct tegra_csi *csi; struct device_node *of_node; + u8 numgangports; unsigned int numlanes; - u8 csi_port_num; + u8 csi_port_nums[GANG_PORTS_MAX]; u8 pg_mode; struct v4l2_mbus_framefmt format; unsigned int framerate; @@ -150,6 +157,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; void tegra_csi_error_recover(struct v4l2_subdev *subdev); void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 csi_port_num, u8 *clk_settle_time, u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index ac066c030a4f..f10a041e3e6c 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -149,21 +149,22 @@ static u32 tegra_vi_read(struct tegra_vi_channel *chan, unsigned int addr) } /* Tegra210 VI_CSI registers accessors */ -static void vi_csi_write(struct tegra_vi_channel *chan, unsigned int addr, - u32 val) +static void vi_csi_write(struct tegra_vi_channel *chan, u8 portno, + unsigned int addr, u32 val) { void __iomem *vi_csi_base; - vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(chan->portno); + vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); writel_relaxed(val, vi_csi_base + addr); } -static u32 vi_csi_read(struct tegra_vi_channel *chan, unsigned int addr) +static u32 vi_csi_read(struct tegra_vi_channel *chan, u8 portno, + unsigned int addr) { void __iomem *vi_csi_base; - vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(chan->portno); + vi_csi_base = chan->vi->iomem + TEGRA210_VI_CSI_BASE(portno); return readl_relaxed(vi_csi_base + addr); } @@ -171,27 +172,52 @@ static u32 vi_csi_read(struct tegra_vi_channel *chan, unsigned int addr) /* * Tegra210 VI channel capture operations */ -static int tegra_channel_capture_setup(struct tegra_vi_channel *chan) +static int tegra_channel_capture_setup(struct tegra_vi_channel *chan, + u8 portno) { u32 height = chan->format.height; u32 width = chan->format.width; u32 format = chan->fmtinfo->img_fmt; u32 data_type = chan->fmtinfo->img_dt; u32 word_count = (width * chan->fmtinfo->bit_width) / 8; + u32 bypass_pixel_transform = BIT(BYPASS_PXL_TRANSFORM_OFFSET); - vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, 0xffffffff); - vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_DEF, - ((chan->pg_mode ? 0 : 1) << BYPASS_PXL_TRANSFORM_OFFSET) | + /* + * VI Pixel transformation unit converts source pixels data format + * into selected destination pixel format and aligns properly while + * interfacing with memory packer. + * This pixel transformation should be enabled for YUV and RGB + * formats and should be bypassed for RAW formats as RAW formats + * only support direct to memory. + */ + if (chan->pg_mode || data_type == TEGRA_IMAGE_DT_YUV422_8 || + data_type == TEGRA_IMAGE_DT_RGB888) + bypass_pixel_transform = 0; + + /* + * For x8 source streaming, the source image is split onto two x4 ports + * with left half to first x4 port and right half to second x4 port. + * So, use split width and corresponding word count for each x4 port. + */ + if (chan->numgangports > 1) { + width = width >> 1; + word_count = (width * chan->fmtinfo->bit_width) / 8; + } + + vi_csi_write(chan, portno, TEGRA_VI_CSI_ERROR_STATUS, 0xffffffff); + vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_DEF, + bypass_pixel_transform | (format << IMAGE_DEF_FORMAT_OFFSET) | IMAGE_DEF_DEST_MEM); - vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_DT, data_type); - vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE_WC, word_count); - vi_csi_write(chan, TEGRA_VI_CSI_IMAGE_SIZE, + vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_DT, data_type); + vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_SIZE_WC, word_count); + vi_csi_write(chan, portno, TEGRA_VI_CSI_IMAGE_SIZE, (height << IMAGE_SIZE_HEIGHT_OFFSET) | width); return 0; } -static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan) +static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan, + u8 portno) { /* disable clock gating to enable continuous clock */ tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, 0); @@ -199,15 +225,16 @@ static void tegra_channel_vi_soft_reset(struct tegra_vi_channel *chan) * Soft reset memory client interface, pixel format logic, sensor * control logic, and a shadow copy logic to bring VI to clean state. */ - vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0xf); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SW_RESET, 0xf); usleep_range(100, 200); - vi_csi_write(chan, TEGRA_VI_CSI_SW_RESET, 0x0); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SW_RESET, 0x0); /* enable back VI clock gating */ tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN); } -static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) +static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan, + u8 portno) { struct v4l2_subdev *subdev; u32 val; @@ -219,9 +246,9 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) * events which can cause CSI and VI hardware hang. * This helps to have a clean capture for next frame. */ - val = vi_csi_read(chan, TEGRA_VI_CSI_ERROR_STATUS); + val = vi_csi_read(chan, portno, TEGRA_VI_CSI_ERROR_STATUS); dev_dbg(&chan->video.dev, "TEGRA_VI_CSI_ERROR_STATUS 0x%08x\n", val); - vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, val); + vi_csi_write(chan, portno, TEGRA_VI_CSI_ERROR_STATUS, val); val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR); dev_dbg(&chan->video.dev, @@ -229,8 +256,8 @@ static void tegra_channel_capture_error_recover(struct tegra_vi_channel *chan) tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val); /* recover VI by issuing software reset and re-setup for capture */ - tegra_channel_vi_soft_reset(chan); - tegra_channel_capture_setup(chan); + tegra_channel_vi_soft_reset(chan, portno); + tegra_channel_capture_setup(chan, portno); /* recover CSI block */ subdev = tegra_channel_get_remote_csi_subdev(chan); @@ -269,67 +296,114 @@ static void release_buffer(struct tegra_vi_channel *chan, vb2_buffer_done(&vb->vb2_buf, state); } -static int tegra_channel_capture_frame(struct tegra_vi_channel *chan, - struct tegra_channel_buffer *buf) +static void tegra_channel_vi_buffer_setup(struct tegra_vi_channel *chan, + u8 portno, u32 buf_offset, + struct tegra_channel_buffer *buf) { - u32 thresh, value, frame_start, mw_ack_done; - int bytes_per_line = chan->format.bytesperline; - int err; + int bytesperline = chan->format.bytesperline; + u32 sizeimage = chan->format.sizeimage; /* program buffer address by using surface 0 */ - vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB, - (u64)buf->addr >> 32); - vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, buf->addr); - vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_OFFSET_MSB, + ((u64)buf->addr + buf_offset) >> 32); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_OFFSET_LSB, + buf->addr + buf_offset); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE0_STRIDE, bytesperline); + if (chan->fmtinfo->fourcc != V4L2_PIX_FMT_NV16) + return; /* - * Tegra VI block interacts with host1x syncpt for synchronizing - * programmed condition of capture state and hardware operation. - * Frame start and Memory write acknowledge syncpts has their own - * FIFO of depth 2. - * - * Syncpoint trigger conditions set through VI_INCR_SYNCPT register - * are added to HW syncpt FIFO and when the HW triggers, syncpt - * condition is removed from the FIFO and counter at syncpoint index - * will be incremented by the hardware and software can wait for - * counter to reach threshold to synchronize capturing frame with the - * hardware capture events. + * Program surface 1 for UV plane with offset sizeimage from Y plane. */ + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_OFFSET_MSB, + (((u64)buf->addr + sizeimage / 2) + buf_offset) >> 32); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_OFFSET_LSB, + buf->addr + sizeimage / 2 + buf_offset); + vi_csi_write(chan, portno, TEGRA_VI_CSI_SURFACE1_STRIDE, bytesperline); +} - /* increase channel syncpoint threshold for FRAME_START */ - thresh = host1x_syncpt_incr_max(chan->frame_start_sp, 1); +static int tegra_channel_capture_frame(struct tegra_vi_channel *chan, + struct tegra_channel_buffer *buf) +{ + u32 thresh, value, frame_start, mw_ack_done; + u32 fs_thresh[GANG_PORTS_MAX]; + u8 *portnos = chan->portnos; + int gang_bpl = (chan->format.width >> 1) * chan->fmtinfo->bpp; + u32 buf_offset; + bool capture_timedout = false; + int err, i; + + for (i = 0; i < chan->numgangports; i++) { + /* + * Align buffers side-by-side for all consecutive x4 ports + * in gang ports using bytes per line based on source split + * width. + */ + buf_offset = i * roundup(gang_bpl, SURFACE_ALIGN_BYTES); + tegra_channel_vi_buffer_setup(chan, portnos[i], buf_offset, + buf); - /* Program FRAME_START trigger condition syncpt request */ - frame_start = VI_CSI_PP_FRAME_START(chan->portno); - value = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) | - host1x_syncpt_id(chan->frame_start_sp); - tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); + /* + * Tegra VI block interacts with host1x syncpt to synchronize + * programmed condition and hardware operation for capture. + * Frame start and Memory write acknowledge syncpts has their + * own FIFO of depth 2. + * + * Syncpoint trigger conditions set through VI_INCR_SYNCPT + * register are added to HW syncpt FIFO and when HW triggers, + * syncpt condition is removed from the FIFO and counter at + * syncpoint index will be incremented by the hardware and + * software can wait for counter to reach threshold to + * synchronize capturing frame with hardware capture events. + */ - /* increase channel syncpoint threshold for MW_ACK_DONE */ - buf->mw_ack_sp_thresh = host1x_syncpt_incr_max(chan->mw_ack_sp, 1); + /* increase channel syncpoint threshold for FRAME_START */ + thresh = host1x_syncpt_incr_max(chan->frame_start_sp[i], 1); + fs_thresh[i] = thresh; + + /* Program FRAME_START trigger condition syncpt request */ + frame_start = VI_CSI_PP_FRAME_START(portnos[i]); + value = VI_CFG_VI_INCR_SYNCPT_COND(frame_start) | + host1x_syncpt_id(chan->frame_start_sp[i]); + tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); + + /* increase channel syncpoint threshold for MW_ACK_DONE */ + thresh = host1x_syncpt_incr_max(chan->mw_ack_sp[i], 1); + buf->mw_ack_sp_thresh[i] = thresh; + + /* Program MW_ACK_DONE trigger condition syncpt request */ + mw_ack_done = VI_CSI_MW_ACK_DONE(portnos[i]); + value = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) | + host1x_syncpt_id(chan->mw_ack_sp[i]); + tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); + } - /* Program MW_ACK_DONE trigger condition syncpt request */ - mw_ack_done = VI_CSI_MW_ACK_DONE(chan->portno); - value = VI_CFG_VI_INCR_SYNCPT_COND(mw_ack_done) | - host1x_syncpt_id(chan->mw_ack_sp); - tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT, value); + /* enable single shot capture after all ganged ports are ready */ + for (i = 0; i < chan->numgangports; i++) + vi_csi_write(chan, portnos[i], TEGRA_VI_CSI_SINGLE_SHOT, + SINGLE_SHOT_CAPTURE); - /* enable single shot capture */ - vi_csi_write(chan, TEGRA_VI_CSI_SINGLE_SHOT, SINGLE_SHOT_CAPTURE); + for (i = 0; i < chan->numgangports; i++) { + /* + * Wait for syncpt counter to reach frame start event threshold + */ + err = host1x_syncpt_wait(chan->frame_start_sp[i], fs_thresh[i], + TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); + if (err) { + capture_timedout = true; + /* increment syncpoint counter for timedout events */ + host1x_syncpt_incr(chan->frame_start_sp[i]); + spin_lock(&chan->sp_incr_lock[i]); + host1x_syncpt_incr(chan->mw_ack_sp[i]); + spin_unlock(&chan->sp_incr_lock[i]); + /* clear errors and recover */ + tegra_channel_capture_error_recover(chan, portnos[i]); + } + } - /* wait for syncpt counter to reach frame start event threshold */ - err = host1x_syncpt_wait(chan->frame_start_sp, thresh, - TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); - if (err) { + if (capture_timedout) { dev_err_ratelimited(&chan->video.dev, "frame start syncpt timeout: %d\n", err); - /* increment syncpoint counter for timedout events */ - host1x_syncpt_incr(chan->frame_start_sp); - spin_lock(&chan->sp_incr_lock); - host1x_syncpt_incr(chan->mw_ack_sp); - spin_unlock(&chan->sp_incr_lock); - /* clear errors and recover */ - tegra_channel_capture_error_recover(chan); release_buffer(chan, buf, VB2_BUF_STATE_ERROR); return err; } @@ -350,21 +424,29 @@ static void tegra_channel_capture_done(struct tegra_vi_channel *chan, { enum vb2_buffer_state state = VB2_BUF_STATE_DONE; u32 value; - int ret; + bool capture_timedout = false; + int ret, i; - /* wait for syncpt counter to reach MW_ACK_DONE event threshold */ - ret = host1x_syncpt_wait(chan->mw_ack_sp, buf->mw_ack_sp_thresh, - TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); - if (ret) { - dev_err_ratelimited(&chan->video.dev, - "MW_ACK_DONE syncpt timeout: %d\n", ret); - state = VB2_BUF_STATE_ERROR; - /* increment syncpoint counter for timedout event */ - spin_lock(&chan->sp_incr_lock); - host1x_syncpt_incr(chan->mw_ack_sp); - spin_unlock(&chan->sp_incr_lock); + for (i = 0; i < chan->numgangports; i++) { + /* + * Wait for syncpt counter to reach MW_ACK_DONE event threshold + */ + ret = host1x_syncpt_wait(chan->mw_ack_sp[i], + buf->mw_ack_sp_thresh[i], + TEGRA_VI_SYNCPT_WAIT_TIMEOUT, &value); + if (ret) { + capture_timedout = true; + state = VB2_BUF_STATE_ERROR; + /* increment syncpoint counter for timedout event */ + spin_lock(&chan->sp_incr_lock[i]); + host1x_syncpt_incr(chan->mw_ack_sp[i]); + spin_unlock(&chan->sp_incr_lock[i]); + } } + if (capture_timedout) + dev_err_ratelimited(&chan->video.dev, + "MW_ACK_DONE syncpt timeout: %d\n", ret); release_buffer(chan, buf, state); } @@ -372,6 +454,7 @@ static int chan_capture_kthread_start(void *data) { struct tegra_vi_channel *chan = data; struct tegra_channel_buffer *buf; + unsigned int retries = 0; int err = 0; while (1) { @@ -401,8 +484,15 @@ static int chan_capture_kthread_start(void *data) spin_unlock(&chan->start_lock); err = tegra_channel_capture_frame(chan, buf); - if (err) + if (!err) { + retries = 0; + continue; + } + + if (retries++ > chan->syncpt_timeout_retry) vb2_queue_error(&chan->queue); + else + err = 0; } return 0; @@ -437,14 +527,12 @@ static int tegra210_vi_start_streaming(struct vb2_queue *vq, u32 count) struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); struct media_pipeline *pipe = &chan->video.pipe; u32 val; - int ret; + u8 *portnos = chan->portnos; + int ret, i; tegra_vi_write(chan, TEGRA_VI_CFG_CG_CTRL, VI_CG_2ND_LEVEL_EN); - /* clear errors */ - val = vi_csi_read(chan, TEGRA_VI_CSI_ERROR_STATUS); - vi_csi_write(chan, TEGRA_VI_CSI_ERROR_STATUS, val); - + /* clear syncpt errors */ val = tegra_vi_read(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR); tegra_vi_write(chan, TEGRA_VI_CFG_VI_INCR_SYNCPT_ERROR, val); @@ -463,7 +551,14 @@ static int tegra210_vi_start_streaming(struct vb2_queue *vq, u32 count) if (ret < 0) goto error_pipeline_start; - tegra_channel_capture_setup(chan); + /* clear csi errors and do capture setup for all ports in gang mode */ + for (i = 0; i < chan->numgangports; i++) { + val = vi_csi_read(chan, portnos[i], TEGRA_VI_CSI_ERROR_STATUS); + vi_csi_write(chan, portnos[i], TEGRA_VI_CSI_ERROR_STATUS, val); + + tegra_channel_capture_setup(chan, portnos[i]); + } + ret = tegra_channel_set_stream(chan, true); if (ret < 0) goto error_set_stream; @@ -606,19 +701,19 @@ static const struct tegra_video_format tegra210_video_formats[] = { TEGRA210_VIDEO_FMT(RAW12, 12, SGBRG12_1X12, 2, T_R16_I, SGBRG12), TEGRA210_VIDEO_FMT(RAW12, 12, SBGGR12_1X12, 2, T_R16_I, SBGGR12), /* RGB888 */ - TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X24, 4, T_A8R8G8B8, RGB24), + TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X24, 4, T_A8R8G8B8, XBGR32), TEGRA210_VIDEO_FMT(RGB888, 24, RGB888_1X32_PADHI, 4, T_A8B8G8R8, - XBGR32), + RGBX32), /* YUV422 */ - TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 2, T_U8_Y8__V8_Y8, UYVY), - TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 2, T_V8_Y8__U8_Y8, VYUY), - TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 2, T_Y8_U8__Y8_V8, YUYV), - TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 2, T_Y8_V8__Y8_U8, YVYU), + TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 2, T_U8_Y8__V8_Y8, YVYU), + TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 2, T_V8_Y8__U8_Y8, YUYV), + TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 2, T_Y8_U8__Y8_V8, VYUY), + TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 2, T_Y8_V8__Y8_U8, UYVY), TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 1, T_Y8__V8U8_N422, NV16), - TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 2, T_U8_Y8__V8_Y8, UYVY), - TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, T_V8_Y8__U8_Y8, VYUY), - TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, T_Y8_U8__Y8_V8, YUYV), - TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, T_Y8_V8__Y8_U8, YVYU), + TEGRA210_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 2, T_U8_Y8__V8_Y8, YVYU), + TEGRA210_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, T_V8_Y8__U8_Y8, YUYV), + TEGRA210_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, T_Y8_U8__Y8_V8, VYUY), + TEGRA210_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, T_Y8_V8__Y8_U8, UYVY), }; /* Tegra210 VI operations */ @@ -717,10 +812,10 @@ static void tpg_write(struct tegra_csi *csi, u8 portno, unsigned int addr, /* * Tegra210 CSI operations */ -static void tegra210_csi_error_recover(struct tegra_csi_channel *csi_chan) +static void tegra210_csi_port_recover(struct tegra_csi_channel *csi_chan, + u8 portno) { struct tegra_csi *csi = csi_chan->csi; - unsigned int portno = csi_chan->csi_port_num; u32 val; /* @@ -769,16 +864,26 @@ static void tegra210_csi_error_recover(struct tegra_csi_channel *csi_chan) } } -static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) +static void tegra210_csi_error_recover(struct tegra_csi_channel *csi_chan) +{ + u8 *portnos = csi_chan->csi_port_nums; + int i; + + for (i = 0; i < csi_chan->numgangports; i++) + tegra210_csi_port_recover(csi_chan, portnos[i]); +} + +static int +tegra210_csi_port_start_streaming(struct tegra_csi_channel *csi_chan, + u8 portno) { struct tegra_csi *csi = csi_chan->csi; - unsigned int portno = csi_chan->csi_port_num; u8 clk_settle_time = 0; u8 ths_settle_time = 10; u32 val; if (!csi_chan->pg_mode) - tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + tegra_csi_calc_settle_time(csi_chan, portno, &clk_settle_time, &ths_settle_time); csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); @@ -877,10 +982,10 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) return 0; } -static void tegra210_csi_stop_streaming(struct tegra_csi_channel *csi_chan) +static void +tegra210_csi_port_stop_streaming(struct tegra_csi_channel *csi_chan, u8 portno) { struct tegra_csi *csi = csi_chan->csi; - unsigned int portno = csi_chan->csi_port_num; u32 val; val = pp_read(csi, portno, TEGRA_CSI_PIXEL_PARSER_STATUS); @@ -918,6 +1023,35 @@ static void tegra210_csi_stop_streaming(struct tegra_csi_channel *csi_chan) } } +static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) +{ + u8 *portnos = csi_chan->csi_port_nums; + int ret, i; + + for (i = 0; i < csi_chan->numgangports; i++) { + ret = tegra210_csi_port_start_streaming(csi_chan, portnos[i]); + if (ret) + goto stream_start_fail; + } + + return 0; + +stream_start_fail: + for (i = i - 1; i >= 0; i--) + tegra210_csi_port_stop_streaming(csi_chan, portnos[i]); + + return ret; +} + +static void tegra210_csi_stop_streaming(struct tegra_csi_channel *csi_chan) +{ + u8 *portnos = csi_chan->csi_port_nums; + int i; + + for (i = 0; i < csi_chan->numgangports; i++) + tegra210_csi_port_stop_streaming(csi_chan, portnos[i]); +} + /* * Tegra210 CSI TPG frame rate table with horizontal and vertical * blanking intervals for corresponding format and resolution. diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 560d8b368124..7a09061cda57 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -18,6 +18,7 @@ #include <linux/pm_runtime.h> #include <linux/slab.h> +#include <media/v4l2-dv-timings.h> #include <media/v4l2-event.h> #include <media/v4l2-fh.h> #include <media/v4l2-fwnode.h> @@ -29,7 +30,6 @@ #include "vi.h" #include "video.h" -#define SURFACE_ALIGN_BYTES 64 #define MAX_CID_CONTROLS 1 static const struct tegra_video_format tegra_default_format = { @@ -484,6 +484,8 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, pix->bytesperline = clamp(bpl, min_bpl, max_bpl); pix->sizeimage = pix->bytesperline * pix->height; + if (pix->pixelformat == V4L2_PIX_FMT_NV16) + pix->sizeimage *= 2; } static int __tegra_channel_try_format(struct tegra_vi_channel *chan, @@ -533,11 +535,18 @@ static int __tegra_channel_try_format(struct tegra_vi_channel *chan, fse.code = fmtinfo->code; ret = v4l2_subdev_call(subdev, pad, enum_frame_size, pad_cfg, &fse); if (ret) { - ret = v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel); - if (ret) - return -EINVAL; - pad_cfg->try_crop.width = sdsel.r.width; - pad_cfg->try_crop.height = sdsel.r.height; + if (!v4l2_subdev_has_op(subdev, pad, get_selection)) { + pad_cfg->try_crop.width = 0; + pad_cfg->try_crop.height = 0; + } else { + ret = v4l2_subdev_call(subdev, pad, get_selection, + NULL, &sdsel); + if (ret) + return -EINVAL; + + pad_cfg->try_crop.width = sdsel.r.width; + pad_cfg->try_crop.height = sdsel.r.height; + } } else { pad_cfg->try_crop.width = fse.max_width; pad_cfg->try_crop.height = fse.max_height; @@ -563,6 +572,14 @@ static int tegra_channel_try_format(struct file *file, void *fh, return __tegra_channel_try_format(chan, &format->fmt.pix); } +static void tegra_channel_update_gangports(struct tegra_vi_channel *chan) +{ + if (chan->format.width <= 1920) + chan->numgangports = 1; + else + chan->numgangports = chan->totalports; +} + static int tegra_channel_set_format(struct file *file, void *fh, struct v4l2_format *format) { @@ -596,6 +613,7 @@ static int tegra_channel_set_format(struct file *file, void *fh, chan->format = *pix; chan->fmtinfo = fmtinfo; + tegra_channel_update_gangports(chan); return 0; } @@ -628,10 +646,23 @@ static int tegra_channel_set_subdev_active_fmt(struct tegra_vi_channel *chan) chan->format.sizeimage = chan->format.bytesperline * chan->format.height; tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + tegra_channel_update_gangports(chan); return 0; } +static int +tegra_channel_subscribe_event(struct v4l2_fh *fh, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_SOURCE_CHANGE: + return v4l2_event_subscribe(fh, sub, 4, NULL); + } + + return v4l2_ctrl_subscribe_event(fh, sub); +} + static int tegra_channel_g_selection(struct file *file, void *priv, struct v4l2_selection *sel) { @@ -711,6 +742,133 @@ static int tegra_channel_s_selection(struct file *file, void *fh, return ret; } +static int tegra_channel_g_edid(struct file *file, void *fh, + struct v4l2_edid *edid) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, get_edid)) + return -ENOTTY; + + return v4l2_subdev_call(subdev, pad, get_edid, edid); +} + +static int tegra_channel_s_edid(struct file *file, void *fh, + struct v4l2_edid *edid) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, set_edid)) + return -ENOTTY; + + return v4l2_subdev_call(subdev, pad, set_edid, edid); +} + +static int tegra_channel_g_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, video, g_dv_timings)) + return -ENOTTY; + + return v4l2_device_call_until_err(chan->video.v4l2_dev, 0, + video, g_dv_timings, timings); +} + +static int tegra_channel_s_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + struct v4l2_bt_timings *bt = &timings->bt; + struct v4l2_dv_timings curr_timings; + int ret; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, video, s_dv_timings)) + return -ENOTTY; + + ret = tegra_channel_g_dv_timings(file, fh, &curr_timings); + if (ret) + return ret; + + if (v4l2_match_dv_timings(timings, &curr_timings, 0, false)) + return 0; + + if (vb2_is_busy(&chan->queue)) + return -EBUSY; + + ret = v4l2_device_call_until_err(chan->video.v4l2_dev, 0, + video, s_dv_timings, timings); + if (ret) + return ret; + + chan->format.width = bt->width; + chan->format.height = bt->height; + chan->format.bytesperline = bt->width * chan->fmtinfo->bpp; + chan->format.sizeimage = chan->format.bytesperline * bt->height; + tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); + tegra_channel_update_gangports(chan); + + return 0; +} + +static int tegra_channel_query_dv_timings(struct file *file, void *fh, + struct v4l2_dv_timings *timings) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, video, query_dv_timings)) + return -ENOTTY; + + return v4l2_device_call_until_err(chan->video.v4l2_dev, 0, + video, query_dv_timings, timings); +} + +static int tegra_channel_enum_dv_timings(struct file *file, void *fh, + struct v4l2_enum_dv_timings *timings) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, enum_dv_timings)) + return -ENOTTY; + + return v4l2_subdev_call(subdev, pad, enum_dv_timings, timings); +} + +static int tegra_channel_dv_timings_cap(struct file *file, void *fh, + struct v4l2_dv_timings_cap *cap) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + struct v4l2_subdev *subdev; + + subdev = tegra_channel_get_remote_source_subdev(chan); + if (!v4l2_subdev_has_op(subdev, pad, dv_timings_cap)) + return -ENOTTY; + + return v4l2_subdev_call(subdev, pad, dv_timings_cap, cap); +} + +static int tegra_channel_log_status(struct file *file, void *fh) +{ + struct tegra_vi_channel *chan = video_drvdata(file); + + v4l2_device_call_all(chan->video.v4l2_dev, 0, core, log_status); + + return 0; +} + static int tegra_channel_enum_input(struct file *file, void *fh, struct v4l2_input *inp) { @@ -723,6 +881,8 @@ static int tegra_channel_enum_input(struct file *file, void *fh, inp->type = V4L2_INPUT_TYPE_CAMERA; subdev = tegra_channel_get_remote_source_subdev(chan); strscpy(inp->name, subdev->name, sizeof(inp->name)); + if (v4l2_subdev_has_op(subdev, pad, dv_timings_cap)) + inp->capabilities = V4L2_IN_CAP_DV_TIMINGS; return 0; } @@ -766,10 +926,18 @@ static const struct v4l2_ioctl_ops tegra_channel_ioctl_ops = { .vidioc_expbuf = vb2_ioctl_expbuf, .vidioc_streamon = vb2_ioctl_streamon, .vidioc_streamoff = vb2_ioctl_streamoff, - .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_subscribe_event = tegra_channel_subscribe_event, .vidioc_unsubscribe_event = v4l2_event_unsubscribe, .vidioc_g_selection = tegra_channel_g_selection, .vidioc_s_selection = tegra_channel_s_selection, + .vidioc_g_edid = tegra_channel_g_edid, + .vidioc_s_edid = tegra_channel_s_edid, + .vidioc_g_dv_timings = tegra_channel_g_dv_timings, + .vidioc_s_dv_timings = tegra_channel_s_dv_timings, + .vidioc_query_dv_timings = tegra_channel_query_dv_timings, + .vidioc_enum_dv_timings = tegra_channel_enum_dv_timings, + .vidioc_dv_timings_cap = tegra_channel_dv_timings_cap, + .vidioc_log_status = tegra_channel_log_status, }; /* @@ -788,7 +956,6 @@ static const struct v4l2_file_operations tegra_channel_fops = { /* * V4L2 control operations */ -#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) static int vi_s_ctrl(struct v4l2_ctrl *ctrl) { struct tegra_vi_channel *chan = container_of(ctrl->handler, @@ -800,6 +967,9 @@ static int vi_s_ctrl(struct v4l2_ctrl *ctrl) /* pattern change takes effect on next stream */ chan->pg_mode = ctrl->val + 1; break; + case V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY: + chan->syncpt_timeout_retry = ctrl->val; + break; default: return -EINVAL; } @@ -811,10 +981,22 @@ static const struct v4l2_ctrl_ops vi_ctrl_ops = { .s_ctrl = vi_s_ctrl, }; +#if IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG) static const char *const vi_pattern_strings[] = { "Black/White Direct Mode", "Color Patch Mode", }; +#else +static const struct v4l2_ctrl_config syncpt_timeout_ctrl = { + .ops = &vi_ctrl_ops, + .id = V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY, + .name = "Syncpt timeout retry", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 10000, + .step = 1, + .def = 5, +}; #endif static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) @@ -836,6 +1018,16 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) #else struct v4l2_subdev *subdev; + /* custom control */ + v4l2_ctrl_new_custom(&chan->ctrl_handler, &syncpt_timeout_ctrl, NULL); + if (chan->ctrl_handler.error) { + dev_err(chan->vi->dev, "failed to add %s ctrl handler: %d\n", + syncpt_timeout_ctrl.name, + chan->ctrl_handler.error); + v4l2_ctrl_handler_free(&chan->ctrl_handler); + return chan->ctrl_handler.error; + } + subdev = tegra_channel_get_remote_source_subdev(chan); if (!subdev) return -ENODEV; @@ -934,12 +1126,21 @@ static int vi_fmts_bitmap_init(struct tegra_vi_channel *chan) return 0; } +static void tegra_channel_host1x_syncpts_free(struct tegra_vi_channel *chan) +{ + int i; + + for (i = 0; i < chan->numgangports; i++) { + host1x_syncpt_free(chan->mw_ack_sp[i]); + host1x_syncpt_free(chan->frame_start_sp[i]); + } +} + static void tegra_channel_cleanup(struct tegra_vi_channel *chan) { v4l2_ctrl_handler_free(&chan->ctrl_handler); media_entity_cleanup(&chan->video.entity); - host1x_syncpt_free(chan->mw_ack_sp); - host1x_syncpt_free(chan->frame_start_sp); + tegra_channel_host1x_syncpts_free(chan); mutex_destroy(&chan->video_lock); } @@ -957,11 +1158,46 @@ void tegra_channels_cleanup(struct tegra_vi *vi) } } +static int tegra_channel_host1x_syncpt_init(struct tegra_vi_channel *chan) +{ + struct tegra_vi *vi = chan->vi; + unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; + struct host1x_syncpt *fs_sp; + struct host1x_syncpt *mw_sp; + int ret, i; + + for (i = 0; i < chan->numgangports; i++) { + fs_sp = host1x_syncpt_request(&vi->client, flags); + if (!fs_sp) { + dev_err(vi->dev, "failed to request frame start syncpoint\n"); + ret = -ENOMEM; + goto free_syncpts; + } + + mw_sp = host1x_syncpt_request(&vi->client, flags); + if (!mw_sp) { + dev_err(vi->dev, "failed to request memory ack syncpoint\n"); + host1x_syncpt_free(fs_sp); + ret = -ENOMEM; + goto free_syncpts; + } + + chan->frame_start_sp[i] = fs_sp; + chan->mw_ack_sp[i] = mw_sp; + spin_lock_init(&chan->sp_incr_lock[i]); + } + + return 0; + +free_syncpts: + tegra_channel_host1x_syncpts_free(chan); + return ret; +} + static int tegra_channel_init(struct tegra_vi_channel *chan) { struct tegra_vi *vi = chan->vi; struct tegra_video_device *vid = dev_get_drvdata(vi->client.host); - unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; int ret; mutex_init(&chan->video_lock); @@ -969,7 +1205,6 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) INIT_LIST_HEAD(&chan->done); spin_lock_init(&chan->start_lock); spin_lock_init(&chan->done_lock); - spin_lock_init(&chan->sp_incr_lock); init_waitqueue_head(&chan->start_wait); init_waitqueue_head(&chan->done_wait); @@ -984,18 +1219,9 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) chan->format.sizeimage = chan->format.bytesperline * TEGRA_DEF_HEIGHT; tegra_channel_fmt_align(chan, &chan->format, chan->fmtinfo->bpp); - chan->frame_start_sp = host1x_syncpt_request(&vi->client, flags); - if (!chan->frame_start_sp) { - dev_err(vi->dev, "failed to request frame start syncpoint\n"); - return -ENOMEM; - } - - chan->mw_ack_sp = host1x_syncpt_request(&vi->client, flags); - if (!chan->mw_ack_sp) { - dev_err(vi->dev, "failed to request memory ack syncpoint\n"); - ret = -ENOMEM; - goto free_fs_syncpt; - } + ret = tegra_channel_host1x_syncpt_init(chan); + if (ret) + return ret; /* initialize the media entity */ chan->pad.flags = MEDIA_PAD_FL_SINK; @@ -1003,7 +1229,7 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) if (ret < 0) { dev_err(vi->dev, "failed to initialize media entity: %d\n", ret); - goto free_mw_ack_syncpt; + goto free_syncpts; } ret = v4l2_ctrl_handler_init(&chan->ctrl_handler, MAX_CID_CONTROLS); @@ -1019,7 +1245,7 @@ static int tegra_channel_init(struct tegra_vi_channel *chan) chan->video.release = video_device_release_empty; chan->video.queue = &chan->queue; snprintf(chan->video.name, sizeof(chan->video.name), "%s-%s-%u", - dev_name(vi->dev), "output", chan->portno); + dev_name(vi->dev), "output", chan->portnos[0]); chan->video.vfl_type = VFL_TYPE_VIDEO; chan->video.vfl_dir = VFL_DIR_RX; chan->video.ioctl_ops = &tegra_channel_ioctl_ops; @@ -1055,17 +1281,16 @@ free_v4l2_ctrl_hdl: v4l2_ctrl_handler_free(&chan->ctrl_handler); cleanup_media: media_entity_cleanup(&chan->video.entity); -free_mw_ack_syncpt: - host1x_syncpt_free(chan->mw_ack_sp); -free_fs_syncpt: - host1x_syncpt_free(chan->frame_start_sp); +free_syncpts: + tegra_channel_host1x_syncpts_free(chan); return ret; } static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, - struct device_node *node) + struct device_node *node, unsigned int lanes) { struct tegra_vi_channel *chan; + unsigned int i; /* * Do not use devm_kzalloc as memory is freed immediately @@ -1078,7 +1303,20 @@ static int tegra_vi_channel_alloc(struct tegra_vi *vi, unsigned int port_num, return -ENOMEM; chan->vi = vi; - chan->portno = port_num; + chan->portnos[0] = port_num; + /* + * For data lanes more than maximum csi lanes per brick, multiple of + * x4 ports are used simultaneously for capture. + */ + if (lanes <= CSI_LANES_PER_BRICK) + chan->totalports = 1; + else + chan->totalports = lanes / CSI_LANES_PER_BRICK; + chan->numgangports = chan->totalports; + + for (i = 1; i < chan->totalports; i++) + chan->portnos[i] = chan->portnos[0] + i * CSI_PORTS_PER_BRICK; + chan->of_node = node; list_add_tail(&chan->list, &vi->vi_chans); @@ -1092,7 +1330,8 @@ static int tegra_vi_tpg_channels_alloc(struct tegra_vi *vi) int ret; for (port_num = 0; port_num < nchannels; port_num++) { - ret = tegra_vi_channel_alloc(vi, port_num, vi->dev->of_node); + ret = tegra_vi_channel_alloc(vi, port_num, + vi->dev->of_node, 2); if (ret < 0) return ret; } @@ -1107,6 +1346,9 @@ static int tegra_vi_channels_alloc(struct tegra_vi *vi) struct device_node *ports; struct device_node *port; unsigned int port_num; + struct device_node *parent; + struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 }; + unsigned int lanes; int ret = 0; ports = of_get_child_by_name(node, "ports"); @@ -1133,8 +1375,21 @@ static int tegra_vi_channels_alloc(struct tegra_vi *vi) if (!ep) continue; + parent = of_graph_get_remote_port_parent(ep); + of_node_put(ep); + if (!parent) + continue; + + ep = of_graph_get_endpoint_by_regs(parent, 0, 0); + of_node_put(parent); + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), + &v4l2_ep); of_node_put(ep); - ret = tegra_vi_channel_alloc(vi, port_num, port); + if (ret) + continue; + + lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; + ret = tegra_vi_channel_alloc(vi, port_num, port, lanes); if (ret < 0) { of_node_put(port); goto cleanup; @@ -1156,7 +1411,7 @@ static int tegra_vi_channels_init(struct tegra_vi *vi) if (ret < 0) { dev_err(vi->dev, "failed to initialize channel-%d: %d\n", - chan->portno, ret); + chan->portnos[0], ret); goto cleanup; } } @@ -1478,6 +1733,9 @@ static int tegra_vi_graph_notify_complete(struct v4l2_async_notifier *notifier) v4l2_set_subdev_hostdata(subdev, chan); + subdev = tegra_channel_get_remote_source_subdev(chan); + v4l2_set_subdev_hostdata(subdev, chan); + return 0; unregister_video: @@ -1530,7 +1788,7 @@ static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, struct tegra_vi *vi = chan->vi; struct fwnode_handle *ep = NULL; struct fwnode_handle *remote = NULL; - struct v4l2_async_subdev *asd; + struct tegra_vi_graph_entity *tvge; struct device_node *node = NULL; int ret; @@ -1554,10 +1812,10 @@ static int tegra_vi_graph_parse_one(struct tegra_vi_channel *chan, continue; } - asd = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, - remote, sizeof(struct tegra_vi_graph_entity)); - if (IS_ERR(asd)) { - ret = PTR_ERR(asd); + tvge = v4l2_async_notifier_add_fwnode_subdev(&chan->notifier, + remote, struct tegra_vi_graph_entity); + if (IS_ERR(tvge)) { + ret = PTR_ERR(tvge); dev_err(vi->dev, "failed to add subdev to notifier: %d\n", ret); fwnode_handle_put(remote); @@ -1600,7 +1858,8 @@ static int tegra_vi_graph_init(struct tegra_vi *vi) * next channels. */ list_for_each_entry(chan, &vi->vi_chans, list) { - remote = fwnode_graph_get_remote_node(fwnode, chan->portno, 0); + remote = fwnode_graph_get_remote_node(fwnode, chan->portnos[0], + 0); if (!remote) continue; @@ -1615,7 +1874,7 @@ static int tegra_vi_graph_init(struct tegra_vi *vi) if (ret < 0) { dev_err(vi->dev, "failed to register channel %d notifier: %d\n", - chan->portno, ret); + chan->portnos[0], ret); v4l2_async_notifier_cleanup(&chan->notifier); } } @@ -1666,11 +1925,14 @@ static int tegra_vi_init(struct host1x_client *client) if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { ret = tegra_vi_graph_init(vi); if (ret < 0) - goto free_chans; + goto cleanup_chans; } return 0; +cleanup_chans: + list_for_each_entry(chan, &vi->vi_chans, list) + tegra_channel_cleanup(chan); free_chans: list_for_each_entry_safe(chan, tmp, &vi->vi_chans, list) { list_del(&chan->list); diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index 7d6b7a6d0a45..a68e2c02c7b0 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -21,6 +21,10 @@ #include <media/v4l2-subdev.h> #include <media/videobuf2-v4l2.h> +#include "csi.h" + +#define V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY (V4L2_CTRL_CLASS_CAMERA | 0x1001) + #define TEGRA_MIN_WIDTH 32U #define TEGRA_MAX_WIDTH 32768U #define TEGRA_MIN_HEIGHT 32U @@ -31,6 +35,7 @@ #define TEGRA_IMAGE_FORMAT_DEF 32 #define MAX_FORMAT_NUM 64 +#define SURFACE_ALIGN_BYTES 64 enum tegra_vi_pg_mode { TEGRA_VI_PG_DISABLED = 0, @@ -151,10 +156,13 @@ struct tegra_vi_graph_entity { * @done: list of capture done queued buffers * @done_lock: protects the capture done queue list * - * @portno: VI channel port number + * @portnos: VI channel port numbers + * @totalports: total number of ports used for this channel + * @numgangports: number of ports combined together as a gang for capture * @of_node: device node of VI channel * * @ctrl_handler: V4L2 control handler of this video channel + * @syncpt_timeout_retry: syncpt timeout retry count for the capture * @fmts_bitmap: a bitmap for supported formats matching v4l2 subdev formats * @tpg_fmts_bitmap: a bitmap for supported TPG formats * @pg_mode: test pattern generator mode (disabled/direct/patch) @@ -168,10 +176,10 @@ struct tegra_vi_channel { struct media_pad pad; struct tegra_vi *vi; - struct host1x_syncpt *frame_start_sp; - struct host1x_syncpt *mw_ack_sp; + struct host1x_syncpt *frame_start_sp[GANG_PORTS_MAX]; + struct host1x_syncpt *mw_ack_sp[GANG_PORTS_MAX]; /* protects the cpu syncpoint increment */ - spinlock_t sp_incr_lock; + spinlock_t sp_incr_lock[GANG_PORTS_MAX]; struct task_struct *kthread_start_capture; wait_queue_head_t start_wait; @@ -190,10 +198,13 @@ struct tegra_vi_channel { /* protects the capture done queue list */ spinlock_t done_lock; - unsigned char portno; + unsigned char portnos[GANG_PORTS_MAX]; + u8 totalports; + u8 numgangports; struct device_node *of_node; struct v4l2_ctrl_handler ctrl_handler; + unsigned int syncpt_timeout_retry; DECLARE_BITMAP(fmts_bitmap, MAX_FORMAT_NUM); DECLARE_BITMAP(tpg_fmts_bitmap, MAX_FORMAT_NUM); enum tegra_vi_pg_mode pg_mode; @@ -216,7 +227,7 @@ struct tegra_channel_buffer { struct list_head queue; struct tegra_vi_channel *chan; dma_addr_t addr; - u32 mw_ack_sp_thresh; + u32 mw_ack_sp_thresh[GANG_PORTS_MAX]; }; /* diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/media/tegra-video/video.c index e50bd70575f3..d966b319553f 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -7,6 +7,8 @@ #include <linux/module.h> #include <linux/platform_device.h> +#include <media/v4l2-event.h> + #include "video.h" static void tegra_v4l2_dev_release(struct v4l2_device *v4l2_dev) @@ -24,6 +26,21 @@ static void tegra_v4l2_dev_release(struct v4l2_device *v4l2_dev) kfree(vid); } +static void tegra_v4l2_dev_notify(struct v4l2_subdev *sd, + unsigned int notification, void *arg) +{ + struct tegra_vi_channel *chan; + const struct v4l2_event *ev = arg; + + if (notification != V4L2_DEVICE_NOTIFY_EVENT) + return; + + chan = v4l2_get_subdev_hostdata(sd); + v4l2_event_queue(&chan->video, arg); + if (ev->type == V4L2_EVENT_SOURCE_CHANGE && vb2_is_streaming(&chan->queue)) + vb2_queue_error(&chan->queue); +} + static int host1x_video_probe(struct host1x_device *dev) { struct tegra_video_device *vid; @@ -49,6 +66,7 @@ static int host1x_video_probe(struct host1x_device *dev) vid->v4l2_dev.mdev = &vid->media_dev; vid->v4l2_dev.release = tegra_v4l2_dev_release; + vid->v4l2_dev.notify = tegra_v4l2_dev_notify; ret = v4l2_device_register(&dev->dev, &vid->v4l2_dev); if (ret < 0) { dev_err(&dev->dev, diff --git a/drivers/staging/media/zoran/zoran_driver.c b/drivers/staging/media/zoran/zoran_driver.c index d9f8b21edf6a..e8902f824d6c 100644 --- a/drivers/staging/media/zoran/zoran_driver.c +++ b/drivers/staging/media/zoran/zoran_driver.c @@ -1020,7 +1020,7 @@ int zoran_queue_init(struct zoran *zr, struct vb2_queue *vq) vq->buf_struct_size = sizeof(struct zr_buffer); vq->ops = &zr_video_qops; vq->mem_ops = &vb2_dma_contig_memops; - vq->gfp_flags = GFP_DMA32, + vq->gfp_flags = GFP_DMA32; vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; vq->min_buffers_needed = 9; vq->lock = &zr->lock; |