Merge branch 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr

Pull MIPS updates from Ralf Baechle:
 - Support for Imgtec's Aptiv family of MIPS cores.
 - Improved detection of BCM47xx configurations.
 - Fix hiberation for certain configurations.
 - Add support for the Chinese Loongson 3 CPU, a MIPS64 R2 core and
   systems.
 - Detection and support for the MIPS P5600 core.
 - A few more random fixes that didn't make 3.14.
 - Support for the EVA Extended Virtual Addressing
 - Switch Alchemy to the platform PATA driver
 - Complete unification of Alchemy support
 - Allow availability of I/O cache coherency to be runtime detected
 - Improvments to multiprocessing support for Imgtec platforms
 - A few microoptimizations
 - Cleanups of FPU support
 - Paul Gortmaker's fixes for the init stuff
 - Support for seccomp

* 'mips-for-linux-next' of git://git.linux-mips.org/pub/scm/ralf/upstream-sfr: (165 commits)
  MIPS: CPC: Use __raw_ memory access functions
  MIPS: CM: use __raw_ memory access functions
  MIPS: Fix warning when including smp-ops.h with CONFIG_SMP=n
  MIPS: Malta: GIC IPIs may be used without MT
  MIPS: smp-mt: Use common GIC IPI implementation
  MIPS: smp-cmp: Remove incorrect core number probe
  MIPS: Fix gigaton of warning building with microMIPS.
  MIPS: Fix core number detection for MT cores
  MIPS: MT: core_nvpes function to retrieve VPE count
  MIPS: Provide empty mips_mt_set_cpuoptions when CONFIG_MIPS_MT=n
  MIPS: Lasat: Replace del_timer by del_timer_sync
  MIPS: Malta: Setup PM I/O region on boot
  MIPS: Loongson: Add a Loongson-3 default config file
  MIPS: Loongson 3: Add CPU hotplug support
  MIPS: Loongson 3: Add Loongson-3 SMP support
  MIPS: Loongson: Add Loongson-3 Kconfig options
  MIPS: Loongson: Add swiotlb to support All-Memory DMA
  MIPS: Loongson 3: Add serial port support
  MIPS: Loongson 3: Add IRQ init and dispatch support
  MIPS: Loongson 3: Add HT-linked PCI support
  ...

3 files changed, 202 insertions, 6 deletions

diff --git a/drivers/edac/octeon_edac-lmc.c b/drivers/edac/octeon_edac-lmc.c
index 93412d6b3af1..4bd10f94f068 100644
--- a/drivers/edac/octeon_edac-lmc.c
+++ b/drivers/edac/octeon_edac-lmc.c
@@ -5,12 +5,16 @@
  *
  * Copyright (C) 2009 Wind River Systems,
  *   written by Ralf Baechle <ralf@linux-mips.org>
+ *
+ * Copyright (c) 2013 by Cisco Systems, Inc.
+ * All rights reserved.
  */
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/edac.h>
+#include <linux/ctype.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-lmcx-defs.h>
@@ -20,6 +24,18 @@
 
 #define OCTEON_MAX_MC 4
 
+#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
+
+struct octeon_lmc_pvt {
+	unsigned long inject;
+	unsigned long error_type;
+	unsigned long dimm;
+	unsigned long rank;
+	unsigned long bank;
+	unsigned long row;
+	unsigned long col;
+};
+
 static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
 {
 	union cvmx_lmcx_mem_cfg0 cfg0;
@@ -55,14 +71,31 @@ static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
 
 static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
 {
+	struct octeon_lmc_pvt *pvt = mci->pvt_info;
 	union cvmx_lmcx_int int_reg;
 	bool do_clear = false;
 	char msg[64];
 
-	int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
+	if (!pvt->inject)
+		int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
+	else {
+		if (pvt->error_type == 1)
+			int_reg.s.sec_err = 1;
+		if (pvt->error_type == 2)
+			int_reg.s.ded_err = 1;
+	}
+
 	if (int_reg.s.sec_err || int_reg.s.ded_err) {
 		union cvmx_lmcx_fadr fadr;
-		fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
+		if (likely(!pvt->inject))
+			fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
+		else {
+			fadr.cn61xx.fdimm = pvt->dimm;
+			fadr.cn61xx.fbunk = pvt->rank;
+			fadr.cn61xx.fbank = pvt->bank;
+			fadr.cn61xx.frow = pvt->row;
+			fadr.cn61xx.fcol = pvt->col;
+		}
 		snprintf(msg, sizeof(msg),
 			 "DIMM %d rank %d bank %d row %d col %d",
 			 fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
@@ -82,8 +115,128 @@ static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
 		int_reg.s.ded_err = -1;	/* Done, re-arm */
 		do_clear = true;
 	}
-	if (do_clear)
-		cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
+
+	if (do_clear) {
+		if (likely(!pvt->inject))
+			cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
+		else
+			pvt->inject = 0;
+	}
+}
+
+/************************ MC SYSFS parts ***********************************/
+
+/* Only a couple naming differences per template, so very similar */
+#define TEMPLATE_SHOW(reg)						\
+static ssize_t octeon_mc_inject_##reg##_show(struct device *dev,	\
+			       struct device_attribute *attr,		\
+			       char *data)				\
+{									\
+	struct mem_ctl_info *mci = to_mci(dev);				\
+	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
+	return sprintf(data, "%016llu\n", (u64)pvt->reg);		\
+}
+
+#define TEMPLATE_STORE(reg)						\
+static ssize_t octeon_mc_inject_##reg##_store(struct device *dev,	\
+			       struct device_attribute *attr,		\
+			       const char *data, size_t count)		\
+{									\
+	struct mem_ctl_info *mci = to_mci(dev);				\
+	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
+	if (isdigit(*data)) {						\
+		if (!kstrtoul(data, 0, &pvt->reg))			\
+			return count;					\
+	}								\
+	return 0;							\
+}
+
+TEMPLATE_SHOW(inject);
+TEMPLATE_STORE(inject);
+TEMPLATE_SHOW(dimm);
+TEMPLATE_STORE(dimm);
+TEMPLATE_SHOW(bank);
+TEMPLATE_STORE(bank);
+TEMPLATE_SHOW(rank);
+TEMPLATE_STORE(rank);
+TEMPLATE_SHOW(row);
+TEMPLATE_STORE(row);
+TEMPLATE_SHOW(col);
+TEMPLATE_STORE(col);
+
+static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
+					  struct device_attribute *attr,
+					  const char *data,
+					  size_t count)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct octeon_lmc_pvt *pvt = mci->pvt_info;
+
+	if (!strncmp(data, "single", 6))
+		pvt->error_type = 1;
+	else if (!strncmp(data, "double", 6))
+		pvt->error_type = 2;
+
+	return count;
+}
+
+static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
+					 struct device_attribute *attr,
+					 char *data)
+{
+	struct mem_ctl_info *mci = to_mci(dev);
+	struct octeon_lmc_pvt *pvt = mci->pvt_info;
+	if (pvt->error_type == 1)
+		return sprintf(data, "single");
+	else if (pvt->error_type == 2)
+		return sprintf(data, "double");
+
+	return 0;
+}
+
+static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
+static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
+static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
+static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
+static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
+static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_row_show, octeon_mc_inject_row_store);
+static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
+		   octeon_mc_inject_col_show, octeon_mc_inject_col_store);
+
+
+static int octeon_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
+{
+	int rc;
+
+	rc = device_create_file(&mci->dev, &dev_attr_inject);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_error_type);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_dimm);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_rank);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_bank);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_row);
+	if (rc < 0)
+		return rc;
+	rc = device_create_file(&mci->dev, &dev_attr_col);
+	if (rc < 0)
+		return rc;
+
+	return 0;
 }
 
 static int octeon_lmc_edac_probe(struct platform_device *pdev)
@@ -92,6 +245,8 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)
 	struct edac_mc_layer layers[1];
 	int mc = pdev->id;
 
+	opstate_init();
+
 	layers[0].type = EDAC_MC_LAYER_CHANNEL;
 	layers[0].size = 1;
 	layers[0].is_virt_csrow = false;
@@ -105,7 +260,7 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)
 			return 0;
 		}
 
-		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
+		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
 		if (!mci)
 			return -ENXIO;
 
@@ -122,6 +277,12 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)
 			return -ENXIO;
 		}
 
+		if (octeon_set_mc_sysfs_attributes(mci)) {
+			dev_err(&pdev->dev, "octeon_set_mc_sysfs_attributes() failed\n");
+			return -ENXIO;
+		}
+
+
 		cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
 		cfg0.s.intr_ded_ena = 0;	/* We poll */
 		cfg0.s.intr_sec_ena = 0;
@@ -137,7 +298,7 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)
 			return 0;
 		}
 
-		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);
+		mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
 		if (!mci)
 			return -ENXIO;
 
@@ -154,6 +315,12 @@ static int octeon_lmc_edac_probe(struct platform_device *pdev)
 			return -ENXIO;
 		}
 
+		if (octeon_set_mc_sysfs_attributes(mci)) {
+			dev_err(&pdev->dev, "octeon_set_mc_sysfs_attributes() failed\n");
+			return -ENXIO;
+		}
+
+
 		en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
 		en.s.intr_ded_ena = 0;	/* We poll */
 		en.s.intr_sec_ena = 0;
diff --git a/drivers/gpio/gpio-vr41xx.c b/drivers/gpio/gpio-vr41xx.c
index 9902732a382d..66cbcc108e62 100644
--- a/drivers/gpio/gpio-vr41xx.c
+++ b/drivers/gpio/gpio-vr41xx.c
@@ -81,6 +81,7 @@ static DEFINE_SPINLOCK(giu_lock);
 static unsigned long giu_flags;
 
 static void __iomem *giu_base;
+static struct gpio_chip vr41xx_gpio_chip;
 
 #define giu_read(offset)		readw(giu_base + (offset))
 #define giu_write(offset, value)	writew((value), giu_base + (offset))
@@ -135,12 +136,31 @@ static void unmask_giuint_low(struct irq_data *d)
 	giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
 }
 
+static unsigned int startup_giuint(struct irq_data *data)
+{
+	if (gpio_lock_as_irq(&vr41xx_gpio_chip, data->hwirq))
+		dev_err(vr41xx_gpio_chip.dev,
+			"unable to lock HW IRQ %lu for IRQ\n",
+			data->hwirq);
+	/* Satisfy the .enable semantics by unmasking the line */
+	unmask_giuint_low(data);
+	return 0;
+}
+
+static void shutdown_giuint(struct irq_data *data)
+{
+	mask_giuint_low(data);
+	gpio_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
+}
+
 static struct irq_chip giuint_low_irq_chip = {
 	.name		= "GIUINTL",
 	.irq_ack	= ack_giuint_low,
 	.irq_mask	= mask_giuint_low,
 	.irq_mask_ack	= mask_ack_giuint_low,
 	.irq_unmask	= unmask_giuint_low,
+	.irq_startup	= startup_giuint,
+	.irq_shutdown	= shutdown_giuint,
 };
 
 static void ack_giuint_high(struct irq_data *d)
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c
index aafb812d7ea6..67375a11d4bd 100644
--- a/drivers/spi/spi-au1550.c
+++ b/drivers/spi/spi-au1550.c
@@ -977,6 +977,15 @@ static int __init au1550_spi_init(void)
 	 * create memory device with 8 bits dev_devwidth
 	 * needed for proper byte ordering to spi fifo
 	 */
+	switch (alchemy_get_cputype()) {
+	case ALCHEMY_CPU_AU1550:
+	case ALCHEMY_CPU_AU1200:
+	case ALCHEMY_CPU_AU1300:
+		break;
+	default:
+		return -ENODEV;
+	}
+
 	if (usedma) {
 		ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
 		if (!ddma_memid)