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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2019-09-21 18:04:11 +0300
committerJerome Brunet <jbrunet@baylibre.com>2019-10-01 15:46:30 +0300
commit44b09b11b813b8550e6b976ea51593bc23bba8d1 (patch)
treeaf2503e988d13db4978beaa3a9533d8d41eabcb5 /drivers/regulator/twl6030-regulator.c
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff)
downloadlinux-44b09b11b813b8550e6b976ea51593bc23bba8d1.tar.xz
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
The meson-saradc driver manually sets the input clock for sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB, GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up to sar_adc_clk_sel which will let the common clock framework select the best matching parent clock if we want that. This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk drivers, which both also specify CLK_SET_RATE_PARENT. Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/regulator/twl6030-regulator.c')
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